rp/spi: enable rxdmae/txdmae only once at init.
see https://github.com/raspberrypi/pico-sdk/blob/master/src/rp2_common/hardware_spi/spi.c#L27-L28
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@ -90,10 +90,16 @@ impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
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w.set_sph(config.phase == Phase::CaptureOnSecondTransition);
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w.set_scr(postdiv);
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});
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p.cr1().write(|w| {
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w.set_sse(true); // enable
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// Always enable DREQ signals -- harmless if DMA is not listening
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p.dmacr().write(|reg| {
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reg.set_rxdmae(true);
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reg.set_txdmae(true);
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});
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// finally, enable.
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p.cr1().write(|w| w.set_sse(true));
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if let Some(pin) = &clk {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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@ -329,9 +335,6 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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let tx_ch = self.tx_dma.as_mut().unwrap();
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let tx_transfer = unsafe {
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self.inner.regs().dmacr().modify(|reg| {
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reg.set_txdmae(true);
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});
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::write(tx_ch, buffer, self.inner.regs().dr().ptr() as *mut _, T::TX_DREQ)
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@ -354,13 +357,6 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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}
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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unsafe {
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self.inner.regs().dmacr().write(|reg| {
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reg.set_rxdmae(true);
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reg.set_txdmae(true);
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})
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};
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// Start RX first. Transfer starts when TX starts, if RX
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// is not started yet we might lose bytes.
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let rx_ch = self.rx_dma.as_mut().unwrap();
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@ -392,13 +388,6 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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let (_, tx_len) = crate::dma::slice_ptr_parts(tx_ptr);
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let (_, rx_len) = crate::dma::slice_ptr_parts_mut(rx_ptr);
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unsafe {
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self.inner.regs().dmacr().write(|reg| {
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reg.set_rxdmae(true);
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reg.set_txdmae(true);
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})
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};
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// Start RX first. Transfer starts when TX starts, if RX
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// is not started yet we might lose bytes.
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let rx_ch = self.rx_dma.as_mut().unwrap();
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