Merge pull request #301 from thalesfragoso/i2cv2-dma
i2c-v2: Implement write_dma and write_dma_vectored
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
de77dc11ca
@ -1,9 +1,11 @@
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#![macro_use]
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use embassy::interrupt::Interrupt;
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#[cfg_attr(i2c_v1, path = "v1.rs")]
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#[cfg_attr(i2c_v2, path = "v2.rs")]
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mod _version;
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use crate::peripherals;
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use crate::{dma, peripherals};
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pub use _version::*;
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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@ -18,11 +20,14 @@ pub enum Error {
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}
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pub(crate) mod sealed {
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use super::dma;
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use crate::gpio::Pin;
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use crate::rcc::RccPeripheral;
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pub trait Instance: RccPeripheral {
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fn regs() -> &'static crate::pac::i2c::I2c;
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fn regs() -> crate::pac::i2c::I2c;
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fn state_number() -> usize;
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}
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pub trait SclPin<T: Instance>: Pin {
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@ -32,23 +37,61 @@ pub(crate) mod sealed {
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pub trait SdaPin<T: Instance>: Pin {
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fn af_num(&self) -> u8;
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}
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pub trait RxDma<T: Instance> {
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fn request(&self) -> dma::Request;
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}
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pub trait Instance: sealed::Instance + 'static {}
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pub trait TxDma<T: Instance> {
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fn request(&self) -> dma::Request;
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}
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}
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pub trait Instance: sealed::Instance + 'static {
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type Interrupt: Interrupt;
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}
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pub trait SclPin<T: Instance>: sealed::SclPin<T> + 'static {}
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pub trait SdaPin<T: Instance>: sealed::SdaPin<T> + 'static {}
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crate::pac::peripherals!(
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(i2c, $inst:ident) => {
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pub trait RxDma<T: Instance>: sealed::RxDma<T> + dma::Channel {}
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pub trait TxDma<T: Instance>: sealed::TxDma<T> + dma::Channel {}
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macro_rules! i2c_state {
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(I2C1) => {
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0
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};
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(I2C2) => {
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1
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};
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(I2C3) => {
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2
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};
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(I2C4) => {
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3
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};
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(I2C5) => {
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4
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};
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}
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crate::pac::interrupts!(
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($inst:ident, i2c, $block:ident, EV, $irq:ident) => {
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impl sealed::Instance for peripherals::$inst {
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fn regs() -> &'static crate::pac::i2c::I2c {
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&crate::pac::$inst
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fn regs() -> crate::pac::i2c::I2c {
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crate::pac::$inst
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}
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fn state_number() -> usize {
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i2c_state!($inst)
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}
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}
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impl Instance for peripherals::$inst {}
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impl Instance for peripherals::$inst {
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type Interrupt = crate::interrupt::$irq;
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}
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};
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);
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@ -74,3 +117,39 @@ crate::pac::peripheral_pins!(
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impl_pin!($inst, $pin, SclPin, $af);
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};
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);
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macro_rules! impl_dma {
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($inst:ident, {dmamux: $dmamux:ident}, $signal:ident, $request:expr) => {
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impl<T> sealed::$signal<peripherals::$inst> for T
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where
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T: crate::dma::MuxChannel<Mux = crate::dma::$dmamux>,
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{
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fn request(&self) -> dma::Request {
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$request
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}
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}
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impl<T> $signal<peripherals::$inst> for T where
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T: crate::dma::MuxChannel<Mux = crate::dma::$dmamux>
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{
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}
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};
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($inst:ident, {channel: $channel:ident}, $signal:ident, $request:expr) => {
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impl sealed::$signal<peripherals::$inst> for peripherals::$channel {
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fn request(&self) -> dma::Request {
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$request
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}
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}
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impl $signal<peripherals::$inst> for peripherals::$channel {}
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};
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}
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crate::pac::peripheral_dma_channels! {
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($peri:ident, i2c, $kind:ident, RX, $channel:tt, $request:expr) => {
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impl_dma!($peri, $channel, RxDma, $request);
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};
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($peri:ident, i2c, $kind:ident, TX, $channel:tt, $request:expr) => {
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impl_dma!($peri, $channel, TxDma, $request);
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};
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}
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@ -1,32 +1,66 @@
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use core::cmp;
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use core::task::Poll;
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use atomic_polyfill::{AtomicUsize, Ordering};
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use embassy::interrupt::InterruptExt;
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use embassy::util::{AtomicWaker, OnDrop, Unborrow};
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use embassy_hal_common::unborrow;
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use embedded_hal::blocking::i2c::Read;
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use embedded_hal::blocking::i2c::Write;
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use embedded_hal::blocking::i2c::WriteRead;
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use futures::future::poll_fn;
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use crate::dma::NoDma;
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use crate::i2c::{Error, Instance, SclPin, SdaPin};
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use crate::pac;
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use crate::pac::gpio::vals::{Afr, Moder, Ot};
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use crate::pac::gpio::Gpio;
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use crate::pac::i2c;
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use crate::time::Hertz;
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pub struct I2c<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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const I2C_COUNT: usize = pac::peripheral_count!(i2c);
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pub struct State {
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waker: [AtomicWaker; I2C_COUNT],
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chunks_transferred: [AtomicUsize; I2C_COUNT],
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}
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impl<'d, T: Instance> I2c<'d, T> {
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impl State {
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const fn new() -> Self {
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const AW: AtomicWaker = AtomicWaker::new();
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const CT: AtomicUsize = AtomicUsize::new(0);
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Self {
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waker: [AW; I2C_COUNT],
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chunks_transferred: [CT; I2C_COUNT],
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}
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}
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}
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static STATE: State = State::new();
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pub struct I2c<'d, T: Instance, TXDMA = NoDma, RXDMA = NoDma> {
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phantom: PhantomData<&'d mut T>,
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tx_dma: TXDMA,
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#[allow(dead_code)]
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rx_dma: RXDMA,
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}
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impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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pub fn new<F>(
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_peri: impl Unborrow<Target = T> + 'd,
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scl: impl Unborrow<Target = impl SclPin<T>>,
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sda: impl Unborrow<Target = impl SdaPin<T>>,
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scl: impl Unborrow<Target = impl SclPin<T>> + 'd,
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sda: impl Unborrow<Target = impl SdaPin<T>> + 'd,
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irq: impl Unborrow<Target = T::Interrupt> + 'd,
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tx_dma: impl Unborrow<Target = TXDMA> + 'd,
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rx_dma: impl Unborrow<Target = RXDMA> + 'd,
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freq: F,
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) -> Self
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where
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F: Into<Hertz>,
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{
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unborrow!(scl, sda);
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unborrow!(irq, scl, sda, tx_dma, rx_dma);
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T::enable();
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@ -60,11 +94,33 @@ impl<'d, T: Instance> I2c<'d, T> {
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});
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}
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irq.set_handler(Self::on_interrupt);
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irq.unpend();
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irq.enable();
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Self {
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phantom: PhantomData,
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tx_dma,
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rx_dma,
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}
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}
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unsafe fn on_interrupt(_: *mut ()) {
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let regs = T::regs();
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let isr = regs.isr().read();
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if isr.tcr() || isr.tc() {
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let n = T::state_number();
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STATE.chunks_transferred[n].fetch_add(1, Ordering::Relaxed);
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STATE.waker[n].wake();
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}
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// The flag can only be cleared by writting to nbytes, we won't do that here, so disable
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// the interrupt
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critical_section::with(|_| {
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regs.cr1().modify(|w| w.set_tcie(false));
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});
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}
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unsafe fn configure_pin(block: Gpio, pin: usize, af_num: u8) {
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let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) };
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block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE));
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@ -114,13 +170,13 @@ impl<'d, T: Instance> I2c<'d, T> {
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}
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}
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fn master_write(&mut self, address: u8, length: usize, stop: Stop, reload: bool) {
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unsafe fn master_write(address: u8, length: usize, stop: Stop, reload: bool) {
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assert!(length < 256 && length > 0);
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// Wait for any previous address sequence to end
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// automatically. This could be up to 50% of a bus
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// cycle (ie. up to 0.5/freq)
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while unsafe { T::regs().cr2().read().start() == i2c::vals::Start::START } {}
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while T::regs().cr2().read().start() == i2c::vals::Start::START {}
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let reload = if reload {
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i2c::vals::Reload::NOTCOMPLETED
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@ -131,7 +187,6 @@ impl<'d, T: Instance> I2c<'d, T> {
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// Set START and prepare to send `bytes`. The
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// START bit can be set even if the bus is BUSY or
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// I2C is in slave mode.
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unsafe {
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T::regs().cr2().modify(|w| {
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w.set_sadd((address << 1 | 0) as u16);
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w.set_add10(i2c::vals::Add::BIT7);
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@ -142,12 +197,11 @@ impl<'d, T: Instance> I2c<'d, T> {
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w.set_reload(reload);
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});
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}
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}
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fn master_continue(&mut self, length: usize, reload: bool) {
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unsafe fn master_continue(length: usize, reload: bool) {
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assert!(length < 256 && length > 0);
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while unsafe { !T::regs().isr().read().tcr() } {}
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while !T::regs().isr().read().tcr() {}
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let reload = if reload {
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i2c::vals::Reload::NOTCOMPLETED
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@ -155,13 +209,11 @@ impl<'d, T: Instance> I2c<'d, T> {
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i2c::vals::Reload::COMPLETED
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};
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unsafe {
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T::regs().cr2().modify(|w| {
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w.set_nbytes(length as u8);
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w.set_reload(reload);
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});
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}
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}
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fn flush_txdr(&self) {
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//if $i2c.isr.read().txis().bit_is_set() {
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@ -265,7 +317,10 @@ impl<'d, T: Instance> I2c<'d, T> {
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for (number, chunk) in buffer.chunks_mut(255).enumerate() {
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if number != 0 {
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self.master_continue(chunk.len(), number != last_chunk_idx);
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// NOTE(unsafe) We have &mut self
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unsafe {
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Self::master_continue(chunk.len(), number != last_chunk_idx);
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}
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}
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for byte in chunk {
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@ -292,16 +347,22 @@ impl<'d, T: Instance> I2c<'d, T> {
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// I2C start
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//
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// ST SAD+W
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self.master_write(
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// NOTE(unsafe) We have &mut self
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unsafe {
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Self::master_write(
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address,
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bytes.len().min(255),
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Stop::Software,
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last_chunk_idx != 0,
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);
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}
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for (number, chunk) in bytes.chunks(255).enumerate() {
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if number != 0 {
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self.master_continue(chunk.len(), number != last_chunk_idx);
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// NOTE(unsafe) We have &mut self
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unsafe {
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Self::master_continue(chunk.len(), number != last_chunk_idx);
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}
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}
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for byte in chunk {
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@ -324,6 +385,130 @@ impl<'d, T: Instance> I2c<'d, T> {
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Ok(())
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}
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async fn write_dma_internal(
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&mut self,
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address: u8,
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bytes: &[u8],
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first_slice: bool,
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last_slice: bool,
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) -> Result<(), Error>
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where
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TXDMA: crate::i2c::TxDma<T>,
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{
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let total_len = bytes.len();
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let completed_chunks = total_len / 255;
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let total_chunks = if completed_chunks * 255 == total_len {
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completed_chunks
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} else {
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completed_chunks + 1
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};
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let dma_transfer = unsafe {
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let regs = T::regs();
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regs.cr1().modify(|w| {
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w.set_txdmaen(true);
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if first_slice {
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w.set_tcie(true);
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}
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});
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let dst = regs.txdr().ptr() as *mut u8;
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let ch = &mut self.tx_dma;
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ch.write(ch.request(), bytes, dst)
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};
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let state_number = T::state_number();
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STATE.chunks_transferred[state_number].store(0, Ordering::Relaxed);
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let mut remaining_len = total_len;
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let _on_drop = OnDrop::new(|| {
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let regs = T::regs();
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unsafe {
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regs.cr1().modify(|w| {
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if last_slice {
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w.set_txdmaen(false);
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}
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w.set_tcie(false);
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})
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}
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});
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// NOTE(unsafe) self.tx_dma does not fiddle with the i2c registers
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if first_slice {
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unsafe {
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Self::master_write(
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address,
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total_len.min(255),
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Stop::Software,
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(total_chunks != 1) || !last_slice,
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);
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}
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} else {
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unsafe {
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Self::master_continue(total_len.min(255), (total_chunks != 1) || !last_slice);
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T::regs().cr1().modify(|w| w.set_tcie(true));
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}
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}
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poll_fn(|cx| {
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STATE.waker[state_number].register(cx.waker());
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let chunks_transferred = STATE.chunks_transferred[state_number].load(Ordering::Relaxed);
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if chunks_transferred == total_chunks {
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return Poll::Ready(());
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} else if chunks_transferred != 0 {
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remaining_len = remaining_len.saturating_sub(255);
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let last_piece = (chunks_transferred + 1 == total_chunks) && last_slice;
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// NOTE(unsafe) self.tx_dma does not fiddle with the i2c registers
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unsafe {
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Self::master_continue(remaining_len.min(255), !last_piece);
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T::regs().cr1().modify(|w| w.set_tcie(true));
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}
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}
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Poll::Pending
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})
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.await;
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dma_transfer.await;
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if last_slice {
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// This should be done already
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self.wait_tc()?;
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self.master_stop();
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}
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Ok(())
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}
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pub async fn write_dma(&mut self, address: u8, bytes: &[u8]) -> Result<(), Error>
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where
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TXDMA: crate::i2c::TxDma<T>,
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{
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self.write_dma_internal(address, bytes, true, true).await
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}
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pub async fn write_dma_vectored(&mut self, address: u8, bytes: &[&[u8]]) -> Result<(), Error>
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where
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TXDMA: crate::i2c::TxDma<T>,
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{
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if bytes.is_empty() {
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return Err(Error::ZeroLengthTransfer);
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}
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let mut iter = bytes.iter();
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let mut first = true;
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let mut current = iter.next();
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while let Some(c) = current {
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let next = iter.next();
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let is_last = next.is_none();
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self.write_dma_internal(address, c, first, is_last).await?;
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first = false;
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current = next;
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}
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Ok(())
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}
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pub fn write_vectored(&mut self, address: u8, bytes: &[&[u8]]) -> Result<(), Error> {
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if bytes.is_empty() {
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return Err(Error::ZeroLengthTransfer);
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@ -331,12 +516,15 @@ impl<'d, T: Instance> I2c<'d, T> {
|
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let first_length = bytes[0].len();
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let last_slice_index = bytes.len() - 1;
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|
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self.master_write(
|
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// NOTE(unsafe) We have &mut self
|
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unsafe {
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Self::master_write(
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address,
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first_length.min(255),
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Stop::Software,
|
||||
(first_length > 255) || (last_slice_index != 0),
|
||||
);
|
||||
}
|
||||
|
||||
for (idx, slice) in bytes.iter().enumerate() {
|
||||
let slice_len = slice.len();
|
||||
@ -349,19 +537,25 @@ impl<'d, T: Instance> I2c<'d, T> {
|
||||
let last_chunk_idx = total_chunks.saturating_sub(1);
|
||||
|
||||
if idx != 0 {
|
||||
self.master_continue(
|
||||
// NOTE(unsafe) We have &mut self
|
||||
unsafe {
|
||||
Self::master_continue(
|
||||
slice_len.min(255),
|
||||
(idx != last_slice_index) || (slice_len > 255),
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
for (number, chunk) in slice.chunks(255).enumerate() {
|
||||
if number != 0 {
|
||||
self.master_continue(
|
||||
// NOTE(unsafe) We have &mut self
|
||||
unsafe {
|
||||
Self::master_continue(
|
||||
chunk.len(),
|
||||
(number != last_chunk_idx) || (idx != last_slice_index),
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
for byte in chunk {
|
||||
// Wait until we are allowed to send data
|
||||
|
||||
Loading…
Reference in New Issue
Block a user