stm32: centralize enabling pwr, syscfg, flash.

embassy-stm32/src/rcc/f2.rs

@@ -4,7 +4,7 @@ use core::ops::{Div, Mul};
 pub use super::bus::{AHBPrescaler, APBPrescaler};
 use crate::pac::flash::vals::Latency;
 use crate::pac::rcc::vals::{Pllp, Pllsrc, Sw};
-use crate::pac::{FLASH, PWR, RCC};
+use crate::pac::{FLASH, RCC};
 use crate::rcc::bd::BackupDomain;
 use crate::rcc::{set_freqs, Clocks};
 use crate::rtc::RtcClockSource;
@@ -435,9 +435,6 @@ pub(crate) unsafe fn init(config: Config) {
         RCC.cr().modify(|w| w.set_hsion(false));
     }
 
-    RCC.apb1enr().modify(|w| w.set_pwren(true));
-    PWR.cr().read();
-
     BackupDomain::configure_ls(
         config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
         config.lsi,

embassy-stm32/src/rcc/f4.rs

@@ -3,7 +3,6 @@ use core::marker::PhantomData;
 use embassy_hal_internal::into_ref;
 use stm32_metapac::rcc::vals::{Mco1, Mco2, Mcopre};
 
-use super::sealed::RccPeripheral;
 use crate::gpio::sealed::AFType;
 use crate::gpio::Speed;
 use crate::pac::rcc::vals::{Hpre, Ppre, Sw};
@@ -332,8 +331,6 @@ fn flash_setup(sysclk: u32) {
 }
 
 pub(crate) unsafe fn init(config: Config) {
-    crate::peripherals::PWR::enable();
-
     let pllsrcclk = config.hse.map(|hse| hse.0).unwrap_or(HSI_FREQ.0);
     let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
     let sysclk_on_pll = sysclk != pllsrcclk;

embassy-stm32/src/rcc/f7.rs

@@ -1,4 +1,3 @@
-use super::sealed::RccPeripheral;
 use crate::pac::pwr::vals::Vos;
 use crate::pac::rcc::vals::{Hpre, Ppre, Sw};
 use crate::pac::{FLASH, PWR, RCC};
@@ -111,8 +110,6 @@ fn flash_setup(sysclk: u32) {
 }
 
 pub(crate) unsafe fn init(config: Config) {
-    crate::peripherals::PWR::enable();
-
     if let Some(hse) = config.hse {
         if config.bypass_hse {
             assert!((max::HSE_BYPASS_MIN..=max::HSE_BYPASS_MAX).contains(&hse.0));
@@ -212,10 +209,7 @@ pub(crate) unsafe fn init(config: Config) {
     if plls.use_pll {
         RCC.cr().modify(|w| w.set_pllon(false));
 
-        // enable PWR and setup VOSScale
-
-        RCC.apb1enr().modify(|w| w.set_pwren(true));
-
+        // setup VOSScale
         let vos_scale = if sysclk <= 144_000_000 {
             3
         } else if sysclk <= 168_000_000 {

embassy-stm32/src/rcc/h.rs

@@ -215,11 +215,6 @@ impl Default for Config {
 }
 
 pub(crate) unsafe fn init(config: Config) {
-    #[cfg(stm32h7)]
-    RCC.apb4enr().modify(|w| w.set_syscfgen(true));
-    #[cfg(stm32h5)]
-    RCC.apb3enr().modify(|w| w.set_sbsen(true));
-
     // NB. The lower bytes of CR3 can only be written once after
     // POR, and must be written with a valid combination. Refer to
     // RM0433 Rev 7 6.8.4. This is partially enforced by dropping

embassy-stm32/src/rcc/l0.rs

@@ -283,13 +283,6 @@ pub(crate) unsafe fn init(config: Config) {
 
     #[cfg(crs)]
     if config.enable_hsi48 {
-        // Reset SYSCFG peripheral
-        RCC.apb2rstr().modify(|w| w.set_syscfgrst(true));
-        RCC.apb2rstr().modify(|w| w.set_syscfgrst(false));
-
-        // Enable SYSCFG peripheral
-        RCC.apb2enr().modify(|w| w.set_syscfgen(true));
-
         // Reset CRS peripheral
         RCC.apb1rstr().modify(|w| w.set_crsrst(true));
         RCC.apb1rstr().modify(|w| w.set_crsrst(false));

embassy-stm32/src/rcc/l4.rs

@@ -409,8 +409,6 @@ pub(crate) unsafe fn init(config: Config) {
         while RCC.cfgr().read().sws() != Sw::MSI {}
     }
 
-    RCC.apb1enr1().modify(|w| w.set_pwren(true));
-
     BackupDomain::configure_ls(config.rtc_mux, config.lsi, config.lse.map(|_| Default::default()));
 
     let (sys_clk, sw) = match config.mux {
@@ -608,8 +606,6 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
-    RCC.apb1enr1().modify(|w| w.set_pwren(true));
-
     set_freqs(Clocks {
         sys: Hertz(sys_clk),
         ahb1: Hertz(ahb_freq),