stm32: centralize enabling pwr, syscfg, flash.

embassy-stm32/Cargo.toml

@@ -59,7 +59,7 @@ sdio-host = "0.5.0"
 embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
 critical-section = "1.1"
 atomic-polyfill = "1.0.1"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-2bdbec6dc0fd5fcef5d9fb473de1fc5050a054c2" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-74025d56c0ba061703f360558ce80f51d1165060" }
 vcell = "0.1.3"
 bxcan = "0.7.0"
 nb = "1.0.0"
@@ -78,7 +78,7 @@ critical-section = { version = "1.1", features = ["std"] }
 [build-dependencies]
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-2bdbec6dc0fd5fcef5d9fb473de1fc5050a054c2", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-74025d56c0ba061703f360558ce80f51d1165060", default-features = false, features = ["metadata"]}
 
 [features]
 default = ["rt"]

embassy-stm32/src/eth/v1/mod.rs

@@ -129,7 +129,6 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
 
         #[cfg(any(eth_v1b, eth_v1c))]
         critical_section::with(|_| {
-            RCC.apb2enr().modify(|w| w.set_syscfgen(true));
             RCC.ahb1enr().modify(|w| {
                 w.set_ethen(true);
                 w.set_ethtxen(true);

embassy-stm32/src/eth/v2/mod.rs

@@ -80,7 +80,6 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
         // Enable the necessary Clocks
         #[cfg(not(rcc_h5))]
         critical_section::with(|_| {
-            crate::pac::RCC.apb4enr().modify(|w| w.set_syscfgen(true));
             crate::pac::RCC.ahb1enr().modify(|w| {
                 w.set_eth1macen(true);
                 w.set_eth1txen(true);

embassy-stm32/src/exti.rs

@@ -371,9 +371,4 @@ pub(crate) unsafe fn init() {
     use crate::interrupt::typelevel::Interrupt;
 
     foreach_exti_irq!(enable_irq);
-
-    #[cfg(not(any(rcc_wb, rcc_wl5, rcc_wle, stm32f1, exti_h5, exti_h50)))]
-    <crate::peripherals::SYSCFG as crate::rcc::sealed::RccPeripheral>::enable();
-    #[cfg(stm32f1)]
-    <crate::peripherals::AFIO as crate::rcc::sealed::RccPeripheral>::enable();
 }

embassy-stm32/src/gpio.rs

@@ -758,6 +758,9 @@ foreach_pin!(
 );
 
 pub(crate) unsafe fn init() {
+    #[cfg(afio)]
+    <crate::peripherals::AFIO as crate::rcc::sealed::RccPeripheral>::enable();
+
     crate::_generated::init_gpio();
 }
 

embassy-stm32/src/lib.rs

@@ -117,6 +117,7 @@ pub(crate) use stm32_metapac as pac;
 use crate::interrupt::Priority;
 #[cfg(feature = "rt")]
 pub use crate::pac::NVIC_PRIO_BITS;
+use crate::rcc::sealed::RccPeripheral;
 
 #[non_exhaustive]
 pub struct Config {
@@ -179,6 +180,15 @@ pub fn init(config: Config) -> Peripherals {
         });
     }
 
+    #[cfg(not(any(stm32f1, stm32h5, stm32wb, stm32wl)))]
+    peripherals::SYSCFG::enable();
+    #[cfg(sbs)]
+    peripherals::SBS::enable();
+    #[cfg(not(any(stm32h5, stm32h7, stm32wb, stm32wl)))]
+    peripherals::PWR::enable();
+    #[cfg(not(any(stm32f2, stm32f4, stm32f7, stm32l0, stm32h5, stm32h7)))]
+    peripherals::FLASH::enable();
+
     unsafe {
         gpio::init();
         dma::init(

embassy-stm32/src/rcc/f2.rs

@@ -4,7 +4,7 @@ use core::ops::{Div, Mul};
 pub use super::bus::{AHBPrescaler, APBPrescaler};
 use crate::pac::flash::vals::Latency;
 use crate::pac::rcc::vals::{Pllp, Pllsrc, Sw};
-use crate::pac::{FLASH, PWR, RCC};
+use crate::pac::{FLASH, RCC};
 use crate::rcc::bd::BackupDomain;
 use crate::rcc::{set_freqs, Clocks};
 use crate::rtc::RtcClockSource;
@@ -435,9 +435,6 @@ pub(crate) unsafe fn init(config: Config) {
         RCC.cr().modify(|w| w.set_hsion(false));
     }
 
-    RCC.apb1enr().modify(|w| w.set_pwren(true));
-    PWR.cr().read();
-
     BackupDomain::configure_ls(
         config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
         config.lsi,

embassy-stm32/src/rcc/f4.rs

@@ -3,7 +3,6 @@ use core::marker::PhantomData;
 use embassy_hal_internal::into_ref;
 use stm32_metapac::rcc::vals::{Mco1, Mco2, Mcopre};
 
-use super::sealed::RccPeripheral;
 use crate::gpio::sealed::AFType;
 use crate::gpio::Speed;
 use crate::pac::rcc::vals::{Hpre, Ppre, Sw};
@@ -332,8 +331,6 @@ fn flash_setup(sysclk: u32) {
 }
 
 pub(crate) unsafe fn init(config: Config) {
-    crate::peripherals::PWR::enable();
-
     let pllsrcclk = config.hse.map(|hse| hse.0).unwrap_or(HSI_FREQ.0);
     let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
     let sysclk_on_pll = sysclk != pllsrcclk;

embassy-stm32/src/rcc/f7.rs

@@ -1,4 +1,3 @@
-use super::sealed::RccPeripheral;
 use crate::pac::pwr::vals::Vos;
 use crate::pac::rcc::vals::{Hpre, Ppre, Sw};
 use crate::pac::{FLASH, PWR, RCC};
@@ -111,8 +110,6 @@ fn flash_setup(sysclk: u32) {
 }
 
 pub(crate) unsafe fn init(config: Config) {
-    crate::peripherals::PWR::enable();
-
     if let Some(hse) = config.hse {
         if config.bypass_hse {
             assert!((max::HSE_BYPASS_MIN..=max::HSE_BYPASS_MAX).contains(&hse.0));
@@ -212,10 +209,7 @@ pub(crate) unsafe fn init(config: Config) {
     if plls.use_pll {
         RCC.cr().modify(|w| w.set_pllon(false));
 
-        // enable PWR and setup VOSScale
+        // setup VOSScale
-
-        RCC.apb1enr().modify(|w| w.set_pwren(true));
-
         let vos_scale = if sysclk <= 144_000_000 {
             3
         } else if sysclk <= 168_000_000 {

embassy-stm32/src/rcc/h.rs

@@ -215,11 +215,6 @@ impl Default for Config {
 }
 
 pub(crate) unsafe fn init(config: Config) {
-    #[cfg(stm32h7)]
-    RCC.apb4enr().modify(|w| w.set_syscfgen(true));
-    #[cfg(stm32h5)]
-    RCC.apb3enr().modify(|w| w.set_sbsen(true));
-
     // NB. The lower bytes of CR3 can only be written once after
     // POR, and must be written with a valid combination. Refer to
     // RM0433 Rev 7 6.8.4. This is partially enforced by dropping

embassy-stm32/src/rcc/l0.rs

@@ -283,13 +283,6 @@ pub(crate) unsafe fn init(config: Config) {
 
     #[cfg(crs)]
     if config.enable_hsi48 {
-        // Reset SYSCFG peripheral
-        RCC.apb2rstr().modify(|w| w.set_syscfgrst(true));
-        RCC.apb2rstr().modify(|w| w.set_syscfgrst(false));
-
-        // Enable SYSCFG peripheral
-        RCC.apb2enr().modify(|w| w.set_syscfgen(true));
-
         // Reset CRS peripheral
         RCC.apb1rstr().modify(|w| w.set_crsrst(true));
         RCC.apb1rstr().modify(|w| w.set_crsrst(false));

embassy-stm32/src/rcc/l4.rs

@@ -409,8 +409,6 @@ pub(crate) unsafe fn init(config: Config) {
         while RCC.cfgr().read().sws() != Sw::MSI {}
     }
 
-    RCC.apb1enr1().modify(|w| w.set_pwren(true));
-
     BackupDomain::configure_ls(config.rtc_mux, config.lsi, config.lse.map(|_| Default::default()));
 
     let (sys_clk, sw) = match config.mux {
@@ -608,8 +606,6 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
-    RCC.apb1enr1().modify(|w| w.set_pwren(true));
-
     set_freqs(Clocks {
         sys: Hertz(sys_clk),
         ahb1: Hertz(ahb_freq),

embassy-stm32/src/rtc/v2.rs

@@ -295,20 +295,6 @@ impl sealed::Instance for crate::peripherals::RTC {
             // read to allow the pwr clock to enable
             crate::pac::PWR.cr1().read();
         }
-        #[cfg(any(rtc_v2f2))]
-        {
-            // enable peripheral clock for communication
-            crate::pac::RCC.apb1enr().modify(|w| w.set_pwren(true));
-
-            // read to allow the pwr clock to enable
-            crate::pac::PWR.cr().read();
-        }
-
-        #[cfg(any(rtc_v2f0, rtc_v2l0))]
-        {
-            // enable peripheral clock for communication
-            crate::pac::RCC.apb1enr().modify(|w| w.set_pwren(true));
-        }
     }
 
     fn read_backup_register(rtc: &Rtc, register: usize) -> Option<u32> {

embassy-stm32/src/usb/usb.rs

@@ -264,10 +264,7 @@ impl<'d, T: Instance> Driver<'d, T> {
         let regs = T::regs();
 
         #[cfg(stm32l5)]
-        {
+        crate::pac::PWR.cr2().modify(|w| w.set_usv(true));
-            crate::peripherals::PWR::enable();
-            crate::pac::PWR.cr2().modify(|w| w.set_usv(true));
-        }
 
         #[cfg(pwr_h5)]
         crate::pac::PWR.usbscr().modify(|w| w.set_usb33sv(true));

embassy-stm32/src/usb_otg/usb.rs

@@ -540,10 +540,7 @@ impl<'d, T: Instance> Bus<'d, T> {
 impl<'d, T: Instance> Bus<'d, T> {
     fn init(&mut self) {
         #[cfg(stm32l4)]
-        {
+        critical_section::with(|_| crate::pac::PWR.cr2().modify(|w| w.set_usv(true)));
-            crate::peripherals::PWR::enable();
-            critical_section::with(|_| crate::pac::PWR.cr2().modify(|w| w.set_usv(true)));
-        }
 
         #[cfg(stm32f7)]
         {
@@ -618,15 +615,10 @@ impl<'d, T: Instance> Bus<'d, T> {
         {
             // Enable USB power
             critical_section::with(|_| {
-                crate::pac::RCC.ahb3enr().modify(|w| {
-                    w.set_pwren(true);
-                });
-                cortex_m::asm::delay(2);
-
                 crate::pac::PWR.svmcr().modify(|w| {
                     w.set_usv(true);
                     w.set_uvmen(true);
-                });
+                })
             });
 
             // Wait for USB power to stabilize