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Fix bufferedUart read and write tests

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This commit is contained in:
Mathias 2022-09-27 07:45:10 +02:00
parent 93354b812c
commit e129a97d48
3 changed files with 51 additions and 53 deletions
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22
embassy-rp/src/uart/buffered.rs
View File

@ -228,39 +228,39 @@ where
fn on_interrupt(&mut self) { fn on_interrupt(&mut self) {
let r = T::regs(); let r = T::regs();
unsafe { unsafe {
let ris = r.uartmis().read(); let ris = r.uartris().read();
// Clear interrupt flags // Clear interrupt flags
r.uarticr().modify(|w| { r.uarticr().modify(|w| {
w.set_rxic(true); w.set_rxic(true);
w.set_rtic(true); w.set_rtic(true);
}); });
if ris.rxmis() { if ris.peris() {
if ris.pemis() {
warn!("Parity error"); warn!("Parity error");
r.uarticr().modify(|w| { r.uarticr().modify(|w| {
w.set_peic(true); w.set_peic(true);
}); });
} }
if ris.femis() { if ris.feris() {
warn!("Framing error"); warn!("Framing error");
r.uarticr().modify(|w| { r.uarticr().modify(|w| {
w.set_feic(true); w.set_feic(true);
}); });
} }
if ris.bemis() { if ris.beris() {
warn!("Break error"); warn!("Break error");
r.uarticr().modify(|w| { r.uarticr().modify(|w| {
w.set_beic(true); w.set_beic(true);
}); });
} }
if ris.oemis() { if ris.oeris() {
warn!("Overrun error"); warn!("Overrun error");
r.uarticr().modify(|w| { r.uarticr().modify(|w| {
w.set_oeic(true); w.set_oeic(true);
}); });
} }
if !r.uartfr().read().rxfe() {
let buf = self.buf.push_buf(); let buf = self.buf.push_buf();
if !buf.is_empty() { if !buf.is_empty() {
buf[0] = r.uartdr().read().data(); buf[0] = r.uartdr().read().data();
@ -274,7 +274,7 @@ where
} }
} }
if ris.rtmis() { if ris.rtris() {
self.waker.wake(); self.waker.wake();
}; };
} }
@ -318,13 +318,6 @@ where
fn on_interrupt(&mut self) { fn on_interrupt(&mut self) {
let r = T::regs(); let r = T::regs();
unsafe { unsafe {
let ris = r.uartris().read();
// Clear interrupt flags
r.uarticr().write(|w| {
w.set_rtic(true);
});
if ris.txris() {
let buf = self.buf.pop_buf(); let buf = self.buf.pop_buf();
if !buf.is_empty() { if !buf.is_empty() {
r.uartimsc().modify(|w| { r.uartimsc().modify(|w| {
@ -341,7 +334,6 @@ where
} }
} }
} }
}
} }
impl embedded_io::Error for Error { impl embedded_io::Error for Error {

7
embassy-rp/src/uart/mod.rs
View File

@ -343,7 +343,12 @@ impl<'d, T: Instance, M: Mode> Uart<'d, T, M> {
w.set_stp2(config.stop_bits == StopBits::STOP2); w.set_stp2(config.stop_bits == StopBits::STOP2);
w.set_pen(pen); w.set_pen(pen);
w.set_eps(eps); w.set_eps(eps);
w.set_fen(false); w.set_fen(true);
});
r.uartifls().write(|w| {
w.set_rxiflsel(0b000);
w.set_txiflsel(0b000);
}); });
r.uartcr().write(|w| { r.uartcr().write(|w| {

9
tests/rp/src/bin/uart_buffered.rs
View File

@ -20,8 +20,8 @@ async fn main(_spawner: Spawner) {
let uart = Uart::new_blocking(uart, tx, rx, config); let uart = Uart::new_blocking(uart, tx, rx, config);
let irq = interrupt::take!(UART0_IRQ); let irq = interrupt::take!(UART0_IRQ);
let tx_buf = &mut [0u8; 32]; let tx_buf = &mut [0u8; 16];
let rx_buf = &mut [0u8; 32]; let rx_buf = &mut [0u8; 16];
let mut state = State::new(); let mut state = State::new();
let mut uart = BufferedUart::new(&mut state, uart, irq, tx_buf, rx_buf); let mut uart = BufferedUart::new(&mut state, uart, irq, tx_buf, rx_buf);
@ -32,10 +32,11 @@ async fn main(_spawner: Spawner) {
1_u8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 1_u8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
30, 31, 32, 30, 31, 32,
]; ];
uart.write(&data).await.unwrap(); uart.write_all(&data).await.unwrap();
info!("Done writing");
let mut buf = [0; 32]; let mut buf = [0; 32];
uart.read(&mut buf).await.unwrap(); uart.read_exact(&mut buf).await.unwrap();
assert_eq!(buf, data); assert_eq!(buf, data);
info!("Test OK"); info!("Test OK");