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Eliminates redefinition of AdcClockSource

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This commit is contained in:
shakencodes 2023-11-01 12:06:19 -07:00
parent d0d8585e4c
commit e2688dda22
1 changed files with 4 additions and 27 deletions
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31
embassy-stm32/src/rcc/l4l5.rs
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@ -4,8 +4,8 @@ pub use crate::pac::rcc::vals::Clk48sel as Clk48Src;
#[cfg(any(stm32wb, stm32wl))] #[cfg(any(stm32wb, stm32wl))]
pub use crate::pac::rcc::vals::Hsepre as HsePrescaler; pub use crate::pac::rcc::vals::Hsepre as HsePrescaler;
pub use crate::pac::rcc::vals::{ pub use crate::pac::rcc::vals::{
Adcsel, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Adcsel as AdcClockSource, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul,
Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc,
}; };
use crate::pac::{FLASH, RCC}; use crate::pac::{FLASH, RCC};
use crate::rcc::{set_freqs, Clocks}; use crate::rcc::{set_freqs, Clocks};
@ -52,29 +52,6 @@ pub struct Pll {
pub divr: Option<PllRDiv>, pub divr: Option<PllRDiv>,
} }
#[derive(Clone, Copy)]
pub enum AdcClockSource {
HSI16,
PLLPCLK,
SYSCLK,
}
impl AdcClockSource {
pub fn adcsel(&self) -> Adcsel {
match self {
AdcClockSource::HSI16 => Adcsel::HSI,
AdcClockSource::PLLPCLK => Adcsel::PLL1_P,
AdcClockSource::SYSCLK => Adcsel::SYS,
}
}
}
impl Default for AdcClockSource {
fn default() -> Self {
Self::HSI16
}
}
/// Clocks configuration /// Clocks configuration
pub struct Config { pub struct Config {
// base clock sources // base clock sources
@ -136,7 +113,7 @@ impl Default for Config {
#[cfg(any(stm32l4, stm32l5, stm32wb))] #[cfg(any(stm32l4, stm32l5, stm32wb))]
clk48_src: Clk48Src::HSI48, clk48_src: Clk48Src::HSI48,
ls: Default::default(), ls: Default::default(),
adc_clock_source: AdcClockSource::default(), adc_clock_source: AdcClockSource::HSI,
} }
} }
} }
@ -370,7 +347,7 @@ pub(crate) unsafe fn init(config: Config) {
}); });
while RCC.cfgr().read().sws() != config.mux {} while RCC.cfgr().read().sws() != config.mux {}
RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source.adcsel())); RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source));
#[cfg(any(stm32wl, stm32wb))] #[cfg(any(stm32wl, stm32wb))]
{ {