From e2c074d133e3aa156eb0bc4d86bdd301aa9153e6 Mon Sep 17 00:00:00 2001
From: VasanthakumarV <vasanth260m12@gmail.com>
Date: Fri, 10 Dec 2021 11:39:54 +0530
Subject: [PATCH] [feature] Add pwr register support for F3

---
 embassy-stm32/src/pwr/f3.rs  | 0
 embassy-stm32/src/pwr/mod.rs | 1 +
 2 files changed, 1 insertion(+)
 create mode 100644 embassy-stm32/src/pwr/f3.rs

diff --git a/embassy-stm32/src/pwr/f3.rs b/embassy-stm32/src/pwr/f3.rs
new file mode 100644
index 00000000..e69de29b
diff --git a/embassy-stm32/src/pwr/mod.rs b/embassy-stm32/src/pwr/mod.rs
index a71ce8f3..18f462bd 100644
--- a/embassy-stm32/src/pwr/mod.rs
+++ b/embassy-stm32/src/pwr/mod.rs
@@ -1,4 +1,5 @@
 #[cfg_attr(any(pwr_h7, pwr_h7smps), path = "h7.rs")]
+#[cfg_attr(pwr_f3, path = "f3.rs")]
 #[cfg_attr(pwr_f4, path = "f4.rs")]
 #[cfg_attr(pwr_f7, path = "f7.rs")]
 #[cfg_attr(pwr_wl5, path = "wl5.rs")]