Add support for STM32G0
This commit is contained in:
Ben Gamari
Dario Nieuwenhuis
parent
174c51f097
commit
e2f71ffbbd
@ -281,6 +281,110 @@ stm32f479vg = [ "stm32-metapac/stm32f479vg",]
|
||||
stm32f479vi = [ "stm32-metapac/stm32f479vi",]
|
||||
stm32f479zg = [ "stm32-metapac/stm32f479zg",]
|
||||
stm32f479zi = [ "stm32-metapac/stm32f479zi",]
|
||||
stm32g030c6 = [ "stm32-metapac/stm32g030c6",]
|
||||
stm32g030c8 = [ "stm32-metapac/stm32g030c8",]
|
||||
stm32g030f6 = [ "stm32-metapac/stm32g030f6",]
|
||||
stm32g030j6 = [ "stm32-metapac/stm32g030j6",]
|
||||
stm32g030k6 = [ "stm32-metapac/stm32g030k6",]
|
||||
stm32g030k8 = [ "stm32-metapac/stm32g030k8",]
|
||||
stm32g031c4 = [ "stm32-metapac/stm32g031c4",]
|
||||
stm32g031c6 = [ "stm32-metapac/stm32g031c6",]
|
||||
stm32g031c8 = [ "stm32-metapac/stm32g031c8",]
|
||||
stm32g031f4 = [ "stm32-metapac/stm32g031f4",]
|
||||
stm32g031f6 = [ "stm32-metapac/stm32g031f6",]
|
||||
stm32g031f8 = [ "stm32-metapac/stm32g031f8",]
|
||||
stm32g031g4 = [ "stm32-metapac/stm32g031g4",]
|
||||
stm32g031g6 = [ "stm32-metapac/stm32g031g6",]
|
||||
stm32g031g8 = [ "stm32-metapac/stm32g031g8",]
|
||||
stm32g031j4 = [ "stm32-metapac/stm32g031j4",]
|
||||
stm32g031j6 = [ "stm32-metapac/stm32g031j6",]
|
||||
stm32g031k4 = [ "stm32-metapac/stm32g031k4",]
|
||||
stm32g031k6 = [ "stm32-metapac/stm32g031k6",]
|
||||
stm32g031k8 = [ "stm32-metapac/stm32g031k8",]
|
||||
stm32g031y8 = [ "stm32-metapac/stm32g031y8",]
|
||||
stm32g041c6 = [ "stm32-metapac/stm32g041c6",]
|
||||
stm32g041c8 = [ "stm32-metapac/stm32g041c8",]
|
||||
stm32g041f6 = [ "stm32-metapac/stm32g041f6",]
|
||||
stm32g041f8 = [ "stm32-metapac/stm32g041f8",]
|
||||
stm32g041g6 = [ "stm32-metapac/stm32g041g6",]
|
||||
stm32g041g8 = [ "stm32-metapac/stm32g041g8",]
|
||||
stm32g041j6 = [ "stm32-metapac/stm32g041j6",]
|
||||
stm32g041k6 = [ "stm32-metapac/stm32g041k6",]
|
||||
stm32g041k8 = [ "stm32-metapac/stm32g041k8",]
|
||||
stm32g041y8 = [ "stm32-metapac/stm32g041y8",]
|
||||
stm32g050c6 = [ "stm32-metapac/stm32g050c6",]
|
||||
stm32g050c8 = [ "stm32-metapac/stm32g050c8",]
|
||||
stm32g050f6 = [ "stm32-metapac/stm32g050f6",]
|
||||
stm32g050k6 = [ "stm32-metapac/stm32g050k6",]
|
||||
stm32g050k8 = [ "stm32-metapac/stm32g050k8",]
|
||||
stm32g051c6 = [ "stm32-metapac/stm32g051c6",]
|
||||
stm32g051c8 = [ "stm32-metapac/stm32g051c8",]
|
||||
stm32g051f6 = [ "stm32-metapac/stm32g051f6",]
|
||||
stm32g051f8 = [ "stm32-metapac/stm32g051f8",]
|
||||
stm32g051g6 = [ "stm32-metapac/stm32g051g6",]
|
||||
stm32g051g8 = [ "stm32-metapac/stm32g051g8",]
|
||||
stm32g051k6 = [ "stm32-metapac/stm32g051k6",]
|
||||
stm32g051k8 = [ "stm32-metapac/stm32g051k8",]
|
||||
stm32g061c6 = [ "stm32-metapac/stm32g061c6",]
|
||||
stm32g061c8 = [ "stm32-metapac/stm32g061c8",]
|
||||
stm32g061f6 = [ "stm32-metapac/stm32g061f6",]
|
||||
stm32g061f8 = [ "stm32-metapac/stm32g061f8",]
|
||||
stm32g061g6 = [ "stm32-metapac/stm32g061g6",]
|
||||
stm32g061g8 = [ "stm32-metapac/stm32g061g8",]
|
||||
stm32g061k6 = [ "stm32-metapac/stm32g061k6",]
|
||||
stm32g061k8 = [ "stm32-metapac/stm32g061k8",]
|
||||
stm32g070cb = [ "stm32-metapac/stm32g070cb",]
|
||||
stm32g070kb = [ "stm32-metapac/stm32g070kb",]
|
||||
stm32g070rb = [ "stm32-metapac/stm32g070rb",]
|
||||
stm32g071c6 = [ "stm32-metapac/stm32g071c6",]
|
||||
stm32g071c8 = [ "stm32-metapac/stm32g071c8",]
|
||||
stm32g071cb = [ "stm32-metapac/stm32g071cb",]
|
||||
stm32g071eb = [ "stm32-metapac/stm32g071eb",]
|
||||
stm32g071g6 = [ "stm32-metapac/stm32g071g6",]
|
||||
stm32g071g8 = [ "stm32-metapac/stm32g071g8",]
|
||||
stm32g071gb = [ "stm32-metapac/stm32g071gb",]
|
||||
stm32g071k6 = [ "stm32-metapac/stm32g071k6",]
|
||||
stm32g071k8 = [ "stm32-metapac/stm32g071k8",]
|
||||
stm32g071kb = [ "stm32-metapac/stm32g071kb",]
|
||||
stm32g071r6 = [ "stm32-metapac/stm32g071r6",]
|
||||
stm32g071r8 = [ "stm32-metapac/stm32g071r8",]
|
||||
stm32g071rb = [ "stm32-metapac/stm32g071rb",]
|
||||
stm32g081cb = [ "stm32-metapac/stm32g081cb",]
|
||||
stm32g081eb = [ "stm32-metapac/stm32g081eb",]
|
||||
stm32g081gb = [ "stm32-metapac/stm32g081gb",]
|
||||
stm32g081kb = [ "stm32-metapac/stm32g081kb",]
|
||||
stm32g081rb = [ "stm32-metapac/stm32g081rb",]
|
||||
stm32g0b0ce = [ "stm32-metapac/stm32g0b0ce",]
|
||||
stm32g0b0ke = [ "stm32-metapac/stm32g0b0ke",]
|
||||
stm32g0b0re = [ "stm32-metapac/stm32g0b0re",]
|
||||
stm32g0b0ve = [ "stm32-metapac/stm32g0b0ve",]
|
||||
stm32g0b1cb = [ "stm32-metapac/stm32g0b1cb",]
|
||||
stm32g0b1cc = [ "stm32-metapac/stm32g0b1cc",]
|
||||
stm32g0b1ce = [ "stm32-metapac/stm32g0b1ce",]
|
||||
stm32g0b1kb = [ "stm32-metapac/stm32g0b1kb",]
|
||||
stm32g0b1kc = [ "stm32-metapac/stm32g0b1kc",]
|
||||
stm32g0b1ke = [ "stm32-metapac/stm32g0b1ke",]
|
||||
stm32g0b1mb = [ "stm32-metapac/stm32g0b1mb",]
|
||||
stm32g0b1mc = [ "stm32-metapac/stm32g0b1mc",]
|
||||
stm32g0b1me = [ "stm32-metapac/stm32g0b1me",]
|
||||
stm32g0b1ne = [ "stm32-metapac/stm32g0b1ne",]
|
||||
stm32g0b1rb = [ "stm32-metapac/stm32g0b1rb",]
|
||||
stm32g0b1rc = [ "stm32-metapac/stm32g0b1rc",]
|
||||
stm32g0b1re = [ "stm32-metapac/stm32g0b1re",]
|
||||
stm32g0b1vb = [ "stm32-metapac/stm32g0b1vb",]
|
||||
stm32g0b1vc = [ "stm32-metapac/stm32g0b1vc",]
|
||||
stm32g0b1ve = [ "stm32-metapac/stm32g0b1ve",]
|
||||
stm32g0c1cc = [ "stm32-metapac/stm32g0c1cc",]
|
||||
stm32g0c1ce = [ "stm32-metapac/stm32g0c1ce",]
|
||||
stm32g0c1kc = [ "stm32-metapac/stm32g0c1kc",]
|
||||
stm32g0c1ke = [ "stm32-metapac/stm32g0c1ke",]
|
||||
stm32g0c1mc = [ "stm32-metapac/stm32g0c1mc",]
|
||||
stm32g0c1me = [ "stm32-metapac/stm32g0c1me",]
|
||||
stm32g0c1ne = [ "stm32-metapac/stm32g0c1ne",]
|
||||
stm32g0c1rc = [ "stm32-metapac/stm32g0c1rc",]
|
||||
stm32g0c1re = [ "stm32-metapac/stm32g0c1re",]
|
||||
stm32g0c1vc = [ "stm32-metapac/stm32g0c1vc",]
|
||||
stm32g0c1ve = [ "stm32-metapac/stm32g0c1ve",]
|
||||
stm32h723ve = [ "stm32-metapac/stm32h723ve",]
|
||||
stm32h723vg = [ "stm32-metapac/stm32h723vg",]
|
||||
stm32h723ze = [ "stm32-metapac/stm32h723ze",]
|
||||
|
||||
@ -15,6 +15,7 @@ os.chdir(dname)
|
||||
supported_families = [
|
||||
"STM32F0",
|
||||
'STM32F4',
|
||||
'STM32G0',
|
||||
'STM32L0',
|
||||
'STM32L4',
|
||||
'STM32H7',
|
||||
|
||||
@ -188,6 +188,7 @@ impl<'d, T: Instance> Adc<'d, T> {
|
||||
/// Calculates the system VDDA by sampling the internal VREF channel and comparing
|
||||
/// the result with the value stored at the factory. If the chip's VDDA is not stable, run
|
||||
/// this before each ADC conversion.
|
||||
#[cfg(not(rcc_g0))] // TODO is this supposed to be public?
|
||||
#[allow(unused)] // TODO is this supposed to be public?
|
||||
fn calibrate(&mut self, vref: &mut Vref) {
|
||||
let vref_cal = unsafe { crate::pac::VREFINTCAL.data().read().value() };
|
||||
|
||||
@ -11,7 +11,8 @@ use embedded_hal::digital::v2::InputPin;
|
||||
use crate::gpio::{AnyPin, Input, Pin as GpioPin};
|
||||
use crate::interrupt;
|
||||
use crate::pac;
|
||||
use crate::pac::{EXTI, SYSCFG};
|
||||
use crate::pac::exti::regs::Lines;
|
||||
use crate::pac::EXTI;
|
||||
use crate::peripherals;
|
||||
|
||||
const EXTI_COUNT: usize = 16;
|
||||
@ -28,19 +29,37 @@ fn cpu_regs() -> pac::exti::Exti {
|
||||
EXTI
|
||||
}
|
||||
|
||||
#[cfg(not(any(exti_g0, exti_l5)))]
|
||||
fn exticr_regs() -> pac::syscfg::Syscfg {
|
||||
pac::SYSCFG
|
||||
}
|
||||
#[cfg(any(exti_g0, exti_l5))]
|
||||
fn exticr_regs() -> pac::exti::Exti {
|
||||
EXTI
|
||||
}
|
||||
|
||||
pub unsafe fn on_irq() {
|
||||
let bits = EXTI.pr(0).read();
|
||||
#[cfg(not(any(exti_g0, exti_l5)))]
|
||||
let bits = EXTI.pr(0).read().0;
|
||||
#[cfg(any(exti_g0, exti_l5))]
|
||||
let bits = EXTI.rpr(0).read().0 | EXTI.fpr(0).read().0;
|
||||
|
||||
// Mask all the channels that fired.
|
||||
cpu_regs().imr(0).modify(|w| w.0 &= !bits.0);
|
||||
cpu_regs().imr(0).modify(|w| w.0 &= !bits);
|
||||
|
||||
// Wake the tasks
|
||||
for pin in BitIter(bits.0) {
|
||||
for pin in BitIter(bits) {
|
||||
EXTI_WAKERS[pin as usize].wake();
|
||||
}
|
||||
|
||||
// Clear pending
|
||||
EXTI.pr(0).write_value(bits);
|
||||
#[cfg(not(any(exti_g0, exti_l5)))]
|
||||
EXTI.pr(0).write_value(Lines(bits));
|
||||
#[cfg(any(exti_g0, exti_l5))]
|
||||
{
|
||||
EXTI.rpr(0).write_value(Lines(bits));
|
||||
EXTI.fpr(0).write_value(Lines(bits));
|
||||
}
|
||||
}
|
||||
|
||||
struct BitIter(u32);
|
||||
@ -117,10 +136,21 @@ impl<'a> ExtiInputFuture<'a> {
|
||||
fn new(pin: u8, port: u8, rising: bool, falling: bool) -> Self {
|
||||
cortex_m::interrupt::free(|_| unsafe {
|
||||
let pin = pin as usize;
|
||||
SYSCFG.exticr(pin / 4).modify(|w| w.set_exti(pin % 4, port));
|
||||
exticr_regs()
|
||||
.exticr(pin / 4)
|
||||
.modify(|w| w.set_exti(pin % 4, port));
|
||||
EXTI.rtsr(0).modify(|w| w.set_line(pin, rising));
|
||||
EXTI.ftsr(0).modify(|w| w.set_line(pin, falling));
|
||||
EXTI.pr(0).write(|w| w.set_line(pin, true)); // clear pending bit
|
||||
|
||||
// clear pending bit
|
||||
#[cfg(not(any(exti_g0, exti_l5)))]
|
||||
EXTI.pr(0).write(|w| w.set_line(pin, true));
|
||||
#[cfg(any(exti_g0, exti_l5))]
|
||||
{
|
||||
EXTI.rpr(0).write(|w| w.set_line(pin, true));
|
||||
EXTI.fpr(0).write(|w| w.set_line(pin, true));
|
||||
}
|
||||
|
||||
cpu_regs().imr(0).modify(|w| w.set_line(pin, true));
|
||||
});
|
||||
|
||||
|
||||
190
embassy-stm32/src/rcc/g0/mod.rs
Normal file
190
embassy-stm32/src/rcc/g0/mod.rs
Normal file
@ -0,0 +1,190 @@
|
||||
pub use super::types::*;
|
||||
use crate::pac;
|
||||
use crate::peripherals::{self, RCC};
|
||||
use crate::rcc::{get_freqs, set_freqs, Clocks};
|
||||
use crate::time::Hertz;
|
||||
use crate::time::U32Ext;
|
||||
use core::marker::PhantomData;
|
||||
use embassy::util::Unborrow;
|
||||
use embassy_hal_common::unborrow;
|
||||
|
||||
/// HSI speed
|
||||
pub const HSI_FREQ: u32 = 16_000_000;
|
||||
|
||||
/// LSI speed
|
||||
pub const LSI_FREQ: u32 = 32_000;
|
||||
|
||||
/// System clock mux source
|
||||
#[derive(Clone, Copy)]
|
||||
pub enum ClockSrc {
|
||||
HSE(Hertz),
|
||||
HSI16,
|
||||
LSI,
|
||||
}
|
||||
|
||||
impl Into<u8> for APBPrescaler {
|
||||
fn into(self) -> u8 {
|
||||
match self {
|
||||
APBPrescaler::NotDivided => 1,
|
||||
APBPrescaler::Div2 => 0x04,
|
||||
APBPrescaler::Div4 => 0x05,
|
||||
APBPrescaler::Div8 => 0x06,
|
||||
APBPrescaler::Div16 => 0x07,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Into<u8> for AHBPrescaler {
|
||||
fn into(self) -> u8 {
|
||||
match self {
|
||||
AHBPrescaler::NotDivided => 1,
|
||||
AHBPrescaler::Div2 => 0x08,
|
||||
AHBPrescaler::Div4 => 0x09,
|
||||
AHBPrescaler::Div8 => 0x0a,
|
||||
AHBPrescaler::Div16 => 0x0b,
|
||||
AHBPrescaler::Div64 => 0x0c,
|
||||
AHBPrescaler::Div128 => 0x0d,
|
||||
AHBPrescaler::Div256 => 0x0e,
|
||||
AHBPrescaler::Div512 => 0x0f,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Clocks configutation
|
||||
pub struct Config {
|
||||
mux: ClockSrc,
|
||||
ahb_pre: AHBPrescaler,
|
||||
apb_pre: APBPrescaler,
|
||||
}
|
||||
|
||||
impl Default for Config {
|
||||
#[inline]
|
||||
fn default() -> Config {
|
||||
Config {
|
||||
mux: ClockSrc::HSI16,
|
||||
ahb_pre: AHBPrescaler::NotDivided,
|
||||
apb_pre: APBPrescaler::NotDivided,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Config {
|
||||
#[inline]
|
||||
pub fn clock_src(mut self, mux: ClockSrc) -> Self {
|
||||
self.mux = mux;
|
||||
self
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn ahb_pre(mut self, pre: AHBPrescaler) -> Self {
|
||||
self.ahb_pre = pre;
|
||||
self
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn apb_pre(mut self, pre: APBPrescaler) -> Self {
|
||||
self.apb_pre = pre;
|
||||
self
|
||||
}
|
||||
}
|
||||
|
||||
/// RCC peripheral
|
||||
pub struct Rcc<'d> {
|
||||
_rb: peripherals::RCC,
|
||||
phantom: PhantomData<&'d mut peripherals::RCC>,
|
||||
}
|
||||
|
||||
impl<'d> Rcc<'d> {
|
||||
pub fn new(rcc: impl Unborrow<Target = peripherals::RCC> + 'd) -> Self {
|
||||
unborrow!(rcc);
|
||||
Self {
|
||||
_rb: rcc,
|
||||
phantom: PhantomData,
|
||||
}
|
||||
}
|
||||
|
||||
// Safety: RCC init must have been called
|
||||
pub fn clocks(&self) -> &'static Clocks {
|
||||
unsafe { get_freqs() }
|
||||
}
|
||||
}
|
||||
|
||||
/// Extension trait that freezes the `RCC` peripheral with provided clocks configuration
|
||||
pub trait RccExt {
|
||||
fn freeze(self, config: Config) -> Clocks;
|
||||
}
|
||||
|
||||
impl RccExt for RCC {
|
||||
#[inline]
|
||||
fn freeze(self, cfgr: Config) -> Clocks {
|
||||
let rcc = pac::RCC;
|
||||
let (sys_clk, sw) = match cfgr.mux {
|
||||
ClockSrc::HSI16 => {
|
||||
// Enable HSI16
|
||||
unsafe {
|
||||
rcc.cr().write(|w| w.set_hsion(true));
|
||||
while !rcc.cr().read().hsirdy() {}
|
||||
}
|
||||
|
||||
(HSI_FREQ, 0x00)
|
||||
}
|
||||
ClockSrc::HSE(freq) => {
|
||||
// Enable HSE
|
||||
unsafe {
|
||||
rcc.cr().write(|w| w.set_hseon(true));
|
||||
while !rcc.cr().read().hserdy() {}
|
||||
}
|
||||
|
||||
(freq.0, 0x01)
|
||||
}
|
||||
ClockSrc::LSI => {
|
||||
// Enable LSI
|
||||
unsafe {
|
||||
rcc.csr().write(|w| w.set_lsion(true));
|
||||
while !rcc.csr().read().lsirdy() {}
|
||||
}
|
||||
(LSI_FREQ, 0x03)
|
||||
}
|
||||
};
|
||||
|
||||
unsafe {
|
||||
rcc.cfgr().modify(|w| {
|
||||
w.set_sw(sw.into());
|
||||
w.set_hpre(cfgr.ahb_pre.into());
|
||||
w.set_ppre(cfgr.apb_pre.into());
|
||||
});
|
||||
}
|
||||
|
||||
let ahb_freq: u32 = match cfgr.ahb_pre {
|
||||
AHBPrescaler::NotDivided => sys_clk,
|
||||
pre => {
|
||||
let pre: u8 = pre.into();
|
||||
let pre = 1 << (pre as u32 - 7);
|
||||
sys_clk / pre
|
||||
}
|
||||
};
|
||||
|
||||
let (apb_freq, apb_tim_freq) = match cfgr.apb_pre {
|
||||
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
|
||||
pre => {
|
||||
let pre: u8 = pre.into();
|
||||
let pre: u8 = 1 << (pre - 3);
|
||||
let freq = ahb_freq / pre as u32;
|
||||
(freq, freq * 2)
|
||||
}
|
||||
};
|
||||
|
||||
Clocks {
|
||||
sys: sys_clk.hz(),
|
||||
ahb: ahb_freq.hz(),
|
||||
apb: apb_freq.hz(),
|
||||
apb_tim: apb_tim_freq.hz(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub unsafe fn init(config: Config) {
|
||||
let r = <peripherals::RCC as embassy::util::Steal>::steal();
|
||||
let clocks = r.freeze(config);
|
||||
set_freqs(clocks);
|
||||
}
|
||||
@ -8,15 +8,26 @@ mod types;
|
||||
#[derive(Clone, Copy)]
|
||||
pub struct Clocks {
|
||||
pub sys: Hertz,
|
||||
|
||||
#[cfg(rcc_g0)]
|
||||
pub apb: Hertz,
|
||||
#[cfg(rcc_g0)]
|
||||
pub apb_tim: Hertz,
|
||||
|
||||
#[cfg(not(rcc_g0))]
|
||||
pub apb1: Hertz,
|
||||
#[cfg(not(rcc_g0))]
|
||||
pub apb1_tim: Hertz,
|
||||
|
||||
#[cfg(not(rcc_g0))]
|
||||
pub apb2: Hertz,
|
||||
#[cfg(not(rcc_g0))]
|
||||
pub apb2_tim: Hertz,
|
||||
|
||||
#[cfg(rcc_wl5)]
|
||||
pub apb3: Hertz,
|
||||
|
||||
pub apb1_tim: Hertz,
|
||||
pub apb2_tim: Hertz,
|
||||
|
||||
#[cfg(any(rcc_l0, rcc_f0, rcc_f0x0))]
|
||||
#[cfg(any(rcc_l0, rcc_f0, rcc_f0x0, rcc_g0))]
|
||||
pub ahb: Hertz,
|
||||
|
||||
#[cfg(any(rcc_l4, rcc_f4, rcc_h7, rcc_wb, rcc_wl5))]
|
||||
@ -77,6 +88,9 @@ cfg_if::cfg_if! {
|
||||
} else if #[cfg(any(rcc_f0, rcc_f0x0))] {
|
||||
mod f0;
|
||||
pub use f0::*;
|
||||
} else if #[cfg(any(rcc_g0))] {
|
||||
mod g0;
|
||||
pub use g0::*;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -444,7 +444,9 @@ pub fn gen(options: Options) {
|
||||
Some(clock) => clock.as_str(),
|
||||
None => {
|
||||
// No clock was specified, derive the clock name from the enable register name.
|
||||
Regex::new("([A-Z]+\\d*).*")
|
||||
// N.B. STM32G0 has only one APB bus but split ENR registers
|
||||
// (e.g. APBENR1).
|
||||
Regex::new("([A-Z]+\\d*)ENR\\d*")
|
||||
.unwrap()
|
||||
.captures(enable_reg)
|
||||
.unwrap()
|
||||
|
||||
Loading…
Reference in New Issue
Block a user