max/embassy
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

rp: rename gpio::Pin::io to gpio::Pin::gpio

Browse Source 
we'll need access to the pin io bank registers for an upcoming fix, and
having both `io` and `io_bank` or similar can get confusing quickly.
rename `io` to `gpio` to avoid this, and also match the type while there.
This commit is contained in:
pennae
2023-07-31 18:28:31 +02:00
parent ebc173ea75
commit e6d4043279
7 changed files with 22 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
embassy-rp/src/clocks.rs
View File

@@ -702,7 +702,7 @@ impl<'d, T: Pin> Gpin<'d, T> {
pub fn new<P: GpinPin>(gpin: impl Peripheral<P = P> + 'd) -> Gpin<'d, P> { pub fn new<P: GpinPin>(gpin: impl Peripheral<P = P> + 'd) -> Gpin<'d, P> {
into_ref!(gpin); into_ref!(gpin);
gpin.io().ctrl().write(|w| w.set_funcsel(0x08)); gpin.gpio().ctrl().write(|w| w.set_funcsel(0x08));
Gpin { Gpin {
gpin: gpin.map_into(), gpin: gpin.map_into(),
@@ -718,7 +718,7 @@ impl<'d, T: Pin> Gpin<'d, T> {
impl<'d, T: Pin> Drop for Gpin<'d, T> { impl<'d, T: Pin> Drop for Gpin<'d, T> {
fn drop(&mut self) { fn drop(&mut self) {
self.gpin self.gpin
.io() .gpio()
.ctrl() .ctrl()
.write(|w| w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL as _)); .write(|w| w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL as _));
} }
@@ -766,7 +766,7 @@ impl<'d, T: GpoutPin> Gpout<'d, T> {
pub fn new(gpout: impl Peripheral<P = T> + 'd) -> Self { pub fn new(gpout: impl Peripheral<P = T> + 'd) -> Self {
into_ref!(gpout); into_ref!(gpout);
gpout.io().ctrl().write(|w| w.set_funcsel(0x08)); gpout.gpio().ctrl().write(|w| w.set_funcsel(0x08));
Self { gpout } Self { gpout }
} }
@@ -831,7 +831,7 @@ impl<'d, T: GpoutPin> Drop for Gpout<'d, T> {
fn drop(&mut self) { fn drop(&mut self) {
self.disable(); self.disable();
self.gpout self.gpout
.io() .gpio()
.ctrl() .ctrl()
.write(|w| w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL as _)); .write(|w| w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL as _));
} }

6
embassy-rp/src/gpio.rs
View File

@@ -451,7 +451,7 @@ impl<'d, T: Pin> Flex<'d, T> {
w.set_ie(true); w.set_ie(true);
}); });
pin.io().ctrl().write(|w| { pin.gpio().ctrl().write(|w| {
w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::SIO_0 as _); w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::SIO_0 as _);
}); });
@@ -617,7 +617,7 @@ impl<'d, T: Pin> Drop for Flex<'d, T> {
#[inline] #[inline]
fn drop(&mut self) { fn drop(&mut self) {
self.pin.pad_ctrl().write(|_| {}); self.pin.pad_ctrl().write(|_| {});
self.pin.io().ctrl().write(|w| { self.pin.gpio().ctrl().write(|w| {
w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL as _); w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL as _);
}); });
} }
@@ -643,7 +643,7 @@ pub(crate) mod sealed {
} }
} }
fn io(&self) -> pac::io::Gpio { fn gpio(&self) -> pac::io::Gpio {
let block = match self._bank() { let block = match self._bank() {
Bank::Bank0 => crate::pac::IO_BANK0, Bank::Bank0 => crate::pac::IO_BANK0,
Bank::Qspi => crate::pac::IO_QSPI, Bank::Qspi => crate::pac::IO_QSPI,

4
embassy-rp/src/i2c.rs
View File

@@ -353,8 +353,8 @@ impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
p.ic_rx_tl().write(|w| w.set_rx_tl(0)); p.ic_rx_tl().write(|w| w.set_rx_tl(0));
// Configure SCL & SDA pins // Configure SCL & SDA pins
scl.io().ctrl().write(|w| w.set_funcsel(3)); scl.gpio().ctrl().write(|w| w.set_funcsel(3));
sda.io().ctrl().write(|w| w.set_funcsel(3)); sda.gpio().ctrl().write(|w| w.set_funcsel(3));
scl.pad_ctrl().write(|w| { scl.pad_ctrl().write(|w| {
w.set_schmitt(true); w.set_schmitt(true);

2
embassy-rp/src/pio.rs
View File

@@ -852,7 +852,7 @@ impl<'d, PIO: Instance> Common<'d, PIO> {
/// of [`Pio`] do not keep pin registrations alive.** /// of [`Pio`] do not keep pin registrations alive.**
pub fn make_pio_pin(&mut self, pin: impl Peripheral<P = impl PioPin + 'd> + 'd) -> Pin<'d, PIO> { pub fn make_pio_pin(&mut self, pin: impl Peripheral<P = impl PioPin + 'd> + 'd) -> Pin<'d, PIO> {
into_ref!(pin); into_ref!(pin);
pin.io().ctrl().write(|w| w.set_funcsel(PIO::FUNCSEL as _)); pin.gpio().ctrl().write(|w| w.set_funcsel(PIO::FUNCSEL as _));
// we can be relaxed about this because we're &mut here and nothing is cached // we can be relaxed about this because we're &mut here and nothing is cached
PIO::state().used_pins.fetch_or(1 << pin.pin_bank(), Ordering::Relaxed); PIO::state().used_pins.fetch_or(1 << pin.pin_bank(), Ordering::Relaxed);
Pin { Pin {

8
embassy-rp/src/pwm.rs
View File

@@ -79,10 +79,10 @@ impl<'d, T: Channel> Pwm<'d, T> {
Self::configure(p, &config); Self::configure(p, &config);
if let Some(pin) = &a { if let Some(pin) = &a {
pin.io().ctrl().write(|w| w.set_funcsel(4)); pin.gpio().ctrl().write(|w| w.set_funcsel(4));
} }
if let Some(pin) = &b { if let Some(pin) = &b {
pin.io().ctrl().write(|w| w.set_funcsel(4)); pin.gpio().ctrl().write(|w| w.set_funcsel(4));
} }
Self { Self {
inner, inner,
@@ -243,10 +243,10 @@ impl<'d, T: Channel> Drop for Pwm<'d, T> {
fn drop(&mut self) { fn drop(&mut self) {
self.inner.regs().csr().write_clear(|w| w.set_en(false)); self.inner.regs().csr().write_clear(|w| w.set_en(false));
if let Some(pin) = &self.pin_a { if let Some(pin) = &self.pin_a {
pin.io().ctrl().write(|w| w.set_funcsel(31)); pin.gpio().ctrl().write(|w| w.set_funcsel(31));
} }
if let Some(pin) = &self.pin_b { if let Some(pin) = &self.pin_b {
pin.io().ctrl().write(|w| w.set_funcsel(31)); pin.gpio().ctrl().write(|w| w.set_funcsel(31));
} }
} }
} }

8
embassy-rp/src/spi.rs
View File

@@ -100,16 +100,16 @@ impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
p.cr1().write(|w| w.set_sse(true)); p.cr1().write(|w| w.set_sse(true));
if let Some(pin) = &clk { if let Some(pin) = &clk {
pin.io().ctrl().write(|w| w.set_funcsel(1)); pin.gpio().ctrl().write(|w| w.set_funcsel(1));
} }
if let Some(pin) = &mosi { if let Some(pin) = &mosi {
pin.io().ctrl().write(|w| w.set_funcsel(1)); pin.gpio().ctrl().write(|w| w.set_funcsel(1));
} }
if let Some(pin) = &miso { if let Some(pin) = &miso {
pin.io().ctrl().write(|w| w.set_funcsel(1)); pin.gpio().ctrl().write(|w| w.set_funcsel(1));
} }
if let Some(pin) = &cs { if let Some(pin) = &cs {
pin.io().ctrl().write(|w| w.set_funcsel(1)); pin.gpio().ctrl().write(|w| w.set_funcsel(1));
} }
Self { Self {
inner, inner,

8
embassy-rp/src/uart/mod.rs
View File

@@ -565,7 +565,7 @@ impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> {
) { ) {
let r = T::regs(); let r = T::regs();
if let Some(pin) = &tx { if let Some(pin) = &tx {
pin.io().ctrl().write(|w| { pin.gpio().ctrl().write(|w| {
w.set_funcsel(2); w.set_funcsel(2);
w.set_outover(if config.invert_tx { w.set_outover(if config.invert_tx {
Outover::INVERT Outover::INVERT
@@ -576,7 +576,7 @@ impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> {
pin.pad_ctrl().write(|w| w.set_ie(true)); pin.pad_ctrl().write(|w| w.set_ie(true));
} }
if let Some(pin) = &rx { if let Some(pin) = &rx {
pin.io().ctrl().write(|w| { pin.gpio().ctrl().write(|w| {
w.set_funcsel(2); w.set_funcsel(2);
w.set_inover(if config.invert_rx { w.set_inover(if config.invert_rx {
Inover::INVERT Inover::INVERT
@@ -587,7 +587,7 @@ impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> {
pin.pad_ctrl().write(|w| w.set_ie(true)); pin.pad_ctrl().write(|w| w.set_ie(true));
} }
if let Some(pin) = &cts { if let Some(pin) = &cts {
pin.io().ctrl().write(|w| { pin.gpio().ctrl().write(|w| {
w.set_funcsel(2); w.set_funcsel(2);
w.set_inover(if config.invert_cts { w.set_inover(if config.invert_cts {
Inover::INVERT Inover::INVERT
@@ -598,7 +598,7 @@ impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> {
pin.pad_ctrl().write(|w| w.set_ie(true)); pin.pad_ctrl().write(|w| w.set_ie(true));
} }
if let Some(pin) = &rts { if let Some(pin) = &rts {
pin.io().ctrl().write(|w| { pin.gpio().ctrl().write(|w| {
w.set_funcsel(2); w.set_funcsel(2);
w.set_outover(if config.invert_rts { w.set_outover(if config.invert_rts {
Outover::INVERT Outover::INVERT