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stm32/dma: minor cleanup, optmization

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xoviat 2023-08-04 17:15:56 -05:00
parent 7e269f6f17
commit e80db42061
2 changed files with 6 additions and 6 deletions
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4
embassy-stm32/src/dma/bdma.rs
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@ -497,7 +497,7 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
} }
/// The capacity of the ringbuffer. /// The capacity of the ringbuffer.
pub fn cap(&self) -> usize { pub const fn cap(&self) -> usize {
self.ringbuf.cap() self.ringbuf.cap()
} }
@ -628,7 +628,7 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
} }
/// The capacity of the ringbuffer. /// The capacity of the ringbuffer.
pub fn cap(&self) -> usize { pub const fn cap(&self) -> usize {
self.ringbuf.cap() self.ringbuf.cap()
} }

8
embassy-stm32/src/dma/dma.rs
View File

@ -742,12 +742,12 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
} }
// The capacity of the ringbuffer // The capacity of the ringbuffer
pub fn cap(&self) -> usize { pub const fn cap(&self) -> usize {
self.ringbuf.cap() self.ringbuf.cap()
} }
pub fn set_waker(&mut self, waker: &Waker) { pub fn set_waker(&mut self, waker: &Waker) {
STATE.ch_wakers[self.channel.index()].register(waker); DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
} }
fn clear_irqs(&mut self) { fn clear_irqs(&mut self) {
@ -890,12 +890,12 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
} }
// The capacity of the ringbuffer // The capacity of the ringbuffer
pub fn cap(&self) -> usize { pub const fn cap(&self) -> usize {
self.ringbuf.cap() self.ringbuf.cap()
} }
pub fn set_waker(&mut self, waker: &Waker) { pub fn set_waker(&mut self, waker: &Waker) {
STATE.ch_wakers[self.channel.index()].register(waker); DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
} }
fn clear_irqs(&mut self) { fn clear_irqs(&mut self) {