Update stm32-metapac, includes chiptool changes to use real Rust enums now.
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@@ -1,3 +1,5 @@
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use stm32_metapac::flash::vals::Latency;
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use super::{set_freqs, Clocks};
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use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Sw, Usbsw};
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use crate::pac::{FLASH, RCC};
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@@ -85,14 +87,11 @@ pub(crate) unsafe fn init(config: Config) {
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let timer_mul = if ppre == 1 { 1 } else { 2 };
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FLASH.acr().write(|w| {
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let latency = if real_sysclk <= 24_000_000 {
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0
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} else if real_sysclk <= 48_000_000 {
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1
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w.set_latency(if real_sysclk <= 24_000_000 {
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Latency::WS0
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} else {
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2
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};
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w.latency().0 = latency;
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Latency::WS1
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});
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});
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match (config.hse.is_some(), use_hsi48) {
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@@ -134,20 +133,20 @@ pub(crate) unsafe fn init(config: Config) {
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// TODO: Option to use CRS (Clock Recovery)
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if let Some(pllmul_bits) = pllmul_bits {
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RCC.cfgr().modify(|w| w.set_pllmul(Pllmul(pllmul_bits)));
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RCC.cfgr().modify(|w| w.set_pllmul(Pllmul::from_bits(pllmul_bits)));
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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RCC.cfgr().modify(|w| {
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w.set_ppre(Ppre(ppre_bits));
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w.set_hpre(Hpre(hpre_bits));
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w.set_ppre(Ppre::from_bits(ppre_bits));
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w.set_hpre(Hpre::from_bits(hpre_bits));
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w.set_sw(Sw::PLL)
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});
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} else {
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RCC.cfgr().modify(|w| {
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w.set_ppre(Ppre(ppre_bits));
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w.set_hpre(Hpre(hpre_bits));
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w.set_ppre(Ppre::from_bits(ppre_bits));
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w.set_hpre(Hpre::from_bits(hpre_bits));
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if config.hse.is_some() {
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w.set_sw(Sw::HSE);
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