From e8ca5f9b04c30aa63fa68ae051070f506c5c964e Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Thu, 24 Feb 2022 05:57:17 +0100
Subject: [PATCH] stm32/rcc: fix build on l0 chips without CRS

---
 embassy-stm32/src/rcc/l0.rs | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/embassy-stm32/src/rcc/l0.rs b/embassy-stm32/src/rcc/l0.rs
index e482dcc2..69279117 100644
--- a/embassy-stm32/src/rcc/l0.rs
+++ b/embassy-stm32/src/rcc/l0.rs
@@ -1,5 +1,7 @@
 use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
-use crate::pac::{CRS, RCC, SYSCFG};
+use crate::pac::RCC;
+#[cfg(crs)]
+use crate::pac::{CRS, SYSCFG};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
 use crate::time::U32Ext;
@@ -180,6 +182,7 @@ pub struct Config {
     pub ahb_pre: AHBPrescaler,
     pub apb1_pre: APBPrescaler,
     pub apb2_pre: APBPrescaler,
+    #[cfg(crs)]
     pub enable_hsi48: bool,
 }
 
@@ -191,6 +194,7 @@ impl Default for Config {
             ahb_pre: AHBPrescaler::NotDivided,
             apb1_pre: APBPrescaler::NotDivided,
             apb2_pre: APBPrescaler::NotDivided,
+            #[cfg(crs)]
             enable_hsi48: false,
         }
     }
@@ -312,6 +316,7 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
+    #[cfg(crs)]
     if config.enable_hsi48 {
         // Reset SYSCFG peripheral
         RCC.apb2rstr().modify(|w| w.set_syscfgrst(true));