From e8d3e865912c304e4c495295360955707fffa07c Mon Sep 17 00:00:00 2001 From: Scott Mabin Date: Sun, 30 Jul 2023 21:22:48 +0100 Subject: [PATCH] stm32f2: Avoid resetting rtc backup domain Also ensure the pwr is enabled before trying to initialize. For the F2 series this is in a seperate clock control register. --- embassy-stm32/src/rtc/v2.rs | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/embassy-stm32/src/rtc/v2.rs b/embassy-stm32/src/rtc/v2.rs index a2eace6d..e3b9dfb8 100644 --- a/embassy-stm32/src/rtc/v2.rs +++ b/embassy-stm32/src/rtc/v2.rs @@ -39,9 +39,8 @@ impl<'d, T: Instance> super::Rtc<'d, T> { let rtcsel = reg.rtcsel().to_bits(); if !reg.rtcen() || rtcsel != clock_config { - #[cfg(not(any(rtc_v2l0, rtc_v2l1)))] + #[cfg(not(any(rtc_v2l0, rtc_v2l1, rtc_v2f2)))] crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true)); - #[cfg(not(any(rtc_v2l0, rtc_v2l1)))] let cr = crate::pac::RCC.bdcr(); #[cfg(any(rtc_v2l0, rtc_v2l1))] @@ -201,6 +200,11 @@ impl sealed::Instance for crate::peripherals::RTC { // read to allow the pwr clock to enable crate::pac::PWR.cr1().read(); } + #[cfg(any(rtc_v2f2))] + { + crate::pac::RCC.apb1enr().modify(|w| w.set_pwren(true)); + crate::pac::PWR.cr().read(); + } } fn read_backup_register(rtc: &Rtc, register: usize) -> Option {