rp: allow for MPU-based stack guards on core 0 as well
using these will require some linker script intervention. setting the core0 stack needs linker intervention anyway (to provide _stack_start), having it also provide _stack_end for the guard to use is not that much of a stretch.
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@ -52,41 +52,20 @@ use core::sync::atomic::{compiler_fence, AtomicBool, Ordering};
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use crate::interrupt::InterruptExt;
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use crate::peripherals::CORE1;
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use crate::{gpio, interrupt, pac};
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use crate::{gpio, install_stack_guard, interrupt, pac};
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const PAUSE_TOKEN: u32 = 0xDEADBEEF;
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const RESUME_TOKEN: u32 = !0xDEADBEEF;
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static IS_CORE1_INIT: AtomicBool = AtomicBool::new(false);
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#[inline(always)]
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fn install_stack_guard(stack_bottom: *mut usize) {
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let core = unsafe { cortex_m::Peripherals::steal() };
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// Trap if MPU is already configured
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if core.MPU.ctrl.read() != 0 {
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fn core1_setup(stack_bottom: *mut usize) {
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if let Err(_) = install_stack_guard(stack_bottom) {
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// currently only happens if the MPU was already set up, which
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// would indicate that the core is already in use from outside
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// embassy, somehow. trap if so since we can't deal with that.
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cortex_m::asm::udf();
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}
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// The minimum we can protect is 32 bytes on a 32 byte boundary, so round up which will
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// just shorten the valid stack range a tad.
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let addr = (stack_bottom as u32 + 31) & !31;
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// Mask is 1 bit per 32 bytes of the 256 byte range... clear the bit for the segment we want
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let subregion_select = 0xff ^ (1 << ((addr >> 5) & 7));
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unsafe {
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core.MPU.ctrl.write(5); // enable mpu with background default map
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core.MPU.rbar.write((addr & !0xff) | (1 << 4)); // set address and update RNR
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core.MPU.rasr.write(
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1 // enable region
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| (0x7 << 1) // size 2^(7 + 1) = 256
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| (subregion_select << 8)
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| 0x10000000, // XN = disable instruction fetch; no other bits means no permissions
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);
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}
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}
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#[inline(always)]
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fn core1_setup(stack_bottom: *mut usize) {
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install_stack_guard(stack_bottom);
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unsafe {
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gpio::init();
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}
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