stm32: fix build for h7ab
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@ -9,11 +9,11 @@ pub const VDDA_CALIB_MV: u32 = 3000;
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/// Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent ADC clock
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/// configuration.
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unsafe fn enable() {
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#[cfg(rcc_h7)]
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#[cfg(stm32h7)]
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crate::pac::RCC.apb2enr().modify(|w| w.set_adcen(true));
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#[cfg(rcc_g0)]
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#[cfg(stm32g0)]
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crate::pac::RCC.apbenr2().modify(|w| w.set_adcen(true));
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#[cfg(rcc_l4)]
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#[cfg(stm32l4)]
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crate::pac::RCC.ahb2enr().modify(|w| w.set_adcen(true));
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}
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@ -54,9 +54,9 @@ pub struct Vref;
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impl<T: Instance> AdcPin<T> for Vref {}
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impl<T: Instance> super::sealed::AdcPin<T> for Vref {
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fn channel(&self) -> u8 {
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#[cfg(not(rcc_g0))]
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#[cfg(not(stm32g0))]
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let val = 0;
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#[cfg(rcc_g0)]
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#[cfg(stm32g0)]
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let val = 13;
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val
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}
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@ -66,9 +66,9 @@ pub struct Temperature;
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impl<T: Instance> AdcPin<T> for Temperature {}
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impl<T: Instance> super::sealed::AdcPin<T> for Temperature {
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fn channel(&self) -> u8 {
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#[cfg(not(rcc_g0))]
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#[cfg(not(stm32g0))]
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let val = 17;
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#[cfg(rcc_g0)]
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#[cfg(stm32g0)]
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let val = 12;
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val
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}
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@ -78,9 +78,9 @@ pub struct Vbat;
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impl<T: Instance> AdcPin<T> for Vbat {}
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impl<T: Instance> super::sealed::AdcPin<T> for Vbat {
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fn channel(&self) -> u8 {
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#[cfg(not(rcc_g0))]
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#[cfg(not(stm32g0))]
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let val = 18;
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#[cfg(rcc_g0)]
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#[cfg(stm32g0)]
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let val = 14;
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val
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}
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@ -281,7 +281,7 @@ impl<'d, T: Instance> Adc<'d, T> {
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/// Calculates the system VDDA by sampling the internal VREF channel and comparing
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/// the result with the value stored at the factory. If the chip's VDDA is not stable, run
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/// this before each ADC conversion.
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#[cfg(not(rcc_g0))] // TODO is this supposed to be public?
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#[cfg(not(stm32g0))] // TODO is this supposed to be public?
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#[allow(unused)] // TODO is this supposed to be public?
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fn calibrate(&mut self, vref: &mut Vref) {
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let vref_cal = unsafe { crate::pac::VREFINTCAL.data().read().value() };
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@ -363,11 +363,11 @@ impl<'d, T: Instance> Adc<'d, T> {
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}
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// Configure ADC
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#[cfg(not(rcc_g0))]
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#[cfg(not(stm32g0))]
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T::regs()
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.cfgr()
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.modify(|reg| reg.set_res(self.resolution.res()));
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#[cfg(rcc_g0)]
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#[cfg(stm32g0)]
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T::regs()
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.cfgr1()
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.modify(|reg| reg.set_res(self.resolution.res()));
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@ -376,9 +376,9 @@ impl<'d, T: Instance> Adc<'d, T> {
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Self::set_channel_sample_time(pin.channel(), self.sample_time);
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// Select channel
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#[cfg(not(rcc_g0))]
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#[cfg(not(stm32g0))]
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T::regs().sqr1().write(|reg| reg.set_sq(0, pin.channel()));
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#[cfg(rcc_g0)]
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#[cfg(stm32g0)]
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T::regs()
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.chselr()
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.write(|reg| reg.set_chsel(pin.channel() as u32));
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@ -400,14 +400,14 @@ impl<'d, T: Instance> Adc<'d, T> {
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}
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}
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#[cfg(rcc_g0)]
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#[cfg(stm32g0)]
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unsafe fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
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T::regs()
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.smpr()
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.modify(|reg| reg.set_smp1(sample_time.sample_time()));
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}
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#[cfg(not(rcc_g0))]
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#[cfg(not(stm32g0))]
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unsafe fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
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if ch <= 9 {
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T::regs()
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