diff --git a/embassy-nrf/src/gpiote.rs b/embassy-nrf/src/gpiote.rs index 4d5fa62b..7f7468a2 100644 --- a/embassy-nrf/src/gpiote.rs +++ b/embassy-nrf/src/gpiote.rs @@ -148,14 +148,14 @@ impl Iterator for BitIter { /// GPIOTE channel driver in input mode pub struct InputChannel<'d, C: Channel, T: GpioPin> { - _ch: PeripheralRef<'d, C>, - _pin: Input<'d, T>, + ch: PeripheralRef<'d, C>, + pin: Input<'d, T>, } impl<'d, C: Channel, T: GpioPin> Drop for InputChannel<'d, C, T> { fn drop(&mut self) { let g = regs(); - let num = self._ch.number(); + let num = self.ch.number(); g.config[num].write(|w| w.mode().disabled()); g.intenclr.write(|w| unsafe { w.bits(1 << num) }); } @@ -185,12 +185,12 @@ impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> { g.events_in[num].reset(); - InputChannel { _ch: ch, _pin: pin } + InputChannel { ch, pin } } pub async fn wait(&self) { let g = regs(); - let num = self._ch.number(); + let num = self.ch.number(); // Enable interrupt g.events_in[num].reset(); @@ -211,20 +211,20 @@ impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> { /// Returns the IN event, for use with PPI. pub fn event_in(&self) -> Event { let g = regs(); - Event::from_reg(&g.events_in[self._ch.number()]) + Event::from_reg(&g.events_in[self.ch.number()]) } } /// GPIOTE channel driver in output mode pub struct OutputChannel<'d, C: Channel, T: GpioPin> { - _ch: PeripheralRef<'d, C>, + ch: PeripheralRef<'d, C>, _pin: Output<'d, T>, } impl<'d, C: Channel, T: GpioPin> Drop for OutputChannel<'d, C, T> { fn drop(&mut self) { let g = regs(); - let num = self._ch.number(); + let num = self.ch.number(); g.config[num].write(|w| w.mode().disabled()); g.intenclr.write(|w| unsafe { w.bits(1 << num) }); } @@ -255,47 +255,47 @@ impl<'d, C: Channel, T: GpioPin> OutputChannel<'d, C, T> { unsafe { w.psel().bits(pin.pin.pin.pin()) } }); - OutputChannel { _ch: ch, _pin: pin } + OutputChannel { ch, _pin: pin } } /// Triggers `task out` (as configured with task_out_polarity, defaults to Toggle). pub fn out(&self) { let g = regs(); - g.tasks_out[self._ch.number()].write(|w| unsafe { w.bits(1) }); + g.tasks_out[self.ch.number()].write(|w| unsafe { w.bits(1) }); } /// Triggers `task set` (set associated pin high). #[cfg(not(feature = "nrf51"))] pub fn set(&self) { let g = regs(); - g.tasks_set[self._ch.number()].write(|w| unsafe { w.bits(1) }); + g.tasks_set[self.ch.number()].write(|w| unsafe { w.bits(1) }); } /// Triggers `task clear` (set associated pin low). #[cfg(not(feature = "nrf51"))] pub fn clear(&self) { let g = regs(); - g.tasks_clr[self._ch.number()].write(|w| unsafe { w.bits(1) }); + g.tasks_clr[self.ch.number()].write(|w| unsafe { w.bits(1) }); } /// Returns the OUT task, for use with PPI. pub fn task_out(&self) -> Task { let g = regs(); - Task::from_reg(&g.tasks_out[self._ch.number()]) + Task::from_reg(&g.tasks_out[self.ch.number()]) } /// Returns the CLR task, for use with PPI. #[cfg(not(feature = "nrf51"))] pub fn task_clr(&self) -> Task { let g = regs(); - Task::from_reg(&g.tasks_clr[self._ch.number()]) + Task::from_reg(&g.tasks_clr[self.ch.number()]) } /// Returns the SET task, for use with PPI. #[cfg(not(feature = "nrf51"))] pub fn task_set(&self) -> Task { let g = regs(); - Task::from_reg(&g.tasks_set[self._ch.number()]) + Task::from_reg(&g.tasks_set[self.ch.number()]) } } @@ -443,11 +443,11 @@ mod eh02 { type Error = Infallible; fn is_high(&self) -> Result { - Ok(self._pin.is_high()) + Ok(self.pin.is_high()) } fn is_low(&self) -> Result { - Ok(self._pin.is_low()) + Ok(self.pin.is_low()) } } } @@ -462,11 +462,11 @@ mod eh1 { impl<'d, C: Channel, T: GpioPin> embedded_hal_1::digital::InputPin for InputChannel<'d, C, T> { fn is_high(&self) -> Result { - Ok(self._pin.is_high()) + Ok(self.pin.is_high()) } fn is_low(&self) -> Result { - Ok(self._pin.is_low()) + Ok(self.pin.is_low()) } } }