stm32: update metapac, includes fix for OTG with 9 endpoints (H7)
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@ -57,7 +57,7 @@ sdio-host = "0.5.0"
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embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
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embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
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critical-section = "1.1"
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critical-section = "1.1"
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atomic-polyfill = "1.0.1"
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atomic-polyfill = "1.0.1"
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stm32-metapac = "10"
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stm32-metapac = "11"
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vcell = "0.1.3"
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vcell = "0.1.3"
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bxcan = "0.7.0"
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bxcan = "0.7.0"
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nb = "1.0.0"
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nb = "1.0.0"
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@ -74,7 +74,7 @@ critical-section = { version = "1.1", features = ["std"] }
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[build-dependencies]
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[build-dependencies]
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proc-macro2 = "1.0.36"
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proc-macro2 = "1.0.36"
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quote = "1.0.15"
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quote = "1.0.15"
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stm32-metapac = { version = "10", default-features = false, features = ["metadata"]}
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stm32-metapac = { version = "11", default-features = false, features = ["metadata"]}
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[features]
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[features]
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default = ["rt"]
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default = ["rt"]
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@ -1,7 +1,7 @@
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use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
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use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
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use crate::pac::RCC;
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use crate::pac::RCC;
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#[cfg(crs)]
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#[cfg(crs)]
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use crate::pac::{CRS, SYSCFG};
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use crate::pac::{crs, CRS, SYSCFG};
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use crate::rcc::{set_freqs, Clocks};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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use crate::time::Hertz;
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@ -338,7 +338,7 @@ pub(crate) unsafe fn init(config: Config) {
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CRS.cfgr().write(|w|
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CRS.cfgr().write(|w|
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// Select LSE as synchronization source
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// Select LSE as synchronization source
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w.set_syncsrc(0b01));
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w.set_syncsrc(crs::vals::Syncsrc::LSE));
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CRS.cr().modify(|w| {
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CRS.cr().modify(|w| {
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w.set_autotrimen(true);
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w.set_autotrimen(true);
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w.set_cen(true);
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w.set_cen(true);
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@ -38,7 +38,9 @@ async fn main(_spawner: Spawner) {
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let p = embassy_stm32::init(config);
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let p = embassy_stm32::init(config);
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info!("Hello World!");
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info!("Hello World!");
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pac::RCC.ccipr().write(|w| w.set_clk48sel(0b10));
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pac::RCC.ccipr().write(|w| {
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w.set_clk48sel(pac::rcc::vals::Clk48sel::PLLQCLK);
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});
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let driver = Driver::new(p.USB, Irqs, p.PA12, p.PA11);
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let driver = Driver::new(p.USB, Irqs, p.PA12, p.PA11);
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