From 0470abb3530785c802fb81d0e16fae518766eac6 Mon Sep 17 00:00:00 2001 From: Bob McWhirter Date: Mon, 10 May 2021 15:21:57 -0400 Subject: [PATCH 1/8] Checkpoint. --- embassy-stm32/Cargo.toml | 160 ++++++++++++++------------- embassy-stm32/gen.py | 3 + embassy-stm32/src/lib.rs | 2 + embassy-stm32/src/pac/stm32f429zi.rs | 32 +++--- embassy-stm32/src/pac/stm32l431cb.rs | 9 +- embassy-stm32/src/pac/stm32l431cc.rs | 9 +- embassy-stm32/src/pac/stm32l431kb.rs | 7 +- embassy-stm32/src/pac/stm32l431kc.rs | 7 +- embassy-stm32/src/pac/stm32l431rb.rs | 9 +- embassy-stm32/src/pac/stm32l431rc.rs | 9 +- embassy-stm32/src/pac/stm32l431vc.rs | 9 +- embassy-stm32/src/pac/stm32l432kb.rs | 8 +- embassy-stm32/src/pac/stm32l432kc.rs | 8 +- embassy-stm32/src/pac/stm32l433cb.rs | 9 +- embassy-stm32/src/pac/stm32l433cc.rs | 9 +- embassy-stm32/src/pac/stm32l433rb.rs | 9 +- embassy-stm32/src/pac/stm32l433rc.rs | 9 +- embassy-stm32/src/pac/stm32l433vc.rs | 9 +- embassy-stm32/src/pac/stm32l442kc.rs | 8 +- embassy-stm32/src/pac/stm32l443cc.rs | 9 +- embassy-stm32/src/pac/stm32l443rc.rs | 9 +- embassy-stm32/src/pac/stm32l443vc.rs | 9 +- embassy-stm32/src/pac/stm32l496ae.rs | 9 +- embassy-stm32/src/pac/stm32l496ag.rs | 9 +- embassy-stm32/src/pac/stm32l496qe.rs | 9 +- embassy-stm32/src/pac/stm32l496qg.rs | 9 +- embassy-stm32/src/pac/stm32l496re.rs | 9 +- embassy-stm32/src/pac/stm32l496rg.rs | 9 +- embassy-stm32/src/pac/stm32l496ve.rs | 9 +- embassy-stm32/src/pac/stm32l496vg.rs | 9 +- embassy-stm32/src/pac/stm32l496wg.rs | 9 +- embassy-stm32/src/pac/stm32l496ze.rs | 9 +- embassy-stm32/src/pac/stm32l496zg.rs | 9 +- embassy-stm32/src/pac/stm32l4a6ag.rs | 9 +- embassy-stm32/src/pac/stm32l4a6qg.rs | 9 +- embassy-stm32/src/pac/stm32l4a6rg.rs | 9 +- embassy-stm32/src/pac/stm32l4a6vg.rs | 9 +- embassy-stm32/src/pac/stm32l4a6zg.rs | 9 +- embassy-stm32/src/pac/stm32l4p5ae.rs | 9 +- embassy-stm32/src/pac/stm32l4p5ag.rs | 9 +- embassy-stm32/src/pac/stm32l4p5ce.rs | 9 +- embassy-stm32/src/pac/stm32l4p5cg.rs | 9 +- embassy-stm32/src/pac/stm32l4p5qe.rs | 9 +- embassy-stm32/src/pac/stm32l4p5qg.rs | 9 +- embassy-stm32/src/pac/stm32l4p5re.rs | 9 +- embassy-stm32/src/pac/stm32l4p5rg.rs | 9 +- embassy-stm32/src/pac/stm32l4p5ve.rs | 9 +- embassy-stm32/src/pac/stm32l4p5vg.rs | 9 +- embassy-stm32/src/pac/stm32l4p5ze.rs | 9 +- embassy-stm32/src/pac/stm32l4p5zg.rs | 9 +- embassy-stm32/src/pac/stm32l4q5ag.rs | 9 +- embassy-stm32/src/pac/stm32l4q5cg.rs | 9 +- embassy-stm32/src/pac/stm32l4q5qg.rs | 9 +- embassy-stm32/src/pac/stm32l4q5rg.rs | 9 +- embassy-stm32/src/pac/stm32l4q5vg.rs | 9 +- embassy-stm32/src/pac/stm32l4q5zg.rs | 9 +- embassy-stm32/src/pac/stm32l4r5ag.rs | 9 +- embassy-stm32/src/pac/stm32l4r5ai.rs | 9 +- embassy-stm32/src/pac/stm32l4r5qg.rs | 9 +- embassy-stm32/src/pac/stm32l4r5qi.rs | 9 +- embassy-stm32/src/pac/stm32l4r5vg.rs | 9 +- embassy-stm32/src/pac/stm32l4r5vi.rs | 9 +- embassy-stm32/src/pac/stm32l4r5zg.rs | 9 +- embassy-stm32/src/pac/stm32l4r5zi.rs | 9 +- embassy-stm32/src/pac/stm32l4r7ai.rs | 9 +- embassy-stm32/src/pac/stm32l4r7vi.rs | 9 +- embassy-stm32/src/pac/stm32l4r7zi.rs | 9 +- embassy-stm32/src/pac/stm32l4r9ag.rs | 9 +- embassy-stm32/src/pac/stm32l4r9ai.rs | 9 +- embassy-stm32/src/pac/stm32l4r9vg.rs | 9 +- embassy-stm32/src/pac/stm32l4r9vi.rs | 9 +- embassy-stm32/src/pac/stm32l4r9zg.rs | 9 +- embassy-stm32/src/pac/stm32l4r9zi.rs | 9 +- embassy-stm32/src/pac/stm32l4s5ai.rs | 9 +- embassy-stm32/src/pac/stm32l4s5qi.rs | 9 +- embassy-stm32/src/pac/stm32l4s5vi.rs | 9 +- embassy-stm32/src/pac/stm32l4s5zi.rs | 9 +- embassy-stm32/src/pac/stm32l4s7ai.rs | 9 +- embassy-stm32/src/pac/stm32l4s7vi.rs | 9 +- embassy-stm32/src/pac/stm32l4s7zi.rs | 9 +- embassy-stm32/src/pac/stm32l4s9ai.rs | 9 +- embassy-stm32/src/pac/stm32l4s9vi.rs | 9 +- embassy-stm32/src/pac/stm32l4s9zi.rs | 9 +- embassy-stm32/src/spi.rs | 62 +++++++++++ 84 files changed, 789 insertions(+), 174 deletions(-) create mode 100644 embassy-stm32/src/spi.rs diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml index 7d4bee29..cd940c58 100644 --- a/embassy-stm32/Cargo.toml +++ b/embassy-stm32/Cargo.toml @@ -189,24 +189,24 @@ stm32l422cb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_r stm32l422kb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] stm32l422rb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] stm32l422tb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l431cb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l431cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l431kb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l431kc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l431rb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l431rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l431vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l432kb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l432kc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l433cb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l433cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l433rb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l433rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l433vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l442kc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l443cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l443rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l443vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l431cb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l431cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l431kb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l431kc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l431rb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l431rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l431vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l432kb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l432kc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l433cb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l433cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l433rb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l433rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l433vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l442kc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l443cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l443rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l443vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] stm32l451cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] stm32l451ce = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] stm32l451rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] @@ -257,67 +257,67 @@ stm32l486qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_r stm32l486rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] stm32l486vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] stm32l486zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l496ae = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l496ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l496qe = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l496qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l496re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l496rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l496ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l496vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l496wg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l496ze = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l496zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l4a6ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l4a6qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l4a6rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l4a6vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l4a6zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] -stm32l4p5ae = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4p5ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4p5ce = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4p5cg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4p5qe = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4p5qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4p5re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4p5rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4p5ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4p5vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4p5ze = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4p5zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4q5ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4q5cg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4q5qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4q5rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4q5vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4q5zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r5ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r5ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r5qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r5qi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r5vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r5vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r5zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r5zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r7ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r7vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r7zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r9ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r9ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r9vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r9vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r9zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4r9zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4s5ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4s5qi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4s5vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4s5zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4s7ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4s7vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4s7zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4s9ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4s9vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] -stm32l4s9zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l496ae = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496qe = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496wg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496ze = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l4a6ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l4a6qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l4a6rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l4a6vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l4a6zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l4p5ae = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5ce = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5cg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5qe = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5ze = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4q5ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4q5cg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4q5qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4q5rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4q5vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4q5zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r5ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r5ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r5qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r5qi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r5vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r5vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r5zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r5zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r7ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r7vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r7zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r9ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r9ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r9vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r9vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r9zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r9zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s5ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s5qi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s5vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s5zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s7ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s7vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s7zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s9ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s9vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s9zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] _dma = [] _dma_v1 = [] _dma_v2 = [] @@ -327,6 +327,8 @@ _gpio = [] _gpio_v2 = [] _rng = [ "rand_core",] _rng_v1 = [] +_spi = [] +_spi_v2 = [] _stm32f4 = [] _stm32l4 = [] _stm32l4p = [] diff --git a/embassy-stm32/gen.py b/embassy-stm32/gen.py index ce4bdc1d..c04de7d4 100644 --- a/embassy-stm32/gen.py +++ b/embassy-stm32/gen.py @@ -115,6 +115,9 @@ for chip in chips.values(): if block_mod == 'rng': f.write(f'impl_rng!({name});') + if block_mod == 'spi': + f.write(f'impl_spi!({name});') + if block_mod == 'gpio': custom_singletons = True port = name[4:] diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs index 3ec6013a..6f300263 100644 --- a/embassy-stm32/src/lib.rs +++ b/embassy-stm32/src/lib.rs @@ -17,11 +17,13 @@ pub mod exti; pub mod gpio; #[cfg(feature = "_rng")] pub mod rng; +pub mod spi; #[cfg(feature = "_usart")] pub mod usart; // This must go LAST so that it sees the `impl_foo!` macros mod pac; + pub use embassy_macros::interrupt; pub use pac::{interrupt, peripherals, Peripherals}; diff --git a/embassy-stm32/src/pac/stm32f429zi.rs b/embassy-stm32/src/pac/stm32f429zi.rs index a1a3ab42..b76378e0 100644 --- a/embassy-stm32/src/pac/stm32f429zi.rs +++ b/embassy-stm32/src/pac/stm32f429zi.rs @@ -6,23 +6,23 @@ pub fn GPIO(n: usize) -> gpio::Gpio { gpio::Gpio((0x40020000 + 0x400 * n) as _) } pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); -impl_dma_channel!(DMA1_CH0, DMA1, 0); -impl_dma_channel!(DMA1_CH1, DMA1, 1); -impl_dma_channel!(DMA1_CH2, DMA1, 2); -impl_dma_channel!(DMA1_CH3, DMA1, 3); -impl_dma_channel!(DMA1_CH4, DMA1, 4); -impl_dma_channel!(DMA1_CH5, DMA1, 5); -impl_dma_channel!(DMA1_CH6, DMA1, 6); -impl_dma_channel!(DMA1_CH7, DMA1, 7); +impl_dma_channel!(DMA1_CH0, 1, 0); +impl_dma_channel!(DMA1_CH1, 1, 1); +impl_dma_channel!(DMA1_CH2, 1, 2); +impl_dma_channel!(DMA1_CH3, 1, 3); +impl_dma_channel!(DMA1_CH4, 1, 4); +impl_dma_channel!(DMA1_CH5, 1, 5); +impl_dma_channel!(DMA1_CH6, 1, 6); +impl_dma_channel!(DMA1_CH7, 1, 7); pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); -impl_dma_channel!(DMA2_CH0, DMA2, 0); -impl_dma_channel!(DMA2_CH1, DMA2, 1); -impl_dma_channel!(DMA2_CH2, DMA2, 2); -impl_dma_channel!(DMA2_CH3, DMA2, 3); -impl_dma_channel!(DMA2_CH4, DMA2, 4); -impl_dma_channel!(DMA2_CH5, DMA2, 5); -impl_dma_channel!(DMA2_CH6, DMA2, 6); -impl_dma_channel!(DMA2_CH7, DMA2, 7); +impl_dma_channel!(DMA2_CH0, 2, 0); +impl_dma_channel!(DMA2_CH1, 2, 1); +impl_dma_channel!(DMA2_CH2, 2, 2); +impl_dma_channel!(DMA2_CH3, 2, 3); +impl_dma_channel!(DMA2_CH4, 2, 4); +impl_dma_channel!(DMA2_CH5, 2, 5); +impl_dma_channel!(DMA2_CH6, 2, 6); +impl_dma_channel!(DMA2_CH7, 2, 7); pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); impl_gpio_pin!(PA0, 0, 0, EXTI0); diff --git a/embassy-stm32/src/pac/stm32l431cb.rs b/embassy-stm32/src/pac/stm32l431cb.rs index cab88d7a..4201a530 100644 --- a/embassy-stm32/src/pac/stm32l431cb.rs +++ b/embassy-stm32/src/pac/stm32l431cb.rs @@ -128,6 +128,12 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -180,6 +186,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -194,7 +201,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l431cc.rs b/embassy-stm32/src/pac/stm32l431cc.rs index cab88d7a..4201a530 100644 --- a/embassy-stm32/src/pac/stm32l431cc.rs +++ b/embassy-stm32/src/pac/stm32l431cc.rs @@ -128,6 +128,12 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -180,6 +186,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -194,7 +201,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l431kb.rs b/embassy-stm32/src/pac/stm32l431kb.rs index cb3c2eb5..088aa064 100644 --- a/embassy-stm32/src/pac/stm32l431kb.rs +++ b/embassy-stm32/src/pac/stm32l431kb.rs @@ -128,6 +128,10 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -158,6 +162,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -172,7 +177,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2 + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI3, SYSCFG, USART1, USART2 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l431kc.rs b/embassy-stm32/src/pac/stm32l431kc.rs index cb3c2eb5..088aa064 100644 --- a/embassy-stm32/src/pac/stm32l431kc.rs +++ b/embassy-stm32/src/pac/stm32l431kc.rs @@ -128,6 +128,10 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -158,6 +162,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -172,7 +177,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2 + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI3, SYSCFG, USART1, USART2 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l431rb.rs b/embassy-stm32/src/pac/stm32l431rb.rs index cab88d7a..4201a530 100644 --- a/embassy-stm32/src/pac/stm32l431rb.rs +++ b/embassy-stm32/src/pac/stm32l431rb.rs @@ -128,6 +128,12 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -180,6 +186,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -194,7 +201,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l431rc.rs b/embassy-stm32/src/pac/stm32l431rc.rs index cab88d7a..4201a530 100644 --- a/embassy-stm32/src/pac/stm32l431rc.rs +++ b/embassy-stm32/src/pac/stm32l431rc.rs @@ -128,6 +128,12 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -180,6 +186,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -194,7 +201,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l431vc.rs b/embassy-stm32/src/pac/stm32l431vc.rs index cab88d7a..4201a530 100644 --- a/embassy-stm32/src/pac/stm32l431vc.rs +++ b/embassy-stm32/src/pac/stm32l431vc.rs @@ -128,6 +128,12 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -180,6 +186,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -194,7 +201,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l432kb.rs b/embassy-stm32/src/pac/stm32l432kb.rs index 78ef53b1..a9dd16c9 100644 --- a/embassy-stm32/src/pac/stm32l432kb.rs +++ b/embassy-stm32/src/pac/stm32l432kb.rs @@ -94,6 +94,10 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -119,6 +123,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -131,7 +136,8 @@ peripherals!( PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, - PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2 + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI3, SYSCFG, USART1, + USART2 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l432kc.rs b/embassy-stm32/src/pac/stm32l432kc.rs index 78ef53b1..a9dd16c9 100644 --- a/embassy-stm32/src/pac/stm32l432kc.rs +++ b/embassy-stm32/src/pac/stm32l432kc.rs @@ -94,6 +94,10 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -119,6 +123,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -131,7 +136,8 @@ peripherals!( PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, - PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2 + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI3, SYSCFG, USART1, + USART2 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l433cb.rs b/embassy-stm32/src/pac/stm32l433cb.rs index 2736824d..3d3c1e40 100644 --- a/embassy-stm32/src/pac/stm32l433cb.rs +++ b/embassy-stm32/src/pac/stm32l433cb.rs @@ -128,6 +128,12 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -180,6 +186,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -194,7 +201,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l433cc.rs b/embassy-stm32/src/pac/stm32l433cc.rs index 2736824d..3d3c1e40 100644 --- a/embassy-stm32/src/pac/stm32l433cc.rs +++ b/embassy-stm32/src/pac/stm32l433cc.rs @@ -128,6 +128,12 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -180,6 +186,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -194,7 +201,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l433rb.rs b/embassy-stm32/src/pac/stm32l433rb.rs index 2736824d..3d3c1e40 100644 --- a/embassy-stm32/src/pac/stm32l433rb.rs +++ b/embassy-stm32/src/pac/stm32l433rb.rs @@ -128,6 +128,12 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -180,6 +186,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -194,7 +201,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l433rc.rs b/embassy-stm32/src/pac/stm32l433rc.rs index 2736824d..3d3c1e40 100644 --- a/embassy-stm32/src/pac/stm32l433rc.rs +++ b/embassy-stm32/src/pac/stm32l433rc.rs @@ -128,6 +128,12 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -180,6 +186,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -194,7 +201,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l433vc.rs b/embassy-stm32/src/pac/stm32l433vc.rs index 2736824d..3d3c1e40 100644 --- a/embassy-stm32/src/pac/stm32l433vc.rs +++ b/embassy-stm32/src/pac/stm32l433vc.rs @@ -128,6 +128,12 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -180,6 +186,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -194,7 +201,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l442kc.rs b/embassy-stm32/src/pac/stm32l442kc.rs index 2bcd51e9..b193e51e 100644 --- a/embassy-stm32/src/pac/stm32l442kc.rs +++ b/embassy-stm32/src/pac/stm32l442kc.rs @@ -94,6 +94,10 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -119,6 +123,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -131,7 +136,8 @@ peripherals!( PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, - PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2 + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI3, SYSCFG, USART1, + USART2 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l443cc.rs b/embassy-stm32/src/pac/stm32l443cc.rs index 93f7c8bf..ed14584f 100644 --- a/embassy-stm32/src/pac/stm32l443cc.rs +++ b/embassy-stm32/src/pac/stm32l443cc.rs @@ -128,6 +128,12 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -180,6 +186,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -194,7 +201,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l443rc.rs b/embassy-stm32/src/pac/stm32l443rc.rs index 93f7c8bf..ed14584f 100644 --- a/embassy-stm32/src/pac/stm32l443rc.rs +++ b/embassy-stm32/src/pac/stm32l443rc.rs @@ -128,6 +128,12 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -180,6 +186,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -194,7 +201,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l443vc.rs b/embassy-stm32/src/pac/stm32l443vc.rs index 93f7c8bf..ed14584f 100644 --- a/embassy-stm32/src/pac/stm32l443vc.rs +++ b/embassy-stm32/src/pac/stm32l443vc.rs @@ -128,6 +128,12 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -180,6 +186,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -194,7 +201,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l496ae.rs b/embassy-stm32/src/pac/stm32l496ae.rs index 336533a1..3f97aeec 100644 --- a/embassy-stm32/src/pac/stm32l496ae.rs +++ b/embassy-stm32/src/pac/stm32l496ae.rs @@ -179,6 +179,12 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -236,6 +242,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -253,7 +260,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l496ag.rs b/embassy-stm32/src/pac/stm32l496ag.rs index 336533a1..3f97aeec 100644 --- a/embassy-stm32/src/pac/stm32l496ag.rs +++ b/embassy-stm32/src/pac/stm32l496ag.rs @@ -179,6 +179,12 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -236,6 +242,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -253,7 +260,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l496qe.rs b/embassy-stm32/src/pac/stm32l496qe.rs index 336533a1..3f97aeec 100644 --- a/embassy-stm32/src/pac/stm32l496qe.rs +++ b/embassy-stm32/src/pac/stm32l496qe.rs @@ -179,6 +179,12 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -236,6 +242,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -253,7 +260,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l496qg.rs b/embassy-stm32/src/pac/stm32l496qg.rs index 336533a1..3f97aeec 100644 --- a/embassy-stm32/src/pac/stm32l496qg.rs +++ b/embassy-stm32/src/pac/stm32l496qg.rs @@ -179,6 +179,12 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -236,6 +242,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -253,7 +260,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l496re.rs b/embassy-stm32/src/pac/stm32l496re.rs index 336533a1..3f97aeec 100644 --- a/embassy-stm32/src/pac/stm32l496re.rs +++ b/embassy-stm32/src/pac/stm32l496re.rs @@ -179,6 +179,12 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -236,6 +242,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -253,7 +260,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l496rg.rs b/embassy-stm32/src/pac/stm32l496rg.rs index 336533a1..3f97aeec 100644 --- a/embassy-stm32/src/pac/stm32l496rg.rs +++ b/embassy-stm32/src/pac/stm32l496rg.rs @@ -179,6 +179,12 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -236,6 +242,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -253,7 +260,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l496ve.rs b/embassy-stm32/src/pac/stm32l496ve.rs index 336533a1..3f97aeec 100644 --- a/embassy-stm32/src/pac/stm32l496ve.rs +++ b/embassy-stm32/src/pac/stm32l496ve.rs @@ -179,6 +179,12 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -236,6 +242,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -253,7 +260,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l496vg.rs b/embassy-stm32/src/pac/stm32l496vg.rs index 336533a1..3f97aeec 100644 --- a/embassy-stm32/src/pac/stm32l496vg.rs +++ b/embassy-stm32/src/pac/stm32l496vg.rs @@ -179,6 +179,12 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -236,6 +242,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -253,7 +260,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l496wg.rs b/embassy-stm32/src/pac/stm32l496wg.rs index 336533a1..3f97aeec 100644 --- a/embassy-stm32/src/pac/stm32l496wg.rs +++ b/embassy-stm32/src/pac/stm32l496wg.rs @@ -179,6 +179,12 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -236,6 +242,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -253,7 +260,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l496ze.rs b/embassy-stm32/src/pac/stm32l496ze.rs index 336533a1..3f97aeec 100644 --- a/embassy-stm32/src/pac/stm32l496ze.rs +++ b/embassy-stm32/src/pac/stm32l496ze.rs @@ -179,6 +179,12 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -236,6 +242,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -253,7 +260,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l496zg.rs b/embassy-stm32/src/pac/stm32l496zg.rs index 336533a1..3f97aeec 100644 --- a/embassy-stm32/src/pac/stm32l496zg.rs +++ b/embassy-stm32/src/pac/stm32l496zg.rs @@ -179,6 +179,12 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -236,6 +242,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -253,7 +260,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4a6ag.rs b/embassy-stm32/src/pac/stm32l4a6ag.rs index 2bc67165..2fc3593f 100644 --- a/embassy-stm32/src/pac/stm32l4a6ag.rs +++ b/embassy-stm32/src/pac/stm32l4a6ag.rs @@ -179,6 +179,12 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -236,6 +242,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -253,7 +260,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4a6qg.rs b/embassy-stm32/src/pac/stm32l4a6qg.rs index 2bc67165..2fc3593f 100644 --- a/embassy-stm32/src/pac/stm32l4a6qg.rs +++ b/embassy-stm32/src/pac/stm32l4a6qg.rs @@ -179,6 +179,12 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -236,6 +242,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -253,7 +260,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4a6rg.rs b/embassy-stm32/src/pac/stm32l4a6rg.rs index 2bc67165..2fc3593f 100644 --- a/embassy-stm32/src/pac/stm32l4a6rg.rs +++ b/embassy-stm32/src/pac/stm32l4a6rg.rs @@ -179,6 +179,12 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -236,6 +242,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -253,7 +260,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4a6vg.rs b/embassy-stm32/src/pac/stm32l4a6vg.rs index 2bc67165..2fc3593f 100644 --- a/embassy-stm32/src/pac/stm32l4a6vg.rs +++ b/embassy-stm32/src/pac/stm32l4a6vg.rs @@ -179,6 +179,12 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -236,6 +242,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -253,7 +260,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4a6zg.rs b/embassy-stm32/src/pac/stm32l4a6zg.rs index 2bc67165..2fc3593f 100644 --- a/embassy-stm32/src/pac/stm32l4a6zg.rs +++ b/embassy-stm32/src/pac/stm32l4a6zg.rs @@ -179,6 +179,12 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); @@ -236,6 +242,7 @@ pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; pub use regs::usart_v2 as usart; mod regs; @@ -253,7 +260,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4p5ae.rs b/embassy-stm32/src/pac/stm32l4p5ae.rs index 7d8ca086..ae3342f4 100644 --- a/embassy-stm32/src/pac/stm32l4p5ae.rs +++ b/embassy-stm32/src/pac/stm32l4p5ae.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4p5ag.rs b/embassy-stm32/src/pac/stm32l4p5ag.rs index 7d8ca086..ae3342f4 100644 --- a/embassy-stm32/src/pac/stm32l4p5ag.rs +++ b/embassy-stm32/src/pac/stm32l4p5ag.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4p5ce.rs b/embassy-stm32/src/pac/stm32l4p5ce.rs index 7d8ca086..ae3342f4 100644 --- a/embassy-stm32/src/pac/stm32l4p5ce.rs +++ b/embassy-stm32/src/pac/stm32l4p5ce.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4p5cg.rs b/embassy-stm32/src/pac/stm32l4p5cg.rs index 7d8ca086..ae3342f4 100644 --- a/embassy-stm32/src/pac/stm32l4p5cg.rs +++ b/embassy-stm32/src/pac/stm32l4p5cg.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4p5qe.rs b/embassy-stm32/src/pac/stm32l4p5qe.rs index 7d8ca086..ae3342f4 100644 --- a/embassy-stm32/src/pac/stm32l4p5qe.rs +++ b/embassy-stm32/src/pac/stm32l4p5qe.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4p5qg.rs b/embassy-stm32/src/pac/stm32l4p5qg.rs index 7d8ca086..ae3342f4 100644 --- a/embassy-stm32/src/pac/stm32l4p5qg.rs +++ b/embassy-stm32/src/pac/stm32l4p5qg.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4p5re.rs b/embassy-stm32/src/pac/stm32l4p5re.rs index 7d8ca086..ae3342f4 100644 --- a/embassy-stm32/src/pac/stm32l4p5re.rs +++ b/embassy-stm32/src/pac/stm32l4p5re.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4p5rg.rs b/embassy-stm32/src/pac/stm32l4p5rg.rs index 7d8ca086..ae3342f4 100644 --- a/embassy-stm32/src/pac/stm32l4p5rg.rs +++ b/embassy-stm32/src/pac/stm32l4p5rg.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4p5ve.rs b/embassy-stm32/src/pac/stm32l4p5ve.rs index 7d8ca086..ae3342f4 100644 --- a/embassy-stm32/src/pac/stm32l4p5ve.rs +++ b/embassy-stm32/src/pac/stm32l4p5ve.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4p5vg.rs b/embassy-stm32/src/pac/stm32l4p5vg.rs index 7d8ca086..ae3342f4 100644 --- a/embassy-stm32/src/pac/stm32l4p5vg.rs +++ b/embassy-stm32/src/pac/stm32l4p5vg.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4p5ze.rs b/embassy-stm32/src/pac/stm32l4p5ze.rs index 7d8ca086..ae3342f4 100644 --- a/embassy-stm32/src/pac/stm32l4p5ze.rs +++ b/embassy-stm32/src/pac/stm32l4p5ze.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4p5zg.rs b/embassy-stm32/src/pac/stm32l4p5zg.rs index 7d8ca086..ae3342f4 100644 --- a/embassy-stm32/src/pac/stm32l4p5zg.rs +++ b/embassy-stm32/src/pac/stm32l4p5zg.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4q5ag.rs b/embassy-stm32/src/pac/stm32l4q5ag.rs index 03c5b679..2313edd8 100644 --- a/embassy-stm32/src/pac/stm32l4q5ag.rs +++ b/embassy-stm32/src/pac/stm32l4q5ag.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4q5cg.rs b/embassy-stm32/src/pac/stm32l4q5cg.rs index 03c5b679..2313edd8 100644 --- a/embassy-stm32/src/pac/stm32l4q5cg.rs +++ b/embassy-stm32/src/pac/stm32l4q5cg.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4q5qg.rs b/embassy-stm32/src/pac/stm32l4q5qg.rs index 03c5b679..2313edd8 100644 --- a/embassy-stm32/src/pac/stm32l4q5qg.rs +++ b/embassy-stm32/src/pac/stm32l4q5qg.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4q5rg.rs b/embassy-stm32/src/pac/stm32l4q5rg.rs index 03c5b679..2313edd8 100644 --- a/embassy-stm32/src/pac/stm32l4q5rg.rs +++ b/embassy-stm32/src/pac/stm32l4q5rg.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4q5vg.rs b/embassy-stm32/src/pac/stm32l4q5vg.rs index 03c5b679..2313edd8 100644 --- a/embassy-stm32/src/pac/stm32l4q5vg.rs +++ b/embassy-stm32/src/pac/stm32l4q5vg.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4q5zg.rs b/embassy-stm32/src/pac/stm32l4q5zg.rs index 03c5b679..2313edd8 100644 --- a/embassy-stm32/src/pac/stm32l4q5zg.rs +++ b/embassy-stm32/src/pac/stm32l4q5zg.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r5ag.rs b/embassy-stm32/src/pac/stm32l4r5ag.rs index 70339417..c9741414 100644 --- a/embassy-stm32/src/pac/stm32l4r5ag.rs +++ b/embassy-stm32/src/pac/stm32l4r5ag.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r5ai.rs b/embassy-stm32/src/pac/stm32l4r5ai.rs index 70339417..c9741414 100644 --- a/embassy-stm32/src/pac/stm32l4r5ai.rs +++ b/embassy-stm32/src/pac/stm32l4r5ai.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r5qg.rs b/embassy-stm32/src/pac/stm32l4r5qg.rs index 70339417..c9741414 100644 --- a/embassy-stm32/src/pac/stm32l4r5qg.rs +++ b/embassy-stm32/src/pac/stm32l4r5qg.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r5qi.rs b/embassy-stm32/src/pac/stm32l4r5qi.rs index 70339417..c9741414 100644 --- a/embassy-stm32/src/pac/stm32l4r5qi.rs +++ b/embassy-stm32/src/pac/stm32l4r5qi.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r5vg.rs b/embassy-stm32/src/pac/stm32l4r5vg.rs index 70339417..c9741414 100644 --- a/embassy-stm32/src/pac/stm32l4r5vg.rs +++ b/embassy-stm32/src/pac/stm32l4r5vg.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r5vi.rs b/embassy-stm32/src/pac/stm32l4r5vi.rs index 70339417..c9741414 100644 --- a/embassy-stm32/src/pac/stm32l4r5vi.rs +++ b/embassy-stm32/src/pac/stm32l4r5vi.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r5zg.rs b/embassy-stm32/src/pac/stm32l4r5zg.rs index 70339417..c9741414 100644 --- a/embassy-stm32/src/pac/stm32l4r5zg.rs +++ b/embassy-stm32/src/pac/stm32l4r5zg.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r5zi.rs b/embassy-stm32/src/pac/stm32l4r5zi.rs index 70339417..c9741414 100644 --- a/embassy-stm32/src/pac/stm32l4r5zi.rs +++ b/embassy-stm32/src/pac/stm32l4r5zi.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r7ai.rs b/embassy-stm32/src/pac/stm32l4r7ai.rs index 9d88e59a..62ec3567 100644 --- a/embassy-stm32/src/pac/stm32l4r7ai.rs +++ b/embassy-stm32/src/pac/stm32l4r7ai.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r7vi.rs b/embassy-stm32/src/pac/stm32l4r7vi.rs index 9d88e59a..62ec3567 100644 --- a/embassy-stm32/src/pac/stm32l4r7vi.rs +++ b/embassy-stm32/src/pac/stm32l4r7vi.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r7zi.rs b/embassy-stm32/src/pac/stm32l4r7zi.rs index 9d88e59a..62ec3567 100644 --- a/embassy-stm32/src/pac/stm32l4r7zi.rs +++ b/embassy-stm32/src/pac/stm32l4r7zi.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r9ag.rs b/embassy-stm32/src/pac/stm32l4r9ag.rs index edb5287c..dedc3788 100644 --- a/embassy-stm32/src/pac/stm32l4r9ag.rs +++ b/embassy-stm32/src/pac/stm32l4r9ag.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r9ai.rs b/embassy-stm32/src/pac/stm32l4r9ai.rs index edb5287c..dedc3788 100644 --- a/embassy-stm32/src/pac/stm32l4r9ai.rs +++ b/embassy-stm32/src/pac/stm32l4r9ai.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r9vg.rs b/embassy-stm32/src/pac/stm32l4r9vg.rs index edb5287c..dedc3788 100644 --- a/embassy-stm32/src/pac/stm32l4r9vg.rs +++ b/embassy-stm32/src/pac/stm32l4r9vg.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r9vi.rs b/embassy-stm32/src/pac/stm32l4r9vi.rs index edb5287c..dedc3788 100644 --- a/embassy-stm32/src/pac/stm32l4r9vi.rs +++ b/embassy-stm32/src/pac/stm32l4r9vi.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r9zg.rs b/embassy-stm32/src/pac/stm32l4r9zg.rs index edb5287c..dedc3788 100644 --- a/embassy-stm32/src/pac/stm32l4r9zg.rs +++ b/embassy-stm32/src/pac/stm32l4r9zg.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4r9zi.rs b/embassy-stm32/src/pac/stm32l4r9zi.rs index edb5287c..dedc3788 100644 --- a/embassy-stm32/src/pac/stm32l4r9zi.rs +++ b/embassy-stm32/src/pac/stm32l4r9zi.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4s5ai.rs b/embassy-stm32/src/pac/stm32l4s5ai.rs index e7d2eb0c..95c47ae1 100644 --- a/embassy-stm32/src/pac/stm32l4s5ai.rs +++ b/embassy-stm32/src/pac/stm32l4s5ai.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4s5qi.rs b/embassy-stm32/src/pac/stm32l4s5qi.rs index e7d2eb0c..95c47ae1 100644 --- a/embassy-stm32/src/pac/stm32l4s5qi.rs +++ b/embassy-stm32/src/pac/stm32l4s5qi.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4s5vi.rs b/embassy-stm32/src/pac/stm32l4s5vi.rs index e7d2eb0c..95c47ae1 100644 --- a/embassy-stm32/src/pac/stm32l4s5vi.rs +++ b/embassy-stm32/src/pac/stm32l4s5vi.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4s5zi.rs b/embassy-stm32/src/pac/stm32l4s5zi.rs index e7d2eb0c..95c47ae1 100644 --- a/embassy-stm32/src/pac/stm32l4s5zi.rs +++ b/embassy-stm32/src/pac/stm32l4s5zi.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4s7ai.rs b/embassy-stm32/src/pac/stm32l4s7ai.rs index 072ffc23..6ff9debf 100644 --- a/embassy-stm32/src/pac/stm32l4s7ai.rs +++ b/embassy-stm32/src/pac/stm32l4s7ai.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4s7vi.rs b/embassy-stm32/src/pac/stm32l4s7vi.rs index 072ffc23..6ff9debf 100644 --- a/embassy-stm32/src/pac/stm32l4s7vi.rs +++ b/embassy-stm32/src/pac/stm32l4s7vi.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4s7zi.rs b/embassy-stm32/src/pac/stm32l4s7zi.rs index 072ffc23..6ff9debf 100644 --- a/embassy-stm32/src/pac/stm32l4s7zi.rs +++ b/embassy-stm32/src/pac/stm32l4s7zi.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4s9ai.rs b/embassy-stm32/src/pac/stm32l4s9ai.rs index c3ef398d..7031b3ac 100644 --- a/embassy-stm32/src/pac/stm32l4s9ai.rs +++ b/embassy-stm32/src/pac/stm32l4s9ai.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4s9vi.rs b/embassy-stm32/src/pac/stm32l4s9vi.rs index c3ef398d..7031b3ac 100644 --- a/embassy-stm32/src/pac/stm32l4s9vi.rs +++ b/embassy-stm32/src/pac/stm32l4s9vi.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32l4s9zi.rs b/embassy-stm32/src/pac/stm32l4s9zi.rs index c3ef398d..7031b3ac 100644 --- a/embassy-stm32/src/pac/stm32l4s9zi.rs +++ b/embassy-stm32/src/pac/stm32l4s9zi.rs @@ -179,11 +179,18 @@ impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; pub use regs::syscfg_l4 as syscfg; mod regs; use embassy_extras::peripherals; @@ -200,7 +207,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG ); pub mod interrupt { diff --git a/embassy-stm32/src/spi.rs b/embassy-stm32/src/spi.rs new file mode 100644 index 00000000..b4b1d3d8 --- /dev/null +++ b/embassy-stm32/src/spi.rs @@ -0,0 +1,62 @@ +pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; +use core::marker::PhantomData; +use embassy::interrupt::Interrupt; +use embedded_hal::blocking::spi::Write; +use crate::pac::spi + +pub struct Spi<'d, T: Instance> { + peri: T, + irq: T::Interrupt, + phantom: PhantomData<&'d mut T>, +} + +pub enum Error { + +} + +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spim<'d, T> { + type Error = Error; + + fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> { + let mut recv: &mut [u8] = &mut []; + + } +} + +mod sealed { + use super::*; + use embassy::util::AtomicWaker; + + pub struct State { + pub end_waker: AtomicWaker, + } + + impl State { + pub const fn new() -> Self { + Self { + end_waker: AtomicWaker::new(), + } + } + } + + pub trait Instance { + fn regs() -> &'static crate::pac::spi::Spi; + fn state() -> &'static State; + } +} + +pub trait Instance: sealed::Instance + 'static { + type Interrupt: Interrupt; +} + +macro_rules! impl_spi { + ($inst:ident) => { + impl crate::spi::sealed::Instance for peripherals::$inst { + fn regs() -> crate::pac::spi::Spi { + crate::pac::$inst + } + } + + impl crate::spi::Instance for peripherals::$inst {} + }; +} \ No newline at end of file From 8a79e2cbbf3a2418690926e69c9d1ef3f3b36181 Mon Sep 17 00:00:00 2001 From: Bob McWhirter Date: Mon, 10 May 2021 16:17:58 -0400 Subject: [PATCH 2/8] Draft for partial review. Do not merge. --- embassy-stm32/src/spi.rs | 110 +++++++++++++++++++++++++++++++-------- 1 file changed, 89 insertions(+), 21 deletions(-) diff --git a/embassy-stm32/src/spi.rs b/embassy-stm32/src/spi.rs index b4b1d3d8..3eec7742 100644 --- a/embassy-stm32/src/spi.rs +++ b/embassy-stm32/src/spi.rs @@ -1,59 +1,127 @@ +#![macro_use] + pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; use core::marker::PhantomData; use embassy::interrupt::Interrupt; -use embedded_hal::blocking::spi::Write; -use crate::pac::spi +use embedded_hal::blocking::spi::{Write, Transfer}; +//use crate::pac::spi; pub struct Spi<'d, T: Instance> { peri: T, - irq: T::Interrupt, + //irq: T::Interrupt, phantom: PhantomData<&'d mut T>, } pub enum Error { - + Framing, + Crc, + Overrun, } -impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spim<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { type Error = Error; fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> { - let mut recv: &mut [u8] = &mut []; + let regs = T::regs(); + for word in words.iter() { + while unsafe { !regs.sr().read().txe() } { + // spin + } + unsafe { + regs.dr().write(|reg| reg.0 = *word as u32); + } + loop { + let sr = unsafe { regs.sr().read() }; + if sr.fre() { + return Err(Error::Framing); + } + if sr.ovr() { + return Err(Error::Overrun); + } + if sr.crcerr() { + return Err(Error::Crc); + } + if !sr.txe() { + // loop waiting for TXE + } + } + } + + Ok(()) } } -mod sealed { +impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { + type Error = Error; + + fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> { + let regs = T::regs(); + + for word in words.iter_mut() { + while unsafe { !regs.sr().read().txe() } { + // spin + } + unsafe { + regs.dr().write(|reg| reg.0 = *word as u32); + } + while unsafe { !regs.sr().read().rxne() } { + // spin waiting for inbound to shift in. + } + *word = unsafe { regs.dr().read().0 as u8 }; + loop { + let sr = unsafe { regs.sr().read() }; + if sr.fre() { + return Err(Error::Framing); + } + if sr.ovr() { + return Err(Error::Overrun); + } + if sr.crcerr() { + return Err(Error::Crc); + } + if !sr.txe() { + // loop waiting for TXE + } + } + } + + Ok(words) + } +} + + +pub(crate) mod sealed { use super::*; use embassy::util::AtomicWaker; - pub struct State { - pub end_waker: AtomicWaker, - } + //pub struct State { + //pub end_waker: AtomicWaker, + //} - impl State { - pub const fn new() -> Self { - Self { - end_waker: AtomicWaker::new(), - } - } - } + //impl State { + //pub const fn new() -> Self { + //Self { + //end_waker: AtomicWaker::new(), + //} + //} + //} pub trait Instance { fn regs() -> &'static crate::pac::spi::Spi; - fn state() -> &'static State; + //fn state() -> &'static State; } } pub trait Instance: sealed::Instance + 'static { - type Interrupt: Interrupt; + //type Interrupt: Interrupt; } macro_rules! impl_spi { ($inst:ident) => { impl crate::spi::sealed::Instance for peripherals::$inst { - fn regs() -> crate::pac::spi::Spi { - crate::pac::$inst + fn regs() -> &'static crate::pac::spi::Spi { + &crate::pac::$inst } } From 7d52e1b35048afca73fe3f0f4db2bca3edbe2e86 Mon Sep 17 00:00:00 2001 From: Bob McWhirter Date: Tue, 11 May 2021 11:25:01 -0400 Subject: [PATCH 3/8] Further work on SPI v2 blocking. --- embassy-stm32/gen.py | 8 + embassy-stm32/src/pac/regs.rs | 13826 ++++++++++++------------- embassy-stm32/src/pac/stm32f429zi.rs | 32 +- embassy-stm32/src/pac/stm32l431cb.rs | 27 + embassy-stm32/src/pac/stm32l431cc.rs | 27 + embassy-stm32/src/pac/stm32l431kb.rs | 18 + embassy-stm32/src/pac/stm32l431kc.rs | 18 + embassy-stm32/src/pac/stm32l431rb.rs | 27 + embassy-stm32/src/pac/stm32l431rc.rs | 27 + embassy-stm32/src/pac/stm32l431vc.rs | 27 + embassy-stm32/src/pac/stm32l432kb.rs | 15 + embassy-stm32/src/pac/stm32l432kc.rs | 15 + embassy-stm32/src/pac/stm32l433cb.rs | 27 + embassy-stm32/src/pac/stm32l433cc.rs | 27 + embassy-stm32/src/pac/stm32l433rb.rs | 27 + embassy-stm32/src/pac/stm32l433rc.rs | 27 + embassy-stm32/src/pac/stm32l433vc.rs | 27 + embassy-stm32/src/pac/stm32l442kc.rs | 15 + embassy-stm32/src/pac/stm32l443cc.rs | 27 + embassy-stm32/src/pac/stm32l443rc.rs | 27 + embassy-stm32/src/pac/stm32l443vc.rs | 27 + embassy-stm32/src/pac/stm32l496ae.rs | 39 + embassy-stm32/src/pac/stm32l496ag.rs | 39 + embassy-stm32/src/pac/stm32l496qe.rs | 39 + embassy-stm32/src/pac/stm32l496qg.rs | 39 + embassy-stm32/src/pac/stm32l496re.rs | 39 + embassy-stm32/src/pac/stm32l496rg.rs | 39 + embassy-stm32/src/pac/stm32l496ve.rs | 39 + embassy-stm32/src/pac/stm32l496vg.rs | 39 + embassy-stm32/src/pac/stm32l496wg.rs | 39 + embassy-stm32/src/pac/stm32l496ze.rs | 39 + embassy-stm32/src/pac/stm32l496zg.rs | 39 + embassy-stm32/src/pac/stm32l4a6ag.rs | 39 + embassy-stm32/src/pac/stm32l4a6qg.rs | 39 + embassy-stm32/src/pac/stm32l4a6rg.rs | 39 + embassy-stm32/src/pac/stm32l4a6vg.rs | 39 + embassy-stm32/src/pac/stm32l4a6zg.rs | 39 + embassy-stm32/src/pac/stm32l4p5ae.rs | 40 + embassy-stm32/src/pac/stm32l4p5ag.rs | 40 + embassy-stm32/src/pac/stm32l4p5ce.rs | 40 + embassy-stm32/src/pac/stm32l4p5cg.rs | 40 + embassy-stm32/src/pac/stm32l4p5qe.rs | 40 + embassy-stm32/src/pac/stm32l4p5qg.rs | 40 + embassy-stm32/src/pac/stm32l4p5re.rs | 40 + embassy-stm32/src/pac/stm32l4p5rg.rs | 40 + embassy-stm32/src/pac/stm32l4p5ve.rs | 40 + embassy-stm32/src/pac/stm32l4p5vg.rs | 40 + embassy-stm32/src/pac/stm32l4p5ze.rs | 40 + embassy-stm32/src/pac/stm32l4p5zg.rs | 40 + embassy-stm32/src/pac/stm32l4q5ag.rs | 40 + embassy-stm32/src/pac/stm32l4q5cg.rs | 40 + embassy-stm32/src/pac/stm32l4q5qg.rs | 40 + embassy-stm32/src/pac/stm32l4q5rg.rs | 40 + embassy-stm32/src/pac/stm32l4q5vg.rs | 40 + embassy-stm32/src/pac/stm32l4q5zg.rs | 40 + embassy-stm32/src/pac/stm32l4r5ag.rs | 40 + embassy-stm32/src/pac/stm32l4r5ai.rs | 40 + embassy-stm32/src/pac/stm32l4r5qg.rs | 40 + embassy-stm32/src/pac/stm32l4r5qi.rs | 40 + embassy-stm32/src/pac/stm32l4r5vg.rs | 40 + embassy-stm32/src/pac/stm32l4r5vi.rs | 40 + embassy-stm32/src/pac/stm32l4r5zg.rs | 40 + embassy-stm32/src/pac/stm32l4r5zi.rs | 40 + embassy-stm32/src/pac/stm32l4r7ai.rs | 40 + embassy-stm32/src/pac/stm32l4r7vi.rs | 40 + embassy-stm32/src/pac/stm32l4r7zi.rs | 40 + embassy-stm32/src/pac/stm32l4r9ag.rs | 40 + embassy-stm32/src/pac/stm32l4r9ai.rs | 40 + embassy-stm32/src/pac/stm32l4r9vg.rs | 40 + embassy-stm32/src/pac/stm32l4r9vi.rs | 40 + embassy-stm32/src/pac/stm32l4r9zg.rs | 40 + embassy-stm32/src/pac/stm32l4r9zi.rs | 40 + embassy-stm32/src/pac/stm32l4s5ai.rs | 40 + embassy-stm32/src/pac/stm32l4s5qi.rs | 40 + embassy-stm32/src/pac/stm32l4s5vi.rs | 40 + embassy-stm32/src/pac/stm32l4s5zi.rs | 40 + embassy-stm32/src/pac/stm32l4s7ai.rs | 40 + embassy-stm32/src/pac/stm32l4s7vi.rs | 40 + embassy-stm32/src/pac/stm32l4s7zi.rs | 40 + embassy-stm32/src/pac/stm32l4s9ai.rs | 40 + embassy-stm32/src/pac/stm32l4s9vi.rs | 40 + embassy-stm32/src/pac/stm32l4s9zi.rs | 40 + embassy-stm32/src/spi.rs | 86 + embassy-stm32/stm32-data | 2 +- 84 files changed, 9880 insertions(+), 6930 deletions(-) diff --git a/embassy-stm32/gen.py b/embassy-stm32/gen.py index c04de7d4..ec6b99b1 100644 --- a/embassy-stm32/gen.py +++ b/embassy-stm32/gen.py @@ -117,6 +117,14 @@ for chip in chips.values(): if block_mod == 'spi': f.write(f'impl_spi!({name});') + for pin, funcs in af.items(): + if pin in pins: + if func := funcs.get(f'{name}_SCK'): + f.write(f'impl_spi_pin!({name}, Sck, {pin}, {func});') + if func := funcs.get(f'{name}_MOSI'): + f.write(f'impl_spi_pin!({name}, Mosi, {pin}, {func});') + if func := funcs.get(f'{name}_MISO'): + f.write(f'impl_spi_pin!({name}, Miso, {pin}, {func});') if block_mod == 'gpio': custom_singletons = True diff --git a/embassy-stm32/src/pac/regs.rs b/embassy-stm32/src/pac/regs.rs index 38ce5981..9e4efa70 100644 --- a/embassy-stm32/src/pac/regs.rs +++ b/embassy-stm32/src/pac/regs.rs @@ -1,1145 +1,5 @@ #![no_std] #![doc = "Peripheral access API (generated using svd2rust v0.17.0 (22741fa 2021-04-20))"] -pub mod gpio_v1 { - use crate::generic::*; - #[doc = "General purpose I/O"] - #[derive(Copy, Clone)] - pub struct Gpio(pub *mut u8); - unsafe impl Send for Gpio {} - unsafe impl Sync for Gpio {} - impl Gpio { - #[doc = "Port configuration register low (GPIOn_CRL)"] - pub fn cr(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) } - } - #[doc = "Port input data register (GPIOn_IDR)"] - pub fn idr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "Port output data register (GPIOn_ODR)"] - pub fn odr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "Port bit set/reset register (GPIOn_BSRR)"] - pub fn bsrr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "Port bit reset register (GPIOn_BRR)"] - pub fn brr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "Port configuration lock register"] - pub fn lckr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "Port configuration register (GPIOn_CRx)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr(pub u32); - impl Cr { - #[doc = "Port n mode bits"] - pub fn mode(&self, n: usize) -> super::vals::Mode { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Mode(val as u8) - } - #[doc = "Port n mode bits"] - pub fn set_mode(&mut self, n: usize, val: super::vals::Mode) { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - #[doc = "Port n configuration bits"] - pub fn cnf(&self, n: usize) -> super::vals::Cnf { - assert!(n < 8usize); - let offs = 2usize + n * 4usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Cnf(val as u8) - } - #[doc = "Port n configuration bits"] - pub fn set_cnf(&mut self, n: usize, val: super::vals::Cnf) { - assert!(n < 8usize); - let offs = 2usize + n * 4usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - } - impl Default for Cr { - fn default() -> Cr { - Cr(0) - } - } - #[doc = "Port bit set/reset register (GPIOn_BSRR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Bsrr(pub u32); - impl Bsrr { - #[doc = "Set bit"] - pub fn bs(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Set bit"] - pub fn set_bs(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Reset bit"] - pub fn br(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 16usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Reset bit"] - pub fn set_br(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 16usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Bsrr { - fn default() -> Bsrr { - Bsrr(0) - } - } - #[doc = "Port input data register (GPIOn_IDR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idr(pub u32); - impl Idr { - #[doc = "Port input data"] - pub fn idr(&self, n: usize) -> super::vals::Idr { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Idr(val as u8) - } - #[doc = "Port input data"] - pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Idr { - fn default() -> Idr { - Idr(0) - } - } - #[doc = "Port bit reset register (GPIOn_BRR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Brr(pub u32); - impl Brr { - #[doc = "Reset bit"] - pub fn br(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Reset bit"] - pub fn set_br(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Brr { - fn default() -> Brr { - Brr(0) - } - } - #[doc = "Port output data register (GPIOn_ODR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Odr(pub u32); - impl Odr { - #[doc = "Port output data"] - pub fn odr(&self, n: usize) -> super::vals::Odr { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Odr(val as u8) - } - #[doc = "Port output data"] - pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Odr { - fn default() -> Odr { - Odr(0) - } - } - #[doc = "Port configuration lock register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Lckr(pub u32); - impl Lckr { - #[doc = "Port A Lock bit"] - pub fn lck(&self, n: usize) -> super::vals::Lck { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Lck(val as u8) - } - #[doc = "Port A Lock bit"] - pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - #[doc = "Lock key"] - pub const fn lckk(&self) -> super::vals::Lckk { - let val = (self.0 >> 16usize) & 0x01; - super::vals::Lckk(val as u8) - } - #[doc = "Lock key"] - pub fn set_lckk(&mut self, val: super::vals::Lckk) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); - } - } - impl Default for Lckr { - fn default() -> Lckr { - Lckr(0) - } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bsw(pub u8); - impl Bsw { - #[doc = "No action on the corresponding ODx bit"] - pub const NOACTION: Self = Self(0); - #[doc = "Sets the corresponding ODRx bit"] - pub const SET: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lckk(pub u8); - impl Lckk { - #[doc = "Port configuration lock key not active"] - pub const NOTACTIVE: Self = Self(0); - #[doc = "Port configuration lock key active"] - pub const ACTIVE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Odr(pub u8); - impl Odr { - #[doc = "Set output to logic low"] - pub const LOW: Self = Self(0); - #[doc = "Set output to logic high"] - pub const HIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Idr(pub u8); - impl Idr { - #[doc = "Input is logic low"] - pub const LOW: Self = Self(0); - #[doc = "Input is logic high"] - pub const HIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mode(pub u8); - impl Mode { - #[doc = "Input mode (reset state)"] - pub const INPUT: Self = Self(0); - #[doc = "Output mode 10 MHz"] - pub const OUTPUT: Self = Self(0x01); - #[doc = "Output mode 2 MHz"] - pub const OUTPUT2: Self = Self(0x02); - #[doc = "Output mode 50 MHz"] - pub const OUTPUT50: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lck(pub u8); - impl Lck { - #[doc = "Port configuration not locked"] - pub const UNLOCKED: Self = Self(0); - #[doc = "Port configuration locked"] - pub const LOCKED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cnf(pub u8); - impl Cnf { - #[doc = "Analog mode / Push-Pull mode"] - pub const PUSHPULL: Self = Self(0); - #[doc = "Floating input (reset state) / Open Drain-Mode"] - pub const OPENDRAIN: Self = Self(0x01); - #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"] - pub const ALTPUSHPULL: Self = Self(0x02); - #[doc = "Alternate Function Open-Drain Mode"] - pub const ALTOPENDRAIN: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Brw(pub u8); - impl Brw { - #[doc = "No action on the corresponding ODx bit"] - pub const NOACTION: Self = Self(0); - #[doc = "Reset the ODx bit"] - pub const RESET: Self = Self(0x01); - } - } -} -pub mod syscfg_f4 { - use crate::generic::*; - #[doc = "System configuration controller"] - #[derive(Copy, Clone)] - pub struct Syscfg(pub *mut u8); - unsafe impl Send for Syscfg {} - unsafe impl Sync for Syscfg {} - impl Syscfg { - #[doc = "memory remap register"] - pub fn memrm(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "peripheral mode configuration register"] - pub fn pmc(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "external interrupt configuration register"] - pub fn exticr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } - } - #[doc = "Compensation cell control register"] - pub fn cmpcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(32usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "memory remap register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Memrm(pub u32); - impl Memrm { - #[doc = "Memory mapping selection"] - pub const fn mem_mode(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Memory mapping selection"] - pub fn set_mem_mode(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Flash bank mode selection"] - pub const fn fb_mode(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Flash bank mode selection"] - pub fn set_fb_mode(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "FMC memory mapping swap"] - pub const fn swp_fmc(&self) -> u8 { - let val = (self.0 >> 10usize) & 0x03; - val as u8 - } - #[doc = "FMC memory mapping swap"] - pub fn set_swp_fmc(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize); - } - } - impl Default for Memrm { - fn default() -> Memrm { - Memrm(0) - } - } - #[doc = "Compensation cell control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cmpcr(pub u32); - impl Cmpcr { - #[doc = "Compensation cell power-down"] - pub const fn cmp_pd(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Compensation cell power-down"] - pub fn set_cmp_pd(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "READY"] - pub const fn ready(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "READY"] - pub fn set_ready(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for Cmpcr { - fn default() -> Cmpcr { - Cmpcr(0) - } - } - #[doc = "peripheral mode configuration register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pmc(pub u32); - impl Pmc { - #[doc = "ADC1DC2"] - pub const fn adc1dc2(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "ADC1DC2"] - pub fn set_adc1dc2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "ADC2DC2"] - pub const fn adc2dc2(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "ADC2DC2"] - pub fn set_adc2dc2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[doc = "ADC3DC2"] - pub const fn adc3dc2(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[doc = "ADC3DC2"] - pub fn set_adc3dc2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[doc = "Ethernet PHY interface selection"] - pub const fn mii_rmii_sel(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[doc = "Ethernet PHY interface selection"] - pub fn set_mii_rmii_sel(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - } - impl Default for Pmc { - fn default() -> Pmc { - Pmc(0) - } - } - #[doc = "external interrupt configuration register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Exticr(pub u32); - impl Exticr { - #[doc = "EXTI x configuration"] - pub fn exti(&self, n: usize) -> u8 { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x0f; - val as u8 - } - #[doc = "EXTI x configuration"] - pub fn set_exti(&mut self, n: usize, val: u8) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); - } - } - impl Default for Exticr { - fn default() -> Exticr { - Exticr(0) - } - } - } -} -pub mod exti_v1 { - use crate::generic::*; - #[doc = "External interrupt/event controller"] - #[derive(Copy, Clone)] - pub struct Exti(pub *mut u8); - unsafe impl Send for Exti {} - unsafe impl Sync for Exti {} - impl Exti { - #[doc = "Interrupt mask register (EXTI_IMR)"] - pub fn imr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "Event mask register (EXTI_EMR)"] - pub fn emr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "Rising Trigger selection register (EXTI_RTSR)"] - pub fn rtsr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "Falling Trigger selection register (EXTI_FTSR)"] - pub fn ftsr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "Software interrupt event register (EXTI_SWIER)"] - pub fn swier(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "Pending register (EXTI_PR)"] - pub fn pr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "Falling Trigger selection register (EXTI_FTSR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ftsr(pub u32); - impl Ftsr { - #[doc = "Falling trigger event configuration of line 0"] - pub fn tr(&self, n: usize) -> super::vals::Tr { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Tr(val as u8) - } - #[doc = "Falling trigger event configuration of line 0"] - pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Ftsr { - fn default() -> Ftsr { - Ftsr(0) - } - } - #[doc = "Event mask register (EXTI_EMR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Emr(pub u32); - impl Emr { - #[doc = "Event Mask on line 0"] - pub fn mr(&self, n: usize) -> super::vals::Mr { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Mr(val as u8) - } - #[doc = "Event Mask on line 0"] - pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Emr { - fn default() -> Emr { - Emr(0) - } - } - #[doc = "Software interrupt event register (EXTI_SWIER)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Swier(pub u32); - impl Swier { - #[doc = "Software Interrupt on line 0"] - pub fn swier(&self, n: usize) -> bool { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Software Interrupt on line 0"] - pub fn set_swier(&mut self, n: usize, val: bool) { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Swier { - fn default() -> Swier { - Swier(0) - } - } - #[doc = "Rising Trigger selection register (EXTI_RTSR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Rtsr(pub u32); - impl Rtsr { - #[doc = "Rising trigger event configuration of line 0"] - pub fn tr(&self, n: usize) -> super::vals::Tr { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Tr(val as u8) - } - #[doc = "Rising trigger event configuration of line 0"] - pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Rtsr { - fn default() -> Rtsr { - Rtsr(0) - } - } - #[doc = "Interrupt mask register (EXTI_IMR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Imr(pub u32); - impl Imr { - #[doc = "Interrupt Mask on line 0"] - pub fn mr(&self, n: usize) -> super::vals::Mr { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Mr(val as u8) - } - #[doc = "Interrupt Mask on line 0"] - pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Imr { - fn default() -> Imr { - Imr(0) - } - } - #[doc = "Pending register (EXTI_PR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pr(pub u32); - impl Pr { - #[doc = "Pending bit 0"] - pub fn pr(&self, n: usize) -> bool { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Pending bit 0"] - pub fn set_pr(&mut self, n: usize, val: bool) { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Pr { - fn default() -> Pr { - Pr(0) - } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mr(pub u8); - impl Mr { - #[doc = "Interrupt request line is masked"] - pub const MASKED: Self = Self(0); - #[doc = "Interrupt request line is unmasked"] - pub const UNMASKED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Prw(pub u8); - impl Prw { - #[doc = "Clears pending bit"] - pub const CLEAR: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Swierw(pub u8); - impl Swierw { - #[doc = "Generates an interrupt request"] - pub const PEND: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Tr(pub u8); - impl Tr { - #[doc = "Falling edge trigger is disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Falling edge trigger is enabled"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Prr(pub u8); - impl Prr { - #[doc = "No trigger request occurred"] - pub const NOTPENDING: Self = Self(0); - #[doc = "Selected trigger request occurred"] - pub const PENDING: Self = Self(0x01); - } - } -} -pub mod dma_v1 { - use crate::generic::*; - #[doc = "DMA controller"] - #[derive(Copy, Clone)] - pub struct Dma(pub *mut u8); - unsafe impl Send for Dma {} - unsafe impl Sync for Dma {} - impl Dma { - #[doc = "DMA interrupt status register (DMA_ISR)"] - pub fn isr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] - pub fn ifcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] - pub fn ch(self, n: usize) -> Ch { - assert!(n < 7usize); - unsafe { Ch(self.0.add(8usize + n * 20usize)) } - } - } - #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] - #[derive(Copy, Clone)] - pub struct Ch(pub *mut u8); - unsafe impl Send for Ch {} - unsafe impl Sync for Ch {} - impl Ch { - #[doc = "DMA channel configuration register (DMA_CCR)"] - pub fn cr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "DMA channel 1 number of data register"] - pub fn ndtr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "DMA channel 1 peripheral address register"] - pub fn par(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "DMA channel 1 memory address register"] - pub fn mar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pl(pub u8); - impl Pl { - #[doc = "Low priority"] - pub const LOW: Self = Self(0); - #[doc = "Medium priority"] - pub const MEDIUM: Self = Self(0x01); - #[doc = "High priority"] - pub const HIGH: Self = Self(0x02); - #[doc = "Very high priority"] - pub const VERYHIGH: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Circ(pub u8); - impl Circ { - #[doc = "Circular buffer disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Circular buffer enabled"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Inc(pub u8); - impl Inc { - #[doc = "Increment mode disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Increment mode enabled"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Size(pub u8); - impl Size { - #[doc = "8-bit size"] - pub const BITS8: Self = Self(0); - #[doc = "16-bit size"] - pub const BITS16: Self = Self(0x01); - #[doc = "32-bit size"] - pub const BITS32: Self = Self(0x02); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Memmem(pub u8); - impl Memmem { - #[doc = "Memory to memory mode disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Memory to memory mode enabled"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dir(pub u8); - impl Dir { - #[doc = "Read from peripheral"] - pub const FROMPERIPHERAL: Self = Self(0); - #[doc = "Read from memory"] - pub const FROMMEMORY: Self = Self(0x01); - } - } - pub mod regs { - use crate::generic::*; - #[doc = "DMA interrupt status register (DMA_ISR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Isr(pub u32); - impl Isr { - #[doc = "Channel 1 Global interrupt flag"] - pub fn gif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Global interrupt flag"] - pub fn set_gif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Transfer Complete flag"] - pub fn tcif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 1usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Transfer Complete flag"] - pub fn set_tcif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 1usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Half Transfer Complete flag"] - pub fn htif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 2usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Half Transfer Complete flag"] - pub fn set_htif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 2usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Transfer Error flag"] - pub fn teif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 3usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Transfer Error flag"] - pub fn set_teif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 3usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Isr { - fn default() -> Isr { - Isr(0) - } - } - #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ifcr(pub u32); - impl Ifcr { - #[doc = "Channel 1 Global interrupt clear"] - pub fn cgif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Global interrupt clear"] - pub fn set_cgif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Transfer Complete clear"] - pub fn ctcif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 1usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Transfer Complete clear"] - pub fn set_ctcif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 1usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Half Transfer clear"] - pub fn chtif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 2usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Half Transfer clear"] - pub fn set_chtif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 2usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Transfer Error clear"] - pub fn cteif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 3usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Transfer Error clear"] - pub fn set_cteif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 3usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Ifcr { - fn default() -> Ifcr { - Ifcr(0) - } - } - #[doc = "DMA channel 1 number of data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ndtr(pub u32); - impl Ndtr { - #[doc = "Number of data to transfer"] - pub const fn ndt(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Number of data to transfer"] - pub fn set_ndt(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Ndtr { - fn default() -> Ndtr { - Ndtr(0) - } - } - #[doc = "DMA channel configuration register (DMA_CCR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr(pub u32); - impl Cr { - #[doc = "Channel enable"] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Channel enable"] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Transfer complete interrupt enable"] - pub const fn tcie(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Transfer complete interrupt enable"] - pub fn set_tcie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Half Transfer interrupt enable"] - pub const fn htie(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Half Transfer interrupt enable"] - pub fn set_htie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Transfer error interrupt enable"] - pub const fn teie(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Transfer error interrupt enable"] - pub fn set_teie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Data transfer direction"] - pub const fn dir(&self) -> super::vals::Dir { - let val = (self.0 >> 4usize) & 0x01; - super::vals::Dir(val as u8) - } - #[doc = "Data transfer direction"] - pub fn set_dir(&mut self, val: super::vals::Dir) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); - } - #[doc = "Circular mode"] - pub const fn circ(&self) -> super::vals::Circ { - let val = (self.0 >> 5usize) & 0x01; - super::vals::Circ(val as u8) - } - #[doc = "Circular mode"] - pub fn set_circ(&mut self, val: super::vals::Circ) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); - } - #[doc = "Peripheral increment mode"] - pub const fn pinc(&self) -> super::vals::Inc { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Inc(val as u8) - } - #[doc = "Peripheral increment mode"] - pub fn set_pinc(&mut self, val: super::vals::Inc) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize); - } - #[doc = "Memory increment mode"] - pub const fn minc(&self) -> super::vals::Inc { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Inc(val as u8) - } - #[doc = "Memory increment mode"] - pub fn set_minc(&mut self, val: super::vals::Inc) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Peripheral size"] - pub const fn psize(&self) -> super::vals::Size { - let val = (self.0 >> 8usize) & 0x03; - super::vals::Size(val as u8) - } - #[doc = "Peripheral size"] - pub fn set_psize(&mut self, val: super::vals::Size) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); - } - #[doc = "Memory size"] - pub const fn msize(&self) -> super::vals::Size { - let val = (self.0 >> 10usize) & 0x03; - super::vals::Size(val as u8) - } - #[doc = "Memory size"] - pub fn set_msize(&mut self, val: super::vals::Size) { - self.0 = (self.0 & !(0x03 << 10usize)) | (((val.0 as u32) & 0x03) << 10usize); - } - #[doc = "Channel Priority level"] - pub const fn pl(&self) -> super::vals::Pl { - let val = (self.0 >> 12usize) & 0x03; - super::vals::Pl(val as u8) - } - #[doc = "Channel Priority level"] - pub fn set_pl(&mut self, val: super::vals::Pl) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); - } - #[doc = "Memory to memory mode"] - pub const fn mem2mem(&self) -> super::vals::Memmem { - let val = (self.0 >> 14usize) & 0x01; - super::vals::Memmem(val as u8) - } - #[doc = "Memory to memory mode"] - pub fn set_mem2mem(&mut self, val: super::vals::Memmem) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); - } - } - impl Default for Cr { - fn default() -> Cr { - Cr(0) - } - } - } -} -pub mod generic { - use core::marker::PhantomData; - #[derive(Copy, Clone)] - pub struct RW; - #[derive(Copy, Clone)] - pub struct R; - #[derive(Copy, Clone)] - pub struct W; - mod sealed { - use super::*; - pub trait Access {} - impl Access for R {} - impl Access for W {} - impl Access for RW {} - } - pub trait Access: sealed::Access + Copy {} - impl Access for R {} - impl Access for W {} - impl Access for RW {} - pub trait Read: Access {} - impl Read for RW {} - impl Read for R {} - pub trait Write: Access {} - impl Write for RW {} - impl Write for W {} - #[derive(Copy, Clone)] - pub struct Reg { - ptr: *mut u8, - phantom: PhantomData<*mut (T, A)>, - } - unsafe impl Send for Reg {} - unsafe impl Sync for Reg {} - impl Reg { - pub fn from_ptr(ptr: *mut u8) -> Self { - Self { - ptr, - phantom: PhantomData, - } - } - pub fn ptr(&self) -> *mut T { - self.ptr as _ - } - } - impl Reg { - pub unsafe fn read(&self) -> T { - (self.ptr as *mut T).read_volatile() - } - } - impl Reg { - pub unsafe fn write_value(&self, val: T) { - (self.ptr as *mut T).write_volatile(val) - } - } - impl Reg { - pub unsafe fn write(&self, f: impl FnOnce(&mut T) -> R) -> R { - let mut val = Default::default(); - let res = f(&mut val); - self.write_value(val); - res - } - } - impl Reg { - pub unsafe fn modify(&self, f: impl FnOnce(&mut T) -> R) -> R { - let mut val = self.read(); - let res = f(&mut val); - self.write_value(val); - res - } - } -} pub mod syscfg_l4 { use crate::generic::*; #[doc = "System configuration controller"] @@ -1180,6 +40,26 @@ pub mod syscfg_l4 { } pub mod regs { use crate::generic::*; + #[doc = "SKR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Skr(pub u32); + impl Skr { + #[doc = "SRAM2 write protection key for software erase"] + pub const fn key(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "SRAM2 write protection key for software erase"] + pub fn set_key(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + } + impl Default for Skr { + fn default() -> Skr { + Skr(0) + } + } #[doc = "external interrupt configuration register 4"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1204,6 +84,35 @@ pub mod syscfg_l4 { Exticr(0) } } + #[doc = "SCSR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Scsr(pub u32); + impl Scsr { + #[doc = "SRAM2 Erase"] + pub const fn sram2er(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 Erase"] + pub fn set_sram2er(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "SRAM2 busy by erase operation"] + pub const fn sram2bsy(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 busy by erase operation"] + pub fn set_sram2bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + } + impl Default for Scsr { + fn default() -> Scsr { + Scsr(0) + } + } #[doc = "SWPR"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1367,55 +276,6 @@ pub mod syscfg_l4 { Memrmp(0) } } - #[doc = "SCSR"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Scsr(pub u32); - impl Scsr { - #[doc = "SRAM2 Erase"] - pub const fn sram2er(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "SRAM2 Erase"] - pub fn set_sram2er(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "SRAM2 busy by erase operation"] - pub const fn sram2bsy(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "SRAM2 busy by erase operation"] - pub fn set_sram2bsy(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - } - impl Default for Scsr { - fn default() -> Scsr { - Scsr(0) - } - } - #[doc = "SKR"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Skr(pub u32); - impl Skr { - #[doc = "SRAM2 write protection key for software erase"] - pub const fn key(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "SRAM2 write protection key for software erase"] - pub fn set_key(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - } - impl Default for Skr { - fn default() -> Skr { - Skr(0) - } - } #[doc = "CFGR2"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1474,290 +334,316 @@ pub mod syscfg_l4 { } } } -pub mod gpio_v2 { +pub mod dma_v1 { use crate::generic::*; - #[doc = "General-purpose I/Os"] + #[doc = "DMA controller"] #[derive(Copy, Clone)] - pub struct Gpio(pub *mut u8); - unsafe impl Send for Gpio {} - unsafe impl Sync for Gpio {} - impl Gpio { - #[doc = "GPIO port mode register"] - pub fn moder(self) -> Reg { + pub struct Dma(pub *mut u8); + unsafe impl Send for Dma {} + unsafe impl Sync for Dma {} + impl Dma { + #[doc = "DMA interrupt status register (DMA_ISR)"] + pub fn isr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(0usize)) } } - #[doc = "GPIO port output type register"] - pub fn otyper(self) -> Reg { + #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] + pub fn ifcr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(4usize)) } } - #[doc = "GPIO port output speed register"] - pub fn ospeedr(self) -> Reg { + #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] + pub fn ch(self, n: usize) -> Ch { + assert!(n < 7usize); + unsafe { Ch(self.0.add(8usize + n * 20usize)) } + } + } + #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] + #[derive(Copy, Clone)] + pub struct Ch(pub *mut u8); + unsafe impl Send for Ch {} + unsafe impl Sync for Ch {} + impl Ch { + #[doc = "DMA channel configuration register (DMA_CCR)"] + pub fn cr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "DMA channel 1 number of data register"] + pub fn ndtr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "DMA channel 1 peripheral address register"] + pub fn par(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(8usize)) } } - #[doc = "GPIO port pull-up/pull-down register"] - pub fn pupdr(self) -> Reg { + #[doc = "DMA channel 1 memory address register"] + pub fn mar(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(12usize)) } } - #[doc = "GPIO port input data register"] - pub fn idr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "GPIO port output data register"] - pub fn odr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "GPIO port bit set/reset register"] - pub fn bsrr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } - } - #[doc = "GPIO port configuration lock register"] - pub fn lckr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(28usize)) } - } - #[doc = "GPIO alternate function register (low, high)"] - pub fn afr(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(32usize + n * 4usize)) } - } } pub mod regs { use crate::generic::*; - #[doc = "GPIO port output data register"] + #[doc = "DMA interrupt status register (DMA_ISR)"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Odr(pub u32); - impl Odr { - #[doc = "Port output data (y = 0..15)"] - pub fn odr(&self, n: usize) -> super::vals::Odr { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Odr(val as u8) - } - #[doc = "Port output data (y = 0..15)"] - pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Odr { - fn default() -> Odr { - Odr(0) - } - } - #[doc = "GPIO alternate function register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Afr(pub u32); - impl Afr { - #[doc = "Alternate function selection for port x bit y (y = 0..15)"] - pub fn afr(&self, n: usize) -> super::vals::Afr { - assert!(n < 8usize); + pub struct Isr(pub u32); + impl Isr { + #[doc = "Channel 1 Global interrupt flag"] + pub fn gif(&self, n: usize) -> bool { + assert!(n < 7usize); let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x0f; - super::vals::Afr(val as u8) - } - #[doc = "Alternate function selection for port x bit y (y = 0..15)"] - pub fn set_afr(&mut self, n: usize, val: super::vals::Afr) { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); - } - } - impl Default for Afr { - fn default() -> Afr { - Afr(0) - } - } - #[doc = "GPIO port bit set/reset register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Bsrr(pub u32); - impl Bsrr { - #[doc = "Port x set bit y (y= 0..15)"] - pub fn bs(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; let val = (self.0 >> offs) & 0x01; val != 0 } - #[doc = "Port x set bit y (y= 0..15)"] - pub fn set_bs(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; + #[doc = "Channel 1 Global interrupt flag"] + pub fn set_gif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } - #[doc = "Port x set bit y (y= 0..15)"] - pub fn br(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 16usize + n * 1usize; + #[doc = "Channel 1 Transfer Complete flag"] + pub fn tcif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; let val = (self.0 >> offs) & 0x01; val != 0 } - #[doc = "Port x set bit y (y= 0..15)"] - pub fn set_br(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 16usize + n * 1usize; + #[doc = "Channel 1 Transfer Complete flag"] + pub fn set_tcif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Half Transfer Complete flag"] + pub fn htif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Half Transfer Complete flag"] + pub fn set_htif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Error flag"] + pub fn teif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Error flag"] + pub fn set_teif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } } - impl Default for Bsrr { - fn default() -> Bsrr { - Bsrr(0) + impl Default for Isr { + fn default() -> Isr { + Isr(0) } } - #[doc = "GPIO port output speed register"] + #[doc = "DMA channel 1 number of data register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ospeedr(pub u32); - impl Ospeedr { - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Ospeedr(val as u8) + pub struct Ndtr(pub u32); + impl Ndtr { + #[doc = "Number of data to transfer"] + pub const fn ndt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 } - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + #[doc = "Number of data to transfer"] + pub fn set_ndt(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); } } - impl Default for Ospeedr { - fn default() -> Ospeedr { - Ospeedr(0) + impl Default for Ndtr { + fn default() -> Ndtr { + Ndtr(0) } } - #[doc = "GPIO port configuration lock register"] + #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Lckr(pub u32); - impl Lckr { - #[doc = "Port x lock bit y (y= 0..15)"] - pub fn lck(&self, n: usize) -> super::vals::Lck { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; + pub struct Ifcr(pub u32); + impl Ifcr { + #[doc = "Channel 1 Global interrupt clear"] + pub fn cgif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; let val = (self.0 >> offs) & 0x01; - super::vals::Lck(val as u8) + val != 0 } - #[doc = "Port x lock bit y (y= 0..15)"] - pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + #[doc = "Channel 1 Global interrupt clear"] + pub fn set_cgif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } - #[doc = "Port x lock bit y (y= 0..15)"] - pub const fn lckk(&self) -> super::vals::Lckk { - let val = (self.0 >> 16usize) & 0x01; - super::vals::Lckk(val as u8) - } - #[doc = "Port x lock bit y (y= 0..15)"] - pub fn set_lckk(&mut self, val: super::vals::Lckk) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); - } - } - impl Default for Lckr { - fn default() -> Lckr { - Lckr(0) - } - } - #[doc = "GPIO port input data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idr(pub u32); - impl Idr { - #[doc = "Port input data (y = 0..15)"] - pub fn idr(&self, n: usize) -> super::vals::Idr { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; + #[doc = "Channel 1 Transfer Complete clear"] + pub fn ctcif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; let val = (self.0 >> offs) & 0x01; - super::vals::Idr(val as u8) + val != 0 } - #[doc = "Port input data (y = 0..15)"] - pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + #[doc = "Channel 1 Transfer Complete clear"] + pub fn set_ctcif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } - } - impl Default for Idr { - fn default() -> Idr { - Idr(0) - } - } - #[doc = "GPIO port mode register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Moder(pub u32); - impl Moder { - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn moder(&self, n: usize) -> super::vals::Moder { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Moder(val as u8) - } - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - } - impl Default for Moder { - fn default() -> Moder { - Moder(0) - } - } - #[doc = "GPIO port pull-up/pull-down register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pupdr(pub u32); - impl Pupdr { - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn pupdr(&self, n: usize) -> super::vals::Pupdr { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Pupdr(val as u8) - } - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn set_pupdr(&mut self, n: usize, val: super::vals::Pupdr) { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - } - impl Default for Pupdr { - fn default() -> Pupdr { - Pupdr(0) - } - } - #[doc = "GPIO port output type register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Otyper(pub u32); - impl Otyper { - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn ot(&self, n: usize) -> super::vals::Ot { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; + #[doc = "Channel 1 Half Transfer clear"] + pub fn chtif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; let val = (self.0 >> offs) & 0x01; - super::vals::Ot(val as u8) + val != 0 } - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn set_ot(&mut self, n: usize, val: super::vals::Ot) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + #[doc = "Channel 1 Half Transfer clear"] + pub fn set_chtif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Error clear"] + pub fn cteif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Error clear"] + pub fn set_cteif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } } - impl Default for Otyper { - fn default() -> Otyper { - Otyper(0) + impl Default for Ifcr { + fn default() -> Ifcr { + Ifcr(0) + } + } + #[doc = "DMA channel configuration register (DMA_CCR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Channel enable"] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Channel enable"] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Transfer complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Transfer complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Half Transfer interrupt enable"] + pub const fn htie(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Half Transfer interrupt enable"] + pub fn set_htie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Transfer error interrupt enable"] + pub const fn teie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Transfer error interrupt enable"] + pub fn set_teie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Data transfer direction"] + pub const fn dir(&self) -> super::vals::Dir { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Dir(val as u8) + } + #[doc = "Data transfer direction"] + pub fn set_dir(&mut self, val: super::vals::Dir) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Circular mode"] + pub const fn circ(&self) -> super::vals::Circ { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Circ(val as u8) + } + #[doc = "Circular mode"] + pub fn set_circ(&mut self, val: super::vals::Circ) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "Peripheral increment mode"] + pub const fn pinc(&self) -> super::vals::Inc { + let val = (self.0 >> 6usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Peripheral increment mode"] + pub fn set_pinc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize); + } + #[doc = "Memory increment mode"] + pub const fn minc(&self) -> super::vals::Inc { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Memory increment mode"] + pub fn set_minc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Peripheral size"] + pub const fn psize(&self) -> super::vals::Size { + let val = (self.0 >> 8usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Peripheral size"] + pub fn set_psize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); + } + #[doc = "Memory size"] + pub const fn msize(&self) -> super::vals::Size { + let val = (self.0 >> 10usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Memory size"] + pub fn set_msize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 10usize)) | (((val.0 as u32) & 0x03) << 10usize); + } + #[doc = "Channel Priority level"] + pub const fn pl(&self) -> super::vals::Pl { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Pl(val as u8) + } + #[doc = "Channel Priority level"] + pub fn set_pl(&mut self, val: super::vals::Pl) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "Memory to memory mode"] + pub const fn mem2mem(&self) -> super::vals::Memmem { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Memmem(val as u8) + } + #[doc = "Memory to memory mode"] + pub fn set_mem2mem(&mut self, val: super::vals::Memmem) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) } } } @@ -1765,136 +651,133 @@ pub mod gpio_v2 { use crate::generic::*; #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pupdr(pub u8); - impl Pupdr { - #[doc = "No pull-up, pull-down"] - pub const FLOATING: Self = Self(0); - #[doc = "Pull-up"] - pub const PULLUP: Self = Self(0x01); - #[doc = "Pull-down"] - pub const PULLDOWN: Self = Self(0x02); + pub struct Circ(pub u8); + impl Circ { + #[doc = "Circular buffer disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Circular buffer enabled"] + pub const ENABLED: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ot(pub u8); - impl Ot { - #[doc = "Output push-pull (reset state)"] - pub const PUSHPULL: Self = Self(0); - #[doc = "Output open-drain"] - pub const OPENDRAIN: Self = Self(0x01); + pub struct Memmem(pub u8); + impl Memmem { + #[doc = "Memory to memory mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Memory to memory mode enabled"] + pub const ENABLED: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Afr(pub u8); - impl Afr { - #[doc = "AF0"] - pub const AF0: Self = Self(0); - #[doc = "AF1"] - pub const AF1: Self = Self(0x01); - #[doc = "AF2"] - pub const AF2: Self = Self(0x02); - #[doc = "AF3"] - pub const AF3: Self = Self(0x03); - #[doc = "AF4"] - pub const AF4: Self = Self(0x04); - #[doc = "AF5"] - pub const AF5: Self = Self(0x05); - #[doc = "AF6"] - pub const AF6: Self = Self(0x06); - #[doc = "AF7"] - pub const AF7: Self = Self(0x07); - #[doc = "AF8"] - pub const AF8: Self = Self(0x08); - #[doc = "AF9"] - pub const AF9: Self = Self(0x09); - #[doc = "AF10"] - pub const AF10: Self = Self(0x0a); - #[doc = "AF11"] - pub const AF11: Self = Self(0x0b); - #[doc = "AF12"] - pub const AF12: Self = Self(0x0c); - #[doc = "AF13"] - pub const AF13: Self = Self(0x0d); - #[doc = "AF14"] - pub const AF14: Self = Self(0x0e); - #[doc = "AF15"] - pub const AF15: Self = Self(0x0f); + pub struct Dir(pub u8); + impl Dir { + #[doc = "Read from peripheral"] + pub const FROMPERIPHERAL: Self = Self(0); + #[doc = "Read from memory"] + pub const FROMMEMORY: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Brw(pub u8); - impl Brw { - #[doc = "Resets the corresponding ODRx bit"] - pub const RESET: Self = Self(0x01); + pub struct Size(pub u8); + impl Size { + #[doc = "8-bit size"] + pub const BITS8: Self = Self(0); + #[doc = "16-bit size"] + pub const BITS16: Self = Self(0x01); + #[doc = "32-bit size"] + pub const BITS32: Self = Self(0x02); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lck(pub u8); - impl Lck { - #[doc = "Port configuration not locked"] - pub const UNLOCKED: Self = Self(0); - #[doc = "Port configuration locked"] - pub const LOCKED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Moder(pub u8); - impl Moder { - #[doc = "Input mode (reset state)"] - pub const INPUT: Self = Self(0); - #[doc = "General purpose output mode"] - pub const OUTPUT: Self = Self(0x01); - #[doc = "Alternate function mode"] - pub const ALTERNATE: Self = Self(0x02); - #[doc = "Analog mode"] - pub const ANALOG: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Idr(pub u8); - impl Idr { - #[doc = "Input is logic low"] + pub struct Pl(pub u8); + impl Pl { + #[doc = "Low priority"] pub const LOW: Self = Self(0); - #[doc = "Input is logic high"] - pub const HIGH: Self = Self(0x01); + #[doc = "Medium priority"] + pub const MEDIUM: Self = Self(0x01); + #[doc = "High priority"] + pub const HIGH: Self = Self(0x02); + #[doc = "Very high priority"] + pub const VERYHIGH: Self = Self(0x03); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ospeedr(pub u8); - impl Ospeedr { - #[doc = "Low speed"] - pub const LOWSPEED: Self = Self(0); - #[doc = "Medium speed"] - pub const MEDIUMSPEED: Self = Self(0x01); - #[doc = "High speed"] - pub const HIGHSPEED: Self = Self(0x02); - #[doc = "Very high speed"] - pub const VERYHIGHSPEED: Self = Self(0x03); + pub struct Inc(pub u8); + impl Inc { + #[doc = "Increment mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Increment mode enabled"] + pub const ENABLED: Self = Self(0x01); } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bsw(pub u8); - impl Bsw { - #[doc = "Sets the corresponding ODRx bit"] - pub const SET: Self = Self(0x01); + } +} +pub mod generic { + use core::marker::PhantomData; + #[derive(Copy, Clone)] + pub struct RW; + #[derive(Copy, Clone)] + pub struct R; + #[derive(Copy, Clone)] + pub struct W; + mod sealed { + use super::*; + pub trait Access {} + impl Access for R {} + impl Access for W {} + impl Access for RW {} + } + pub trait Access: sealed::Access + Copy {} + impl Access for R {} + impl Access for W {} + impl Access for RW {} + pub trait Read: Access {} + impl Read for RW {} + impl Read for R {} + pub trait Write: Access {} + impl Write for RW {} + impl Write for W {} + #[derive(Copy, Clone)] + pub struct Reg { + ptr: *mut u8, + phantom: PhantomData<*mut (T, A)>, + } + unsafe impl Send for Reg {} + unsafe impl Sync for Reg {} + impl Reg { + pub fn from_ptr(ptr: *mut u8) -> Self { + Self { + ptr, + phantom: PhantomData, + } } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lckk(pub u8); - impl Lckk { - #[doc = "Port configuration lock key not active"] - pub const NOTACTIVE: Self = Self(0); - #[doc = "Port configuration lock key active"] - pub const ACTIVE: Self = Self(0x01); + pub fn ptr(&self) -> *mut T { + self.ptr as _ } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Odr(pub u8); - impl Odr { - #[doc = "Set output to logic low"] - pub const LOW: Self = Self(0); - #[doc = "Set output to logic high"] - pub const HIGH: Self = Self(0x01); + } + impl Reg { + pub unsafe fn read(&self) -> T { + (self.ptr as *mut T).read_volatile() + } + } + impl Reg { + pub unsafe fn write_value(&self, val: T) { + (self.ptr as *mut T).write_volatile(val) + } + } + impl Reg { + pub unsafe fn write(&self, f: impl FnOnce(&mut T) -> R) -> R { + let mut val = Default::default(); + let res = f(&mut val); + self.write_value(val); + res + } + } + impl Reg { + pub unsafe fn modify(&self, f: impl FnOnce(&mut T) -> R) -> R { + let mut val = self.read(); + let res = f(&mut val); + self.write_value(val); + res } } } @@ -1939,73 +822,6 @@ pub mod spi_v1 { use crate::generic::*; #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bidimode(pub u8); - impl Bidimode { - #[doc = "2-line unidirectional data mode selected"] - pub const UNIDIRECTIONAL: Self = Self(0); - #[doc = "1-line bidirectional data mode selected"] - pub const BIDIRECTIONAL: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Iscfg(pub u8); - impl Iscfg { - #[doc = "Slave - transmit"] - pub const SLAVETX: Self = Self(0); - #[doc = "Slave - receive"] - pub const SLAVERX: Self = Self(0x01); - #[doc = "Master - transmit"] - pub const MASTERTX: Self = Self(0x02); - #[doc = "Master - receive"] - pub const MASTERRX: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dff(pub u8); - impl Dff { - #[doc = "8-bit data frame format is selected for transmission/reception"] - pub const EIGHTBIT: Self = Self(0); - #[doc = "16-bit data frame format is selected for transmission/reception"] - pub const SIXTEENBIT: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bidioe(pub u8); - impl Bidioe { - #[doc = "Output disabled (receive-only mode)"] - pub const OUTPUTDISABLED: Self = Self(0); - #[doc = "Output enabled (transmit-only mode)"] - pub const OUTPUTENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Rxonly(pub u8); - impl Rxonly { - #[doc = "Full duplex (Transmit and receive)"] - pub const FULLDUPLEX: Self = Self(0); - #[doc = "Output disabled (Receive-only mode)"] - pub const OUTPUTDISABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpha(pub u8); - impl Cpha { - #[doc = "The first clock transition is the first data capture edge"] - pub const FIRSTEDGE: Self = Self(0); - #[doc = "The second clock transition is the first data capture edge"] - pub const SECONDEDGE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frer(pub u8); - impl Frer { - #[doc = "No frame format error"] - pub const NOERROR: Self = Self(0); - #[doc = "A frame format error occurred"] - pub const ERROR: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Crcnext(pub u8); impl Crcnext { #[doc = "Next transmit value is from Tx buffer"] @@ -2015,24 +831,6 @@ pub mod spi_v1 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frf(pub u8); - impl Frf { - #[doc = "SPI Motorola mode"] - pub const MOTOROLA: Self = Self(0); - #[doc = "SPI TI mode"] - pub const TI: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lsbfirst(pub u8); - impl Lsbfirst { - #[doc = "Data is transmitted/received with the MSB first"] - pub const MSBFIRST: Self = Self(0); - #[doc = "Data is transmitted/received with the LSB first"] - pub const LSBFIRST: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Br(pub u8); impl Br { #[doc = "f_PCLK / 2"] @@ -2070,9 +868,302 @@ pub mod spi_v1 { #[doc = "Master configuration"] pub const MASTER: Self = Self(0x01); } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dff(pub u8); + impl Dff { + #[doc = "8-bit data frame format is selected for transmission/reception"] + pub const EIGHTBIT: Self = Self(0); + #[doc = "16-bit data frame format is selected for transmission/reception"] + pub const SIXTEENBIT: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRSTEDGE: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECONDEDGE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frer(pub u8); + impl Frer { + #[doc = "No frame format error"] + pub const NOERROR: Self = Self(0); + #[doc = "A frame format error occurred"] + pub const ERROR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidioe(pub u8); + impl Bidioe { + #[doc = "Output disabled (receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0); + #[doc = "Output enabled (transmit-only mode)"] + pub const OUTPUTENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rxonly(pub u8); + impl Rxonly { + #[doc = "Full duplex (Transmit and receive)"] + pub const FULLDUPLEX: Self = Self(0); + #[doc = "Output disabled (Receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Iscfg(pub u8); + impl Iscfg { + #[doc = "Slave - transmit"] + pub const SLAVETX: Self = Self(0); + #[doc = "Slave - receive"] + pub const SLAVERX: Self = Self(0x01); + #[doc = "Master - transmit"] + pub const MASTERTX: Self = Self(0x02); + #[doc = "Master - receive"] + pub const MASTERRX: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lsbfirst(pub u8); + impl Lsbfirst { + #[doc = "Data is transmitted/received with the MSB first"] + pub const MSBFIRST: Self = Self(0); + #[doc = "Data is transmitted/received with the LSB first"] + pub const LSBFIRST: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frf(pub u8); + impl Frf { + #[doc = "SPI Motorola mode"] + pub const MOTOROLA: Self = Self(0); + #[doc = "SPI TI mode"] + pub const TI: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidimode(pub u8); + impl Bidimode { + #[doc = "2-line unidirectional data mode selected"] + pub const UNIDIRECTIONAL: Self = Self(0); + #[doc = "1-line bidirectional data mode selected"] + pub const BIDIRECTIONAL: Self = Self(0x01); + } } pub mod regs { use crate::generic::*; + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Receive buffer not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Receive buffer not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Transmit buffer empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Transmit buffer empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "CRC error flag"] + pub const fn crcerr(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "CRC error flag"] + pub fn set_crcerr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Mode fault"] + pub const fn modf(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Mode fault"] + pub fn set_modf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Overrun flag"] + pub const fn ovr(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Overrun flag"] + pub fn set_ovr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Busy flag"] + pub const fn bsy(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Busy flag"] + pub fn set_bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "TI frame format error"] + pub const fn fre(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "TI frame format error"] + pub fn set_fre(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + #[doc = "TX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Txcrcr(pub u32); + impl Txcrcr { + #[doc = "Tx CRC register"] + pub const fn tx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Tx CRC register"] + pub fn set_tx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Txcrcr { + fn default() -> Txcrcr { + Txcrcr(0) + } + } + #[doc = "RX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rxcrcr(pub u32); + impl Rxcrcr { + #[doc = "Rx CRC register"] + pub const fn rx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Rx CRC register"] + pub fn set_rx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Rxcrcr { + fn default() -> Rxcrcr { + Rxcrcr(0) + } + } + #[doc = "CRC polynomial register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Crcpr(pub u32); + impl Crcpr { + #[doc = "CRC polynomial register"] + pub const fn crcpoly(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "CRC polynomial register"] + pub fn set_crcpoly(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Crcpr { + fn default() -> Crcpr { + Crcpr(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2(pub u32); + impl Cr2 { + #[doc = "Rx buffer DMA enable"] + pub const fn rxdmaen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Rx buffer DMA enable"] + pub fn set_rxdmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Tx buffer DMA enable"] + pub const fn txdmaen(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Tx buffer DMA enable"] + pub fn set_txdmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "SS output enable"] + pub const fn ssoe(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "SS output enable"] + pub fn set_ssoe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Frame format"] + pub const fn frf(&self) -> super::vals::Frf { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Frf(val as u8) + } + #[doc = "Frame format"] + pub fn set_frf(&mut self, val: super::vals::Frf) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Error interrupt enable"] + pub const fn errie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_errie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "RX buffer not empty interrupt enable"] + pub const fn rxneie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "RX buffer not empty interrupt enable"] + pub fn set_rxneie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Tx buffer empty interrupt enable"] + pub const fn txeie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Tx buffer empty interrupt enable"] + pub fn set_txeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for Cr2 { + fn default() -> Cr2 { + Cr2(0) + } + } #[doc = "control register 1"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -2230,212 +1321,3551 @@ pub mod spi_v1 { Dr(0) } } - #[doc = "CRC polynomial register"] + } +} +pub mod exti_v1 { + use crate::generic::*; + #[doc = "External interrupt/event controller"] + #[derive(Copy, Clone)] + pub struct Exti(pub *mut u8); + unsafe impl Send for Exti {} + unsafe impl Sync for Exti {} + impl Exti { + #[doc = "Interrupt mask register (EXTI_IMR)"] + pub fn imr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Event mask register (EXTI_EMR)"] + pub fn emr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Rising Trigger selection register (EXTI_RTSR)"] + pub fn rtsr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Falling Trigger selection register (EXTI_FTSR)"] + pub fn ftsr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Software interrupt event register (EXTI_SWIER)"] + pub fn swier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Pending register (EXTI_PR)"] + pub fn pr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Prr(pub u8); + impl Prr { + #[doc = "No trigger request occurred"] + pub const NOTPENDING: Self = Self(0); + #[doc = "Selected trigger request occurred"] + pub const PENDING: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Prw(pub u8); + impl Prw { + #[doc = "Clears pending bit"] + pub const CLEAR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Swierw(pub u8); + impl Swierw { + #[doc = "Generates an interrupt request"] + pub const PEND: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mr(pub u8); + impl Mr { + #[doc = "Interrupt request line is masked"] + pub const MASKED: Self = Self(0); + #[doc = "Interrupt request line is unmasked"] + pub const UNMASKED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Tr(pub u8); + impl Tr { + #[doc = "Falling edge trigger is disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Falling edge trigger is enabled"] + pub const ENABLED: Self = Self(0x01); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "Rising Trigger selection register (EXTI_RTSR)"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Crcpr(pub u32); - impl Crcpr { - #[doc = "CRC polynomial register"] - pub const fn crcpoly(&self) -> u16 { + pub struct Rtsr(pub u32); + impl Rtsr { + #[doc = "Rising trigger event configuration of line 0"] + pub fn tr(&self, n: usize) -> super::vals::Tr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Tr(val as u8) + } + #[doc = "Rising trigger event configuration of line 0"] + pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Rtsr { + fn default() -> Rtsr { + Rtsr(0) + } + } + #[doc = "Falling Trigger selection register (EXTI_FTSR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ftsr(pub u32); + impl Ftsr { + #[doc = "Falling trigger event configuration of line 0"] + pub fn tr(&self, n: usize) -> super::vals::Tr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Tr(val as u8) + } + #[doc = "Falling trigger event configuration of line 0"] + pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Ftsr { + fn default() -> Ftsr { + Ftsr(0) + } + } + #[doc = "Interrupt mask register (EXTI_IMR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Imr(pub u32); + impl Imr { + #[doc = "Interrupt Mask on line 0"] + pub fn mr(&self, n: usize) -> super::vals::Mr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Mr(val as u8) + } + #[doc = "Interrupt Mask on line 0"] + pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Imr { + fn default() -> Imr { + Imr(0) + } + } + #[doc = "Pending register (EXTI_PR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pr(pub u32); + impl Pr { + #[doc = "Pending bit 0"] + pub fn pr(&self, n: usize) -> bool { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Pending bit 0"] + pub fn set_pr(&mut self, n: usize, val: bool) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Pr { + fn default() -> Pr { + Pr(0) + } + } + #[doc = "Software interrupt event register (EXTI_SWIER)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Swier(pub u32); + impl Swier { + #[doc = "Software Interrupt on line 0"] + pub fn swier(&self, n: usize) -> bool { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Software Interrupt on line 0"] + pub fn set_swier(&mut self, n: usize, val: bool) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Swier { + fn default() -> Swier { + Swier(0) + } + } + #[doc = "Event mask register (EXTI_EMR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Emr(pub u32); + impl Emr { + #[doc = "Event Mask on line 0"] + pub fn mr(&self, n: usize) -> super::vals::Mr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Mr(val as u8) + } + #[doc = "Event Mask on line 0"] + pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Emr { + fn default() -> Emr { + Emr(0) + } + } + } +} +pub mod gpio_v2 { + use crate::generic::*; + #[doc = "General-purpose I/Os"] + #[derive(Copy, Clone)] + pub struct Gpio(pub *mut u8); + unsafe impl Send for Gpio {} + unsafe impl Sync for Gpio {} + impl Gpio { + #[doc = "GPIO port mode register"] + pub fn moder(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "GPIO port output type register"] + pub fn otyper(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "GPIO port output speed register"] + pub fn ospeedr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "GPIO port pull-up/pull-down register"] + pub fn pupdr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "GPIO port input data register"] + pub fn idr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "GPIO port output data register"] + pub fn odr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "GPIO port bit set/reset register"] + pub fn bsrr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + #[doc = "GPIO port configuration lock register"] + pub fn lckr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(28usize)) } + } + #[doc = "GPIO alternate function register (low, high)"] + pub fn afr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(32usize + n * 4usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "GPIO port pull-up/pull-down register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pupdr(pub u32); + impl Pupdr { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn pupdr(&self, n: usize) -> super::vals::Pupdr { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Pupdr(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_pupdr(&mut self, n: usize, val: super::vals::Pupdr) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Pupdr { + fn default() -> Pupdr { + Pupdr(0) + } + } + #[doc = "GPIO port input data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idr(pub u32); + impl Idr { + #[doc = "Port input data (y = 0..15)"] + pub fn idr(&self, n: usize) -> super::vals::Idr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Idr(val as u8) + } + #[doc = "Port input data (y = 0..15)"] + pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Idr { + fn default() -> Idr { + Idr(0) + } + } + #[doc = "GPIO port bit set/reset register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Bsrr(pub u32); + impl Bsrr { + #[doc = "Port x set bit y (y= 0..15)"] + pub fn bs(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Port x set bit y (y= 0..15)"] + pub fn set_bs(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Port x set bit y (y= 0..15)"] + pub fn br(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Port x set bit y (y= 0..15)"] + pub fn set_br(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Bsrr { + fn default() -> Bsrr { + Bsrr(0) + } + } + #[doc = "GPIO port output type register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Otyper(pub u32); + impl Otyper { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn ot(&self, n: usize) -> super::vals::Ot { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Ot(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_ot(&mut self, n: usize, val: super::vals::Ot) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Otyper { + fn default() -> Otyper { + Otyper(0) + } + } + #[doc = "GPIO port output speed register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ospeedr(pub u32); + impl Ospeedr { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Ospeedr(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Ospeedr { + fn default() -> Ospeedr { + Ospeedr(0) + } + } + #[doc = "GPIO port output data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Odr(pub u32); + impl Odr { + #[doc = "Port output data (y = 0..15)"] + pub fn odr(&self, n: usize) -> super::vals::Odr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Odr(val as u8) + } + #[doc = "Port output data (y = 0..15)"] + pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Odr { + fn default() -> Odr { + Odr(0) + } + } + #[doc = "GPIO alternate function register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Afr(pub u32); + impl Afr { + #[doc = "Alternate function selection for port x bit y (y = 0..15)"] + pub fn afr(&self, n: usize) -> super::vals::Afr { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + super::vals::Afr(val as u8) + } + #[doc = "Alternate function selection for port x bit y (y = 0..15)"] + pub fn set_afr(&mut self, n: usize, val: super::vals::Afr) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); + } + } + impl Default for Afr { + fn default() -> Afr { + Afr(0) + } + } + #[doc = "GPIO port configuration lock register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Lckr(pub u32); + impl Lckr { + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn lck(&self, n: usize) -> super::vals::Lck { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Lck(val as u8) + } + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Port x lock bit y (y= 0..15)"] + pub const fn lckk(&self) -> super::vals::Lckk { + let val = (self.0 >> 16usize) & 0x01; + super::vals::Lckk(val as u8) + } + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn set_lckk(&mut self, val: super::vals::Lckk) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); + } + } + impl Default for Lckr { + fn default() -> Lckr { + Lckr(0) + } + } + #[doc = "GPIO port mode register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Moder(pub u32); + impl Moder { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn moder(&self, n: usize) -> super::vals::Moder { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Moder(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Moder { + fn default() -> Moder { + Moder(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Brw(pub u8); + impl Brw { + #[doc = "Resets the corresponding ODRx bit"] + pub const RESET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Moder(pub u8); + impl Moder { + #[doc = "Input mode (reset state)"] + pub const INPUT: Self = Self(0); + #[doc = "General purpose output mode"] + pub const OUTPUT: Self = Self(0x01); + #[doc = "Alternate function mode"] + pub const ALTERNATE: Self = Self(0x02); + #[doc = "Analog mode"] + pub const ANALOG: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pupdr(pub u8); + impl Pupdr { + #[doc = "No pull-up, pull-down"] + pub const FLOATING: Self = Self(0); + #[doc = "Pull-up"] + pub const PULLUP: Self = Self(0x01); + #[doc = "Pull-down"] + pub const PULLDOWN: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lckk(pub u8); + impl Lckk { + #[doc = "Port configuration lock key not active"] + pub const NOTACTIVE: Self = Self(0); + #[doc = "Port configuration lock key active"] + pub const ACTIVE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ot(pub u8); + impl Ot { + #[doc = "Output push-pull (reset state)"] + pub const PUSHPULL: Self = Self(0); + #[doc = "Output open-drain"] + pub const OPENDRAIN: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ospeedr(pub u8); + impl Ospeedr { + #[doc = "Low speed"] + pub const LOWSPEED: Self = Self(0); + #[doc = "Medium speed"] + pub const MEDIUMSPEED: Self = Self(0x01); + #[doc = "High speed"] + pub const HIGHSPEED: Self = Self(0x02); + #[doc = "Very high speed"] + pub const VERYHIGHSPEED: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Afr(pub u8); + impl Afr { + #[doc = "AF0"] + pub const AF0: Self = Self(0); + #[doc = "AF1"] + pub const AF1: Self = Self(0x01); + #[doc = "AF2"] + pub const AF2: Self = Self(0x02); + #[doc = "AF3"] + pub const AF3: Self = Self(0x03); + #[doc = "AF4"] + pub const AF4: Self = Self(0x04); + #[doc = "AF5"] + pub const AF5: Self = Self(0x05); + #[doc = "AF6"] + pub const AF6: Self = Self(0x06); + #[doc = "AF7"] + pub const AF7: Self = Self(0x07); + #[doc = "AF8"] + pub const AF8: Self = Self(0x08); + #[doc = "AF9"] + pub const AF9: Self = Self(0x09); + #[doc = "AF10"] + pub const AF10: Self = Self(0x0a); + #[doc = "AF11"] + pub const AF11: Self = Self(0x0b); + #[doc = "AF12"] + pub const AF12: Self = Self(0x0c); + #[doc = "AF13"] + pub const AF13: Self = Self(0x0d); + #[doc = "AF14"] + pub const AF14: Self = Self(0x0e); + #[doc = "AF15"] + pub const AF15: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Idr(pub u8); + impl Idr { + #[doc = "Input is logic low"] + pub const LOW: Self = Self(0); + #[doc = "Input is logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lck(pub u8); + impl Lck { + #[doc = "Port configuration not locked"] + pub const UNLOCKED: Self = Self(0); + #[doc = "Port configuration locked"] + pub const LOCKED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Odr(pub u8); + impl Odr { + #[doc = "Set output to logic low"] + pub const LOW: Self = Self(0); + #[doc = "Set output to logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bsw(pub u8); + impl Bsw { + #[doc = "Sets the corresponding ODRx bit"] + pub const SET: Self = Self(0x01); + } + } +} +pub mod dma_v2 { + use crate::generic::*; + #[doc = "DMA controller"] + #[derive(Copy, Clone)] + pub struct Dma(pub *mut u8); + unsafe impl Send for Dma {} + unsafe impl Sync for Dma {} + impl Dma { + #[doc = "low interrupt status register"] + pub fn isr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) } + } + #[doc = "low interrupt flag clear register"] + pub fn ifcr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } + } + #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"] + pub fn st(self, n: usize) -> St { + assert!(n < 8usize); + unsafe { St(self.0.add(16usize + n * 24usize)) } + } + } + #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"] + #[derive(Copy, Clone)] + pub struct St(pub *mut u8); + unsafe impl Send for St {} + unsafe impl Sync for St {} + impl St { + #[doc = "stream x configuration register"] + pub fn cr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "stream x number of data register"] + pub fn ndtr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "stream x peripheral address register"] + pub fn par(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "stream x memory 0 address register"] + pub fn m0ar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "stream x memory 1 address register"] + pub fn m1ar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "stream x FIFO control register"] + pub fn fcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Fth(pub u8); + impl Fth { + #[doc = "1/4 full FIFO"] + pub const QUARTER: Self = Self(0); + #[doc = "1/2 full FIFO"] + pub const HALF: Self = Self(0x01); + #[doc = "3/4 full FIFO"] + pub const THREEQUARTERS: Self = Self(0x02); + #[doc = "Full FIFO"] + pub const FULL: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pincos(pub u8); + impl Pincos { + #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] + pub const PSIZE: Self = Self(0); + #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] + pub const FIXED4: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Size(pub u8); + impl Size { + #[doc = "Byte (8-bit)"] + pub const BITS8: Self = Self(0); + #[doc = "Half-word (16-bit)"] + pub const BITS16: Self = Self(0x01); + #[doc = "Word (32-bit)"] + pub const BITS32: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dbm(pub u8); + impl Dbm { + #[doc = "No buffer switching at the end of transfer"] + pub const DISABLED: Self = Self(0); + #[doc = "Memory target switched at the end of the DMA transfer"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pl(pub u8); + impl Pl { + #[doc = "Low"] + pub const LOW: Self = Self(0); + #[doc = "Medium"] + pub const MEDIUM: Self = Self(0x01); + #[doc = "High"] + pub const HIGH: Self = Self(0x02); + #[doc = "Very high"] + pub const VERYHIGH: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dmdis(pub u8); + impl Dmdis { + #[doc = "Direct mode is enabled"] + pub const ENABLED: Self = Self(0); + #[doc = "Direct mode is disabled"] + pub const DISABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Burst(pub u8); + impl Burst { + #[doc = "Single transfer"] + pub const SINGLE: Self = Self(0); + #[doc = "Incremental burst of 4 beats"] + pub const INCR4: Self = Self(0x01); + #[doc = "Incremental burst of 8 beats"] + pub const INCR8: Self = Self(0x02); + #[doc = "Incremental burst of 16 beats"] + pub const INCR16: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Peripheral-to-memory"] + pub const PERIPHERALTOMEMORY: Self = Self(0); + #[doc = "Memory-to-peripheral"] + pub const MEMORYTOPERIPHERAL: Self = Self(0x01); + #[doc = "Memory-to-memory"] + pub const MEMORYTOMEMORY: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Circ(pub u8); + impl Circ { + #[doc = "Circular mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Circular mode enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ct(pub u8); + impl Ct { + #[doc = "The current target memory is Memory 0"] + pub const MEMORY0: Self = Self(0); + #[doc = "The current target memory is Memory 1"] + pub const MEMORY1: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Inc(pub u8); + impl Inc { + #[doc = "Address pointer is fixed"] + pub const FIXED: Self = Self(0); + #[doc = "Address pointer is incremented after each data transfer"] + pub const INCREMENTED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Fs(pub u8); + impl Fs { + #[doc = "0 < fifo_level < 1/4"] + pub const QUARTER1: Self = Self(0); + #[doc = "1/4 <= fifo_level < 1/2"] + pub const QUARTER2: Self = Self(0x01); + #[doc = "1/2 <= fifo_level < 3/4"] + pub const QUARTER3: Self = Self(0x02); + #[doc = "3/4 <= fifo_level < full"] + pub const QUARTER4: Self = Self(0x03); + #[doc = "FIFO is empty"] + pub const EMPTY: Self = Self(0x04); + #[doc = "FIFO is full"] + pub const FULL: Self = Self(0x05); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pfctrl(pub u8); + impl Pfctrl { + #[doc = "The DMA is the flow controller"] + pub const DMA: Self = Self(0); + #[doc = "The peripheral is the flow controller"] + pub const PERIPHERAL: Self = Self(0x01); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "stream x number of data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ndtr(pub u32); + impl Ndtr { + #[doc = "Number of data items to transfer"] + pub const fn ndt(&self) -> u16 { let val = (self.0 >> 0usize) & 0xffff; val as u16 } - #[doc = "CRC polynomial register"] - pub fn set_crcpoly(&mut self, val: u16) { + #[doc = "Number of data items to transfer"] + pub fn set_ndt(&mut self, val: u16) { self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); } } - impl Default for Crcpr { - fn default() -> Crcpr { - Crcpr(0) + impl Default for Ndtr { + fn default() -> Ndtr { + Ndtr(0) } } - #[doc = "RX CRC register"] + #[doc = "low interrupt flag clear register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Rxcrcr(pub u32); - impl Rxcrcr { - #[doc = "Rx CRC register"] - pub const fn rx_crc(&self) -> u16 { + pub struct Ifcr(pub u32); + impl Ifcr { + #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"] + pub fn cfeif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"] + pub fn set_cfeif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"] + pub fn cdmeif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"] + pub fn set_cdmeif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"] + pub fn cteif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"] + pub fn set_cteif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"] + pub fn chtif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"] + pub fn set_chtif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"] + pub fn ctcif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"] + pub fn set_ctcif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Ifcr { + fn default() -> Ifcr { + Ifcr(0) + } + } + #[doc = "stream x FIFO control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Fcr(pub u32); + impl Fcr { + #[doc = "FIFO threshold selection"] + pub const fn fth(&self) -> super::vals::Fth { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Fth(val as u8) + } + #[doc = "FIFO threshold selection"] + pub fn set_fth(&mut self, val: super::vals::Fth) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize); + } + #[doc = "Direct mode disable"] + pub const fn dmdis(&self) -> super::vals::Dmdis { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Dmdis(val as u8) + } + #[doc = "Direct mode disable"] + pub fn set_dmdis(&mut self, val: super::vals::Dmdis) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "FIFO status"] + pub const fn fs(&self) -> super::vals::Fs { + let val = (self.0 >> 3usize) & 0x07; + super::vals::Fs(val as u8) + } + #[doc = "FIFO status"] + pub fn set_fs(&mut self, val: super::vals::Fs) { + self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); + } + #[doc = "FIFO error interrupt enable"] + pub const fn feie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "FIFO error interrupt enable"] + pub fn set_feie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for Fcr { + fn default() -> Fcr { + Fcr(0) + } + } + #[doc = "low interrupt status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Isr(pub u32); + impl Isr { + #[doc = "Stream x FIFO error interrupt flag (x=3..0)"] + pub fn feif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x FIFO error interrupt flag (x=3..0)"] + pub fn set_feif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x direct mode error interrupt flag (x=3..0)"] + pub fn dmeif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x direct mode error interrupt flag (x=3..0)"] + pub fn set_dmeif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x transfer error interrupt flag (x=3..0)"] + pub fn teif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x transfer error interrupt flag (x=3..0)"] + pub fn set_teif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x half transfer interrupt flag (x=3..0)"] + pub fn htif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x half transfer interrupt flag (x=3..0)"] + pub fn set_htif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"] + pub fn tcif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"] + pub fn set_tcif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Isr { + fn default() -> Isr { + Isr(0) + } + } + #[doc = "stream x configuration register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Stream enable / flag stream ready when read low"] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Stream enable / flag stream ready when read low"] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Direct mode error interrupt enable"] + pub const fn dmeie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Direct mode error interrupt enable"] + pub fn set_dmeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Transfer error interrupt enable"] + pub const fn teie(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Transfer error interrupt enable"] + pub fn set_teie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Half transfer interrupt enable"] + pub const fn htie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Half transfer interrupt enable"] + pub fn set_htie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Transfer complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Transfer complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Peripheral flow controller"] + pub const fn pfctrl(&self) -> super::vals::Pfctrl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Pfctrl(val as u8) + } + #[doc = "Peripheral flow controller"] + pub fn set_pfctrl(&mut self, val: super::vals::Pfctrl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "Data transfer direction"] + pub const fn dir(&self) -> super::vals::Dir { + let val = (self.0 >> 6usize) & 0x03; + super::vals::Dir(val as u8) + } + #[doc = "Data transfer direction"] + pub fn set_dir(&mut self, val: super::vals::Dir) { + self.0 = (self.0 & !(0x03 << 6usize)) | (((val.0 as u32) & 0x03) << 6usize); + } + #[doc = "Circular mode"] + pub const fn circ(&self) -> super::vals::Circ { + let val = (self.0 >> 8usize) & 0x01; + super::vals::Circ(val as u8) + } + #[doc = "Circular mode"] + pub fn set_circ(&mut self, val: super::vals::Circ) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize); + } + #[doc = "Peripheral increment mode"] + pub const fn pinc(&self) -> super::vals::Inc { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Peripheral increment mode"] + pub fn set_pinc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Memory increment mode"] + pub const fn minc(&self) -> super::vals::Inc { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Memory increment mode"] + pub fn set_minc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Peripheral data size"] + pub const fn psize(&self) -> super::vals::Size { + let val = (self.0 >> 11usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Peripheral data size"] + pub fn set_psize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 11usize)) | (((val.0 as u32) & 0x03) << 11usize); + } + #[doc = "Memory data size"] + pub const fn msize(&self) -> super::vals::Size { + let val = (self.0 >> 13usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Memory data size"] + pub fn set_msize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 13usize)) | (((val.0 as u32) & 0x03) << 13usize); + } + #[doc = "Peripheral increment offset size"] + pub const fn pincos(&self) -> super::vals::Pincos { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Pincos(val as u8) + } + #[doc = "Peripheral increment offset size"] + pub fn set_pincos(&mut self, val: super::vals::Pincos) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + #[doc = "Priority level"] + pub const fn pl(&self) -> super::vals::Pl { + let val = (self.0 >> 16usize) & 0x03; + super::vals::Pl(val as u8) + } + #[doc = "Priority level"] + pub fn set_pl(&mut self, val: super::vals::Pl) { + self.0 = (self.0 & !(0x03 << 16usize)) | (((val.0 as u32) & 0x03) << 16usize); + } + #[doc = "Double buffer mode"] + pub const fn dbm(&self) -> super::vals::Dbm { + let val = (self.0 >> 18usize) & 0x01; + super::vals::Dbm(val as u8) + } + #[doc = "Double buffer mode"] + pub fn set_dbm(&mut self, val: super::vals::Dbm) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize); + } + #[doc = "Current target (only in double buffer mode)"] + pub const fn ct(&self) -> super::vals::Ct { + let val = (self.0 >> 19usize) & 0x01; + super::vals::Ct(val as u8) + } + #[doc = "Current target (only in double buffer mode)"] + pub fn set_ct(&mut self, val: super::vals::Ct) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize); + } + #[doc = "Peripheral burst transfer configuration"] + pub const fn pburst(&self) -> super::vals::Burst { + let val = (self.0 >> 21usize) & 0x03; + super::vals::Burst(val as u8) + } + #[doc = "Peripheral burst transfer configuration"] + pub fn set_pburst(&mut self, val: super::vals::Burst) { + self.0 = (self.0 & !(0x03 << 21usize)) | (((val.0 as u32) & 0x03) << 21usize); + } + #[doc = "Memory burst transfer configuration"] + pub const fn mburst(&self) -> super::vals::Burst { + let val = (self.0 >> 23usize) & 0x03; + super::vals::Burst(val as u8) + } + #[doc = "Memory burst transfer configuration"] + pub fn set_mburst(&mut self, val: super::vals::Burst) { + self.0 = (self.0 & !(0x03 << 23usize)) | (((val.0 as u32) & 0x03) << 23usize); + } + #[doc = "Channel selection"] + pub const fn chsel(&self) -> u8 { + let val = (self.0 >> 25usize) & 0x0f; + val as u8 + } + #[doc = "Channel selection"] + pub fn set_chsel(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 25usize)) | (((val as u32) & 0x0f) << 25usize); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + } +} +pub mod gpio_v1 { + use crate::generic::*; + #[doc = "General purpose I/O"] + #[derive(Copy, Clone)] + pub struct Gpio(pub *mut u8); + unsafe impl Send for Gpio {} + unsafe impl Sync for Gpio {} + impl Gpio { + #[doc = "Port configuration register low (GPIOn_CRL)"] + pub fn cr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) } + } + #[doc = "Port input data register (GPIOn_IDR)"] + pub fn idr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Port output data register (GPIOn_ODR)"] + pub fn odr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Port bit set/reset register (GPIOn_BSRR)"] + pub fn bsrr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Port bit reset register (GPIOn_BRR)"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "Port configuration lock register"] + pub fn lckr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Brw(pub u8); + impl Brw { + #[doc = "No action on the corresponding ODx bit"] + pub const NOACTION: Self = Self(0); + #[doc = "Reset the ODx bit"] + pub const RESET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bsw(pub u8); + impl Bsw { + #[doc = "No action on the corresponding ODx bit"] + pub const NOACTION: Self = Self(0); + #[doc = "Sets the corresponding ODRx bit"] + pub const SET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mode(pub u8); + impl Mode { + #[doc = "Input mode (reset state)"] + pub const INPUT: Self = Self(0); + #[doc = "Output mode 10 MHz"] + pub const OUTPUT: Self = Self(0x01); + #[doc = "Output mode 2 MHz"] + pub const OUTPUT2: Self = Self(0x02); + #[doc = "Output mode 50 MHz"] + pub const OUTPUT50: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cnf(pub u8); + impl Cnf { + #[doc = "Analog mode / Push-Pull mode"] + pub const PUSHPULL: Self = Self(0); + #[doc = "Floating input (reset state) / Open Drain-Mode"] + pub const OPENDRAIN: Self = Self(0x01); + #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"] + pub const ALTPUSHPULL: Self = Self(0x02); + #[doc = "Alternate Function Open-Drain Mode"] + pub const ALTOPENDRAIN: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lckk(pub u8); + impl Lckk { + #[doc = "Port configuration lock key not active"] + pub const NOTACTIVE: Self = Self(0); + #[doc = "Port configuration lock key active"] + pub const ACTIVE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Odr(pub u8); + impl Odr { + #[doc = "Set output to logic low"] + pub const LOW: Self = Self(0); + #[doc = "Set output to logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Idr(pub u8); + impl Idr { + #[doc = "Input is logic low"] + pub const LOW: Self = Self(0); + #[doc = "Input is logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lck(pub u8); + impl Lck { + #[doc = "Port configuration not locked"] + pub const UNLOCKED: Self = Self(0); + #[doc = "Port configuration locked"] + pub const LOCKED: Self = Self(0x01); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "Port input data register (GPIOn_IDR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idr(pub u32); + impl Idr { + #[doc = "Port input data"] + pub fn idr(&self, n: usize) -> super::vals::Idr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Idr(val as u8) + } + #[doc = "Port input data"] + pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Idr { + fn default() -> Idr { + Idr(0) + } + } + #[doc = "Port bit reset register (GPIOn_BRR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Brr(pub u32); + impl Brr { + #[doc = "Reset bit"] + pub fn br(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Reset bit"] + pub fn set_br(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Brr { + fn default() -> Brr { + Brr(0) + } + } + #[doc = "Port bit set/reset register (GPIOn_BSRR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Bsrr(pub u32); + impl Bsrr { + #[doc = "Set bit"] + pub fn bs(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Set bit"] + pub fn set_bs(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Reset bit"] + pub fn br(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Reset bit"] + pub fn set_br(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Bsrr { + fn default() -> Bsrr { + Bsrr(0) + } + } + #[doc = "Port configuration register (GPIOn_CRx)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Port n mode bits"] + pub fn mode(&self, n: usize) -> super::vals::Mode { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Mode(val as u8) + } + #[doc = "Port n mode bits"] + pub fn set_mode(&mut self, n: usize, val: super::vals::Mode) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Port n configuration bits"] + pub fn cnf(&self, n: usize) -> super::vals::Cnf { + assert!(n < 8usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Cnf(val as u8) + } + #[doc = "Port n configuration bits"] + pub fn set_cnf(&mut self, n: usize, val: super::vals::Cnf) { + assert!(n < 8usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + #[doc = "Port configuration lock register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Lckr(pub u32); + impl Lckr { + #[doc = "Port A Lock bit"] + pub fn lck(&self, n: usize) -> super::vals::Lck { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Lck(val as u8) + } + #[doc = "Port A Lock bit"] + pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Lock key"] + pub const fn lckk(&self) -> super::vals::Lckk { + let val = (self.0 >> 16usize) & 0x01; + super::vals::Lckk(val as u8) + } + #[doc = "Lock key"] + pub fn set_lckk(&mut self, val: super::vals::Lckk) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); + } + } + impl Default for Lckr { + fn default() -> Lckr { + Lckr(0) + } + } + #[doc = "Port output data register (GPIOn_ODR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Odr(pub u32); + impl Odr { + #[doc = "Port output data"] + pub fn odr(&self, n: usize) -> super::vals::Odr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Odr(val as u8) + } + #[doc = "Port output data"] + pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Odr { + fn default() -> Odr { + Odr(0) + } + } + } +} +pub mod timer_v1 { + use crate::generic::*; + #[doc = "General purpose 16-bit timer"] + #[derive(Copy, Clone)] + pub struct TimGp16(pub *mut u8); + unsafe impl Send for TimGp16 {} + unsafe impl Sync for TimGp16 {} + impl TimGp16 { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "slave mode control register"] + pub fn smcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "capture/compare mode register 1 (input mode)"] + pub fn ccmr_input(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare mode register 1 (output mode)"] + pub fn ccmr_output(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare enable register"] + pub fn ccer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "capture/compare register"] + pub fn ccr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } + } + #[doc = "DMA control register"] + pub fn dcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(72usize)) } + } + #[doc = "DMA address for full transfer"] + pub fn dmar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(76usize)) } + } + } + #[doc = "General purpose 32-bit timer"] + #[derive(Copy, Clone)] + pub struct TimGp32(pub *mut u8); + unsafe impl Send for TimGp32 {} + unsafe impl Sync for TimGp32 {} + impl TimGp32 { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "slave mode control register"] + pub fn smcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "capture/compare mode register 1 (input mode)"] + pub fn ccmr_input(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare mode register 1 (output mode)"] + pub fn ccmr_output(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare enable register"] + pub fn ccer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "capture/compare register"] + pub fn ccr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } + } + #[doc = "DMA control register"] + pub fn dcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(72usize)) } + } + #[doc = "DMA address for full transfer"] + pub fn dmar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(76usize)) } + } + } + #[doc = "Advanced-timers"] + #[derive(Copy, Clone)] + pub struct TimAdv(pub *mut u8); + unsafe impl Send for TimAdv {} + unsafe impl Sync for TimAdv {} + impl TimAdv { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "slave mode control register"] + pub fn smcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "capture/compare mode register 1 (input mode)"] + pub fn ccmr_input(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare mode register 1 (output mode)"] + pub fn ccmr_output(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare enable register"] + pub fn ccer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "repetition counter register"] + pub fn rcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(48usize)) } + } + #[doc = "capture/compare register"] + pub fn ccr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } + } + #[doc = "break and dead-time register"] + pub fn bdtr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(68usize)) } + } + #[doc = "DMA control register"] + pub fn dcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(72usize)) } + } + #[doc = "DMA address for full transfer"] + pub fn dmar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(76usize)) } + } + } + #[doc = "Basic timer"] + #[derive(Copy, Clone)] + pub struct TimBasic(pub *mut u8); + unsafe impl Send for TimBasic {} + unsafe impl Sync for TimBasic {} + impl TimBasic { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ts(pub u8); + impl Ts { + #[doc = "Internal Trigger 0 (ITR0)"] + pub const ITR0: Self = Self(0); + #[doc = "Internal Trigger 1 (ITR1)"] + pub const ITR1: Self = Self(0x01); + #[doc = "Internal Trigger 2 (ITR2)"] + pub const ITR2: Self = Self(0x02); + #[doc = "TI1 Edge Detector (TI1F_ED)"] + pub const TI1F_ED: Self = Self(0x04); + #[doc = "Filtered Timer Input 1 (TI1FP1)"] + pub const TI1FP1: Self = Self(0x05); + #[doc = "Filtered Timer Input 2 (TI2FP2)"] + pub const TI2FP2: Self = Self(0x06); + #[doc = "External Trigger input (ETRF)"] + pub const ETRF: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Sms(pub u8); + impl Sms { + #[doc = "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] + pub const DISABLED: Self = Self(0); + #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."] + pub const ENCODER_MODE_1: Self = Self(0x01); + #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."] + pub const ENCODER_MODE_2: Self = Self(0x02); + #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."] + pub const ENCODER_MODE_3: Self = Self(0x03); + #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."] + pub const RESET_MODE: Self = Self(0x04); + #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."] + pub const GATED_MODE: Self = Self(0x05); + #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."] + pub const TRIGGER_MODE: Self = Self(0x06); + #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."] + pub const EXT_CLOCK_MODE: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Icf(pub u8); + impl Icf { + #[doc = "No filter, sampling is done at fDTS"] + pub const NOFILTER: Self = Self(0); + #[doc = "fSAMPLING=fCK_INT, N=2"] + pub const FCK_INT_N2: Self = Self(0x01); + #[doc = "fSAMPLING=fCK_INT, N=4"] + pub const FCK_INT_N4: Self = Self(0x02); + #[doc = "fSAMPLING=fCK_INT, N=8"] + pub const FCK_INT_N8: Self = Self(0x03); + #[doc = "fSAMPLING=fDTS/2, N=6"] + pub const FDTS_DIV2_N6: Self = Self(0x04); + #[doc = "fSAMPLING=fDTS/2, N=8"] + pub const FDTS_DIV2_N8: Self = Self(0x05); + #[doc = "fSAMPLING=fDTS/4, N=6"] + pub const FDTS_DIV4_N6: Self = Self(0x06); + #[doc = "fSAMPLING=fDTS/4, N=8"] + pub const FDTS_DIV4_N8: Self = Self(0x07); + #[doc = "fSAMPLING=fDTS/8, N=6"] + pub const FDTS_DIV8_N6: Self = Self(0x08); + #[doc = "fSAMPLING=fDTS/8, N=8"] + pub const FDTS_DIV8_N8: Self = Self(0x09); + #[doc = "fSAMPLING=fDTS/16, N=5"] + pub const FDTS_DIV16_N5: Self = Self(0x0a); + #[doc = "fSAMPLING=fDTS/16, N=6"] + pub const FDTS_DIV16_N6: Self = Self(0x0b); + #[doc = "fSAMPLING=fDTS/16, N=8"] + pub const FDTS_DIV16_N8: Self = Self(0x0c); + #[doc = "fSAMPLING=fDTS/32, N=5"] + pub const FDTS_DIV32_N5: Self = Self(0x0d); + #[doc = "fSAMPLING=fDTS/32, N=6"] + pub const FDTS_DIV32_N6: Self = Self(0x0e); + #[doc = "fSAMPLING=fDTS/32, N=8"] + pub const FDTS_DIV32_N8: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Opm(pub u8); + impl Opm { + #[doc = "Counter is not stopped at update event"] + pub const DISABLED: Self = Self(0); + #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ocm(pub u8); + impl Ocm { + #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] + pub const FROZEN: Self = Self(0); + #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] + pub const ACTIVEONMATCH: Self = Self(0x01); + #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] + pub const INACTIVEONMATCH: Self = Self(0x02); + #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] + pub const TOGGLE: Self = Self(0x03); + #[doc = "OCyREF is forced low"] + pub const FORCEINACTIVE: Self = Self(0x04); + #[doc = "OCyREF is forced high"] + pub const FORCEACTIVE: Self = Self(0x05); + #[doc = "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active"] + pub const PWMMODE1: Self = Self(0x06); + #[doc = "Inversely to PwmMode1"] + pub const PWMMODE2: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ossi(pub u8); + impl Ossi { + #[doc = "When inactive, OC/OCN outputs are disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "When inactive, OC/OCN outputs are forced to idle level"] + pub const IDLELEVEL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Counter used as upcounter"] + pub const UP: Self = Self(0); + #[doc = "Counter used as downcounter"] + pub const DOWN: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ossr(pub u8); + impl Ossr { + #[doc = "When inactive, OC/OCN outputs are disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"] + pub const IDLELEVEL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Msm(pub u8); + impl Msm { + #[doc = "No action"] + pub const NOSYNC: Self = Self(0); + #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."] + pub const SYNC: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Arpe(pub u8); + impl Arpe { + #[doc = "TIMx_APRR register is not buffered"] + pub const DISABLED: Self = Self(0); + #[doc = "TIMx_APRR register is buffered"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct CcmrOutputCcs(pub u8); + impl CcmrOutputCcs { + #[doc = "CCx channel is configured as output"] + pub const OUTPUT: Self = Self(0); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ccds(pub u8); + impl Ccds { + #[doc = "CCx DMA request sent when CCx event occurs"] + pub const ONCOMPARE: Self = Self(0); + #[doc = "CCx DMA request sent when update event occurs"] + pub const ONUPDATE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Tis(pub u8); + impl Tis { + #[doc = "The TIMx_CH1 pin is connected to TI1 input"] + pub const NORMAL: Self = Self(0); + #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"] + pub const XOR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct CcmrInputCcs(pub u8); + impl CcmrInputCcs { + #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"] + pub const TI4: Self = Self(0x01); + #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"] + pub const TI3: Self = Self(0x02); + #[doc = "CCx channel is configured as input, ICx is mapped on TRC"] + pub const TRC: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etf(pub u8); + impl Etf { + #[doc = "No filter, sampling is done at fDTS"] + pub const NOFILTER: Self = Self(0); + #[doc = "fSAMPLING=fCK_INT, N=2"] + pub const FCK_INT_N2: Self = Self(0x01); + #[doc = "fSAMPLING=fCK_INT, N=4"] + pub const FCK_INT_N4: Self = Self(0x02); + #[doc = "fSAMPLING=fCK_INT, N=8"] + pub const FCK_INT_N8: Self = Self(0x03); + #[doc = "fSAMPLING=fDTS/2, N=6"] + pub const FDTS_DIV2_N6: Self = Self(0x04); + #[doc = "fSAMPLING=fDTS/2, N=8"] + pub const FDTS_DIV2_N8: Self = Self(0x05); + #[doc = "fSAMPLING=fDTS/4, N=6"] + pub const FDTS_DIV4_N6: Self = Self(0x06); + #[doc = "fSAMPLING=fDTS/4, N=8"] + pub const FDTS_DIV4_N8: Self = Self(0x07); + #[doc = "fSAMPLING=fDTS/8, N=6"] + pub const FDTS_DIV8_N6: Self = Self(0x08); + #[doc = "fSAMPLING=fDTS/8, N=8"] + pub const FDTS_DIV8_N8: Self = Self(0x09); + #[doc = "fSAMPLING=fDTS/16, N=5"] + pub const FDTS_DIV16_N5: Self = Self(0x0a); + #[doc = "fSAMPLING=fDTS/16, N=6"] + pub const FDTS_DIV16_N6: Self = Self(0x0b); + #[doc = "fSAMPLING=fDTS/16, N=8"] + pub const FDTS_DIV16_N8: Self = Self(0x0c); + #[doc = "fSAMPLING=fDTS/32, N=5"] + pub const FDTS_DIV32_N5: Self = Self(0x0d); + #[doc = "fSAMPLING=fDTS/32, N=6"] + pub const FDTS_DIV32_N6: Self = Self(0x0e); + #[doc = "fSAMPLING=fDTS/32, N=8"] + pub const FDTS_DIV32_N8: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cms(pub u8); + impl Cms { + #[doc = "The counter counts up or down depending on the direction bit"] + pub const EDGEALIGNED: Self = Self(0); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] + pub const CENTERALIGNED1: Self = Self(0x01); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] + pub const CENTERALIGNED2: Self = Self(0x02); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] + pub const CENTERALIGNED3: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ckd(pub u8); + impl Ckd { + #[doc = "t_DTS = t_CK_INT"] + pub const DIV1: Self = Self(0); + #[doc = "t_DTS = 2 × t_CK_INT"] + pub const DIV2: Self = Self(0x01); + #[doc = "t_DTS = 4 × t_CK_INT"] + pub const DIV4: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etp(pub u8); + impl Etp { + #[doc = "ETR is noninverted, active at high level or rising edge"] + pub const NOTINVERTED: Self = Self(0); + #[doc = "ETR is inverted, active at low level or falling edge"] + pub const INVERTED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etps(pub u8); + impl Etps { + #[doc = "Prescaler OFF"] + pub const DIV1: Self = Self(0); + #[doc = "ETRP frequency divided by 2"] + pub const DIV2: Self = Self(0x01); + #[doc = "ETRP frequency divided by 4"] + pub const DIV4: Self = Self(0x02); + #[doc = "ETRP frequency divided by 8"] + pub const DIV8: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Urs(pub u8); + impl Urs { + #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"] + pub const ANYEVENT: Self = Self(0); + #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"] + pub const COUNTERONLY: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ocpe(pub u8); + impl Ocpe { + #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"] + pub const DISABLED: Self = Self(0); + #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ece(pub u8); + impl Ece { + #[doc = "External clock mode 2 disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mms(pub u8); + impl Mms { + #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"] + pub const RESET: Self = Self(0); + #[doc = "The counter enable signal, CNT_EN, is used as trigger output"] + pub const ENABLE: Self = Self(0x01); + #[doc = "The update event is selected as trigger output"] + pub const UPDATE: Self = Self(0x02); + #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"] + pub const COMPAREPULSE: Self = Self(0x03); + #[doc = "OC1REF signal is used as trigger output"] + pub const COMPAREOC1: Self = Self(0x04); + #[doc = "OC2REF signal is used as trigger output"] + pub const COMPAREOC2: Self = Self(0x05); + #[doc = "OC3REF signal is used as trigger output"] + pub const COMPAREOC3: Self = Self(0x06); + #[doc = "OC4REF signal is used as trigger output"] + pub const COMPAREOC4: Self = Self(0x07); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "counter"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cnt32(pub u32); + impl Cnt32 { + #[doc = "counter value"] + pub const fn cnt(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "counter value"] + pub fn set_cnt(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Cnt32 { + fn default() -> Cnt32 { + Cnt32(0) + } + } + #[doc = "DMA address for full transfer"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dmar(pub u32); + impl Dmar { + #[doc = "DMA register for burst accesses"] + pub const fn dmab(&self) -> u16 { let val = (self.0 >> 0usize) & 0xffff; val as u16 } - #[doc = "Rx CRC register"] - pub fn set_rx_crc(&mut self, val: u16) { + #[doc = "DMA register for burst accesses"] + pub fn set_dmab(&mut self, val: u16) { self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); } } - impl Default for Rxcrcr { - fn default() -> Rxcrcr { - Rxcrcr(0) - } - } - #[doc = "TX CRC register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Txcrcr(pub u32); - impl Txcrcr { - #[doc = "Tx CRC register"] - pub const fn tx_crc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Tx CRC register"] - pub fn set_tx_crc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Txcrcr { - fn default() -> Txcrcr { - Txcrcr(0) + impl Default for Dmar { + fn default() -> Dmar { + Dmar(0) } } #[doc = "status register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Sr(pub u32); - impl Sr { - #[doc = "Receive buffer not empty"] - pub const fn rxne(&self) -> bool { + pub struct SrGp(pub u32); + impl SrGp { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Receive buffer not empty"] - pub fn set_rxne(&mut self, val: bool) { + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Transmit buffer empty"] - pub const fn txe(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; + #[doc = "Capture/compare 1 interrupt flag"] + pub fn ccif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; val != 0 } - #[doc = "Transmit buffer empty"] - pub fn set_txe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + #[doc = "Capture/compare 1 interrupt flag"] + pub fn set_ccif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } - #[doc = "CRC error flag"] - pub const fn crcerr(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "CRC error flag"] - pub fn set_crcerr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Mode fault"] - pub const fn modf(&self) -> bool { + #[doc = "COM interrupt flag"] + pub const fn comif(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Mode fault"] - pub fn set_modf(&mut self, val: bool) { + #[doc = "COM interrupt flag"] + pub fn set_comif(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Overrun flag"] - pub const fn ovr(&self) -> bool { + #[doc = "Trigger interrupt flag"] + pub const fn tif(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Overrun flag"] - pub fn set_ovr(&mut self, val: bool) { + #[doc = "Trigger interrupt flag"] + pub fn set_tif(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "Busy flag"] - pub const fn bsy(&self) -> bool { + #[doc = "Break interrupt flag"] + pub const fn bif(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Busy flag"] - pub fn set_bsy(&mut self, val: bool) { + #[doc = "Break interrupt flag"] + pub fn set_bif(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - #[doc = "TI frame format error"] - pub const fn fre(&self) -> bool { + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn ccof(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn set_ccof(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for SrGp { + fn default() -> SrGp { + SrGp(0) + } + } + #[doc = "prescaler"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Psc(pub u32); + impl Psc { + #[doc = "Prescaler value"] + pub const fn psc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Prescaler value"] + pub fn set_psc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Psc { + fn default() -> Psc { + Psc(0) + } + } + #[doc = "capture/compare register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccr16(pub u32); + impl Ccr16 { + #[doc = "Capture/Compare 1 value"] + pub const fn ccr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Capture/Compare 1 value"] + pub fn set_ccr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Ccr16 { + fn default() -> Ccr16 { + Ccr16(0) + } + } + #[doc = "event generation register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct EgrGp(pub u32); + impl EgrGp { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 generation"] + pub fn ccg(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 generation"] + pub fn set_ccg(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare control update generation"] + pub const fn comg(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Capture/Compare control update generation"] + pub fn set_comg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger generation"] + pub const fn tg(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger generation"] + pub fn set_tg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break generation"] + pub const fn bg(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break generation"] + pub fn set_bg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for EgrGp { + fn default() -> EgrGp { + EgrGp(0) + } + } + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierAdv(pub u32); + impl DierAdv { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn ccie(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn set_ccie(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt enable"] + pub const fn comie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt enable"] + pub fn set_comie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt enable"] + pub const fn tie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt enable"] + pub fn set_tie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt enable"] + pub const fn bie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break interrupt enable"] + pub fn set_bie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "TI frame format error"] - pub fn set_fre(&mut self, val: bool) { + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn ccde(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn set_ccde(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM DMA request enable"] + pub const fn comde(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "COM DMA request enable"] + pub fn set_comde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Trigger DMA request enable"] + pub const fn tde(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Trigger DMA request enable"] + pub fn set_tde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } } - impl Default for Sr { - fn default() -> Sr { - Sr(0) + impl Default for DierAdv { + fn default() -> DierAdv { + DierAdv(0) + } + } + #[doc = "repetition counter register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rcr(pub u32); + impl Rcr { + #[doc = "Repetition counter value"] + pub const fn rep(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Repetition counter value"] + pub fn set_rep(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + } + impl Default for Rcr { + fn default() -> Rcr { + Rcr(0) + } + } + #[doc = "event generation register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct EgrAdv(pub u32); + impl EgrAdv { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 generation"] + pub fn ccg(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 generation"] + pub fn set_ccg(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare control update generation"] + pub const fn comg(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Capture/Compare control update generation"] + pub fn set_comg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger generation"] + pub const fn tg(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger generation"] + pub fn set_tg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break generation"] + pub const fn bg(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break generation"] + pub fn set_bg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for EgrAdv { + fn default() -> EgrAdv { + EgrAdv(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1Gp(pub u32); + impl Cr1Gp { + #[doc = "Counter enable"] + pub const fn cen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Counter enable"] + pub fn set_cen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update disable"] + pub const fn udis(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Update disable"] + pub fn set_udis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Update request source"] + pub const fn urs(&self) -> super::vals::Urs { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Urs(val as u8) + } + #[doc = "Update request source"] + pub fn set_urs(&mut self, val: super::vals::Urs) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "One-pulse mode"] + pub const fn opm(&self) -> super::vals::Opm { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Opm(val as u8) + } + #[doc = "One-pulse mode"] + pub fn set_opm(&mut self, val: super::vals::Opm) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Direction"] + pub const fn dir(&self) -> super::vals::Dir { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Dir(val as u8) + } + #[doc = "Direction"] + pub fn set_dir(&mut self, val: super::vals::Dir) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Center-aligned mode selection"] + pub const fn cms(&self) -> super::vals::Cms { + let val = (self.0 >> 5usize) & 0x03; + super::vals::Cms(val as u8) + } + #[doc = "Center-aligned mode selection"] + pub fn set_cms(&mut self, val: super::vals::Cms) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize); + } + #[doc = "Auto-reload preload enable"] + pub const fn arpe(&self) -> super::vals::Arpe { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Arpe(val as u8) + } + #[doc = "Auto-reload preload enable"] + pub fn set_arpe(&mut self, val: super::vals::Arpe) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Clock division"] + pub const fn ckd(&self) -> super::vals::Ckd { + let val = (self.0 >> 8usize) & 0x03; + super::vals::Ckd(val as u8) + } + #[doc = "Clock division"] + pub fn set_ckd(&mut self, val: super::vals::Ckd) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); + } + } + impl Default for Cr1Gp { + fn default() -> Cr1Gp { + Cr1Gp(0) + } + } + #[doc = "capture/compare register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccr32(pub u32); + impl Ccr32 { + #[doc = "Capture/Compare 1 value"] + pub const fn ccr(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Capture/Compare 1 value"] + pub fn set_ccr(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Ccr32 { + fn default() -> Ccr32 { + Ccr32(0) + } + } + #[doc = "capture/compare mode register 1 (input mode)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcmrInput(pub u32); + impl CcmrInput { + #[doc = "Capture/Compare 1 selection"] + pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + super::vals::CcmrInputCcs(val as u8) + } + #[doc = "Capture/Compare 1 selection"] + pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Input capture 1 prescaler"] + pub fn icpsc(&self, n: usize) -> u8 { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + val as u8 + } + #[doc = "Input capture 1 prescaler"] + pub fn set_icpsc(&mut self, n: usize, val: u8) { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs); + } + #[doc = "Input capture 1 filter"] + pub fn icf(&self, n: usize) -> super::vals::Icf { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + let val = (self.0 >> offs) & 0x0f; + super::vals::Icf(val as u8) + } + #[doc = "Input capture 1 filter"] + pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); + } + } + impl Default for CcmrInput { + fn default() -> CcmrInput { + CcmrInput(0) + } + } + #[doc = "auto-reload register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Arr32(pub u32); + impl Arr32 { + #[doc = "Auto-reload value"] + pub const fn arr(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Auto-reload value"] + pub fn set_arr(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Arr32 { + fn default() -> Arr32 { + Arr32(0) + } + } + #[doc = "slave mode control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Smcr(pub u32); + impl Smcr { + #[doc = "Slave mode selection"] + pub const fn sms(&self) -> super::vals::Sms { + let val = (self.0 >> 0usize) & 0x07; + super::vals::Sms(val as u8) + } + #[doc = "Slave mode selection"] + pub fn set_sms(&mut self, val: super::vals::Sms) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize); + } + #[doc = "Trigger selection"] + pub const fn ts(&self) -> super::vals::Ts { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Ts(val as u8) + } + #[doc = "Trigger selection"] + pub fn set_ts(&mut self, val: super::vals::Ts) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "Master/Slave mode"] + pub const fn msm(&self) -> super::vals::Msm { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Msm(val as u8) + } + #[doc = "Master/Slave mode"] + pub fn set_msm(&mut self, val: super::vals::Msm) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "External trigger filter"] + pub const fn etf(&self) -> super::vals::Etf { + let val = (self.0 >> 8usize) & 0x0f; + super::vals::Etf(val as u8) + } + #[doc = "External trigger filter"] + pub fn set_etf(&mut self, val: super::vals::Etf) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); + } + #[doc = "External trigger prescaler"] + pub const fn etps(&self) -> super::vals::Etps { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Etps(val as u8) + } + #[doc = "External trigger prescaler"] + pub fn set_etps(&mut self, val: super::vals::Etps) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "External clock enable"] + pub const fn ece(&self) -> super::vals::Ece { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Ece(val as u8) + } + #[doc = "External clock enable"] + pub fn set_ece(&mut self, val: super::vals::Ece) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + #[doc = "External trigger polarity"] + pub const fn etp(&self) -> super::vals::Etp { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Etp(val as u8) + } + #[doc = "External trigger polarity"] + pub fn set_etp(&mut self, val: super::vals::Etp) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + } + impl Default for Smcr { + fn default() -> Smcr { + Smcr(0) } } #[doc = "control register 2"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2(pub u32); - impl Cr2 { - #[doc = "Rx buffer DMA enable"] - pub const fn rxdmaen(&self) -> bool { + pub struct Cr2Basic(pub u32); + impl Cr2Basic { + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + } + impl Default for Cr2Basic { + fn default() -> Cr2Basic { + Cr2Basic(0) + } + } + #[doc = "capture/compare enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcerAdv(pub u32); + impl CcerAdv { + #[doc = "Capture/Compare 1 output enable"] + pub fn cce(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output enable"] + pub fn set_cce(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 complementary output enable"] + pub fn ccne(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 complementary output enable"] + pub fn set_ccne(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccnp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccnp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcerAdv { + fn default() -> CcerAdv { + CcerAdv(0) + } + } + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierGp(pub u32); + impl DierGp { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Rx buffer DMA enable"] - pub fn set_rxdmaen(&mut self, val: bool) { + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Tx buffer DMA enable"] - pub const fn txdmaen(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn ccie(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; val != 0 } - #[doc = "Tx buffer DMA enable"] - pub fn set_txdmaen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn set_ccie(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } - #[doc = "SS output enable"] - pub const fn ssoe(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "SS output enable"] - pub fn set_ssoe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Frame format"] - pub const fn frf(&self) -> super::vals::Frf { - let val = (self.0 >> 4usize) & 0x01; - super::vals::Frf(val as u8) - } - #[doc = "Frame format"] - pub fn set_frf(&mut self, val: super::vals::Frf) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); - } - #[doc = "Error interrupt enable"] - pub const fn errie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Error interrupt enable"] - pub fn set_errie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "RX buffer not empty interrupt enable"] - pub const fn rxneie(&self) -> bool { + #[doc = "Trigger interrupt enable"] + pub const fn tie(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "RX buffer not empty interrupt enable"] - pub fn set_rxneie(&mut self, val: bool) { + #[doc = "Trigger interrupt enable"] + pub fn set_tie(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "Tx buffer empty interrupt enable"] - pub const fn txeie(&self) -> bool { + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn ccde(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn set_ccde(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Trigger DMA request enable"] + pub const fn tde(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Trigger DMA request enable"] + pub fn set_tde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for DierGp { + fn default() -> DierGp { + DierGp(0) + } + } + #[doc = "auto-reload register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Arr16(pub u32); + impl Arr16 { + #[doc = "Auto-reload value"] + pub const fn arr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Auto-reload value"] + pub fn set_arr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Arr16 { + fn default() -> Arr16 { + Arr16(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrBasic(pub u32); + impl SrBasic { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for SrBasic { + fn default() -> SrBasic { + SrBasic(0) + } + } + #[doc = "DMA control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dcr(pub u32); + impl Dcr { + #[doc = "DMA base address"] + pub const fn dba(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 + } + #[doc = "DMA base address"] + pub fn set_dba(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); + } + #[doc = "DMA burst length"] + pub const fn dbl(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x1f; + val as u8 + } + #[doc = "DMA burst length"] + pub fn set_dbl(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); + } + } + impl Default for Dcr { + fn default() -> Dcr { + Dcr(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Adv(pub u32); + impl Cr2Adv { + #[doc = "Capture/compare preloaded control"] + pub const fn ccpc(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Capture/compare preloaded control"] + pub fn set_ccpc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare control update selection"] + pub const fn ccus(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Capture/compare control update selection"] + pub fn set_ccus(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Capture/compare DMA selection"] + pub const fn ccds(&self) -> super::vals::Ccds { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Ccds(val as u8) + } + #[doc = "Capture/compare DMA selection"] + pub fn set_ccds(&mut self, val: super::vals::Ccds) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "TI1 selection"] + pub const fn ti1s(&self) -> super::vals::Tis { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Tis(val as u8) + } + #[doc = "TI1 selection"] + pub fn set_ti1s(&mut self, val: super::vals::Tis) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Output Idle state 1"] + pub fn ois(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 8usize + n * 2usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output Idle state 1"] + pub fn set_ois(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 8usize + n * 2usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Output Idle state 1"] + pub const fn ois1n(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 1"] + pub fn set_ois1n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Output Idle state 2"] + pub const fn ois2n(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 2"] + pub fn set_ois2n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Output Idle state 3"] + pub const fn ois3n(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 3"] + pub fn set_ois3n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + } + impl Default for Cr2Adv { + fn default() -> Cr2Adv { + Cr2Adv(0) + } + } + #[doc = "event generation register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct EgrBasic(pub u32); + impl EgrBasic { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for EgrBasic { + fn default() -> EgrBasic { + EgrBasic(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1Basic(pub u32); + impl Cr1Basic { + #[doc = "Counter enable"] + pub const fn cen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Counter enable"] + pub fn set_cen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update disable"] + pub const fn udis(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Update disable"] + pub fn set_udis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Update request source"] + pub const fn urs(&self) -> super::vals::Urs { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Urs(val as u8) + } + #[doc = "Update request source"] + pub fn set_urs(&mut self, val: super::vals::Urs) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "One-pulse mode"] + pub const fn opm(&self) -> super::vals::Opm { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Opm(val as u8) + } + #[doc = "One-pulse mode"] + pub fn set_opm(&mut self, val: super::vals::Opm) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Auto-reload preload enable"] + pub const fn arpe(&self) -> super::vals::Arpe { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Arpe(val as u8) + } + #[doc = "Auto-reload preload enable"] + pub fn set_arpe(&mut self, val: super::vals::Arpe) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + } + impl Default for Cr1Basic { + fn default() -> Cr1Basic { + Cr1Basic(0) + } + } + #[doc = "capture/compare enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcerGp(pub u32); + impl CcerGp { + #[doc = "Capture/Compare 1 output enable"] + pub fn cce(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output enable"] + pub fn set_cce(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccnp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccnp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcerGp { + fn default() -> CcerGp { + CcerGp(0) + } + } + #[doc = "capture/compare mode register 2 (output mode)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcmrOutput(pub u32); + impl CcmrOutput { + #[doc = "Capture/Compare 3 selection"] + pub fn ccs(&self, n: usize) -> super::vals::CcmrOutputCcs { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + super::vals::CcmrOutputCcs(val as u8) + } + #[doc = "Capture/Compare 3 selection"] + pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrOutputCcs) { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Output compare 3 fast enable"] + pub fn ocfe(&self, n: usize) -> bool { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output compare 3 fast enable"] + pub fn set_ocfe(&mut self, n: usize, val: bool) { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Output compare 3 preload enable"] + pub fn ocpe(&self, n: usize) -> super::vals::Ocpe { + assert!(n < 2usize); + let offs = 3usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Ocpe(val as u8) + } + #[doc = "Output compare 3 preload enable"] + pub fn set_ocpe(&mut self, n: usize, val: super::vals::Ocpe) { + assert!(n < 2usize); + let offs = 3usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Output compare 3 mode"] + pub fn ocm(&self, n: usize) -> super::vals::Ocm { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + let val = (self.0 >> offs) & 0x07; + super::vals::Ocm(val as u8) + } + #[doc = "Output compare 3 mode"] + pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + self.0 = (self.0 & !(0x07 << offs)) | (((val.0 as u32) & 0x07) << offs); + } + #[doc = "Output compare 3 clear enable"] + pub fn occe(&self, n: usize) -> bool { + assert!(n < 2usize); + let offs = 7usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output compare 3 clear enable"] + pub fn set_occe(&mut self, n: usize, val: bool) { + assert!(n < 2usize); + let offs = 7usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcmrOutput { + fn default() -> CcmrOutput { + CcmrOutput(0) + } + } + #[doc = "counter"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cnt16(pub u32); + impl Cnt16 { + #[doc = "counter value"] + pub const fn cnt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "counter value"] + pub fn set_cnt(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Cnt16 { + fn default() -> Cnt16 { + Cnt16(0) + } + } + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierBasic(pub u32); + impl DierBasic { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for DierBasic { + fn default() -> DierBasic { + DierBasic(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrAdv(pub u32); + impl SrAdv { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn ccif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn set_ccif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt flag"] + pub const fn comif(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt flag"] + pub fn set_comif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt flag"] + pub const fn tif(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt flag"] + pub fn set_tif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt flag"] + pub const fn bif(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Tx buffer empty interrupt enable"] - pub fn set_txeie(&mut self, val: bool) { + #[doc = "Break interrupt flag"] + pub fn set_bif(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn ccof(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn set_ccof(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } } - impl Default for Cr2 { - fn default() -> Cr2 { - Cr2(0) + impl Default for SrAdv { + fn default() -> SrAdv { + SrAdv(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Gp(pub u32); + impl Cr2Gp { + #[doc = "Capture/compare DMA selection"] + pub const fn ccds(&self) -> super::vals::Ccds { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Ccds(val as u8) + } + #[doc = "Capture/compare DMA selection"] + pub fn set_ccds(&mut self, val: super::vals::Ccds) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "TI1 selection"] + pub const fn ti1s(&self) -> super::vals::Tis { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Tis(val as u8) + } + #[doc = "TI1 selection"] + pub fn set_ti1s(&mut self, val: super::vals::Tis) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + } + impl Default for Cr2Gp { + fn default() -> Cr2Gp { + Cr2Gp(0) + } + } + #[doc = "break and dead-time register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Bdtr(pub u32); + impl Bdtr { + #[doc = "Dead-time generator setup"] + pub const fn dtg(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Dead-time generator setup"] + pub fn set_dtg(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Lock configuration"] + pub const fn lock(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x03; + val as u8 + } + #[doc = "Lock configuration"] + pub fn set_lock(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); + } + #[doc = "Off-state selection for Idle mode"] + pub const fn ossi(&self) -> super::vals::Ossi { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Ossi(val as u8) + } + #[doc = "Off-state selection for Idle mode"] + pub fn set_ossi(&mut self, val: super::vals::Ossi) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Off-state selection for Run mode"] + pub const fn ossr(&self) -> super::vals::Ossr { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Ossr(val as u8) + } + #[doc = "Off-state selection for Run mode"] + pub fn set_ossr(&mut self, val: super::vals::Ossr) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "Break enable"] + pub const fn bke(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Break enable"] + pub fn set_bke(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Break polarity"] + pub const fn bkp(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Break polarity"] + pub fn set_bkp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Automatic output enable"] + pub const fn aoe(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Automatic output enable"] + pub fn set_aoe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Main output enable"] + pub const fn moe(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Main output enable"] + pub fn set_moe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + } + impl Default for Bdtr { + fn default() -> Bdtr { + Bdtr(0) } } } @@ -2548,162 +4978,6 @@ pub mod syscfg_h7 { } pub mod regs { use crate::generic::*; - #[doc = "SYSCFG user register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur2(pub u32); - impl Ur2 { - #[doc = "BOR_LVL Brownout Reset Threshold Level"] - pub const fn borh(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x03; - val as u8 - } - #[doc = "BOR_LVL Brownout Reset Threshold Level"] - pub fn set_borh(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); - } - #[doc = "Boot Address 0"] - pub const fn boot_add0(&self) -> u16 { - let val = (self.0 >> 16usize) & 0xffff; - val as u16 - } - #[doc = "Boot Address 0"] - pub fn set_boot_add0(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); - } - } - impl Default for Ur2 { - fn default() -> Ur2 { - Ur2(0) - } - } - #[doc = "SYSCFG user register 8"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur8(pub u32); - impl Ur8 { - #[doc = "Mass erase protected area disabled for bank 2"] - pub const fn mepad_2(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Mass erase protected area disabled for bank 2"] - pub fn set_mepad_2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Mass erase secured area disabled for bank 2"] - pub const fn mesad_2(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Mass erase secured area disabled for bank 2"] - pub fn set_mesad_2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur8 { - fn default() -> Ur8 { - Ur8(0) - } - } - #[doc = "SYSCFG user register 9"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur9(pub u32); - impl Ur9 { - #[doc = "Write protection for flash bank 2"] - pub const fn wrpn_2(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Write protection for flash bank 2"] - pub fn set_wrpn_2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - #[doc = "Protected area start address for bank 2"] - pub const fn pa_beg_2(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x0fff; - val as u16 - } - #[doc = "Protected area start address for bank 2"] - pub fn set_pa_beg_2(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); - } - } - impl Default for Ur9 { - fn default() -> Ur9 { - Ur9(0) - } - } - #[doc = "SYSCFG compensation cell code register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cccr(pub u32); - impl Cccr { - #[doc = "NMOS compensation code"] - pub const fn ncc(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "NMOS compensation code"] - pub fn set_ncc(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "PMOS compensation code"] - pub const fn pcc(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 - } - #[doc = "PMOS compensation code"] - pub fn set_pcc(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); - } - } - impl Default for Cccr { - fn default() -> Cccr { - Cccr(0) - } - } - #[doc = "SYSCFG user register 17"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur17(pub u32); - impl Ur17 { - #[doc = "I/O high speed / low voltage"] - pub const fn io_hslv(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "I/O high speed / low voltage"] - pub fn set_io_hslv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for Ur17 { - fn default() -> Ur17 { - Ur17(0) - } - } - #[doc = "SYSCFG user register 14"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur14(pub u32); - impl Ur14 { - #[doc = "D1 Stop Reset"] - pub const fn d1stprst(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "D1 Stop Reset"] - pub fn set_d1stprst(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for Ur14 { - fn default() -> Ur14 { - Ur14(0) - } - } #[doc = "SYSCFG user register 7"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -2733,111 +5007,84 @@ pub mod syscfg_h7 { Ur7(0) } } - #[doc = "SYSCFG user register 12"] + #[doc = "SYSCFG package register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur12(pub u32); - impl Ur12 { - #[doc = "Secure mode"] - pub const fn secure(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Secure mode"] - pub fn set_secure(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur12 { - fn default() -> Ur12 { - Ur12(0) - } - } - #[doc = "SYSCFG user register 0"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur0(pub u32); - impl Ur0 { - #[doc = "Bank Swap"] - pub const fn bks(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Bank Swap"] - pub fn set_bks(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Readout protection"] - pub const fn rdp(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; + pub struct Pkgr(pub u32); + impl Pkgr { + #[doc = "Package"] + pub const fn pkg(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; val as u8 } - #[doc = "Readout protection"] - pub fn set_rdp(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); + #[doc = "Package"] + pub fn set_pkg(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); } } - impl Default for Ur0 { - fn default() -> Ur0 { - Ur0(0) + impl Default for Pkgr { + fn default() -> Pkgr { + Pkgr(0) } } - #[doc = "SYSCFG user register 11"] + #[doc = "SYSCFG user register 15"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur11(pub u32); - impl Ur11 { - #[doc = "Secured area end address for bank 2"] - pub const fn sa_end_2(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; + pub struct Ur15(pub u32); + impl Ur15 { + #[doc = "Freeze independent watchdog in Standby mode"] + pub const fn fziwdgstb(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Freeze independent watchdog in Standby mode"] + pub fn set_fziwdgstb(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur15 { + fn default() -> Ur15 { + Ur15(0) + } + } + #[doc = "SYSCFG user register 4"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur4(pub u32); + impl Ur4 { + #[doc = "Mass Erase Protected Area Disabled for bank 1"] + pub const fn mepad_1(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Mass Erase Protected Area Disabled for bank 1"] + pub fn set_mepad_1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur4 { + fn default() -> Ur4 { + Ur4(0) + } + } + #[doc = "SYSCFG user register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur3(pub u32); + impl Ur3 { + #[doc = "Boot Address 1"] + pub const fn boot_add1(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; val as u16 } - #[doc = "Secured area end address for bank 2"] - pub fn set_sa_end_2(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Independent Watchdog 1 mode"] - pub const fn iwdg1m(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Independent Watchdog 1 mode"] - pub fn set_iwdg1m(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + #[doc = "Boot Address 1"] + pub fn set_boot_add1(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); } } - impl Default for Ur11 { - fn default() -> Ur11 { - Ur11(0) - } - } - #[doc = "SYSCFG user register 16"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur16(pub u32); - impl Ur16 { - #[doc = "Freeze independent watchdog in Stop mode"] - pub const fn fziwdgstp(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Freeze independent watchdog in Stop mode"] - pub fn set_fziwdgstp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Private key programmed"] - pub const fn pkp(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Private key programmed"] - pub fn set_pkp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur16 { - fn default() -> Ur16 { - Ur16(0) + impl Default for Ur3 { + fn default() -> Ur3 { + Ur3(0) } } #[doc = "SYSCFG user register 13"] @@ -2869,273 +5116,6 @@ pub mod syscfg_h7 { Ur13(0) } } - #[doc = "SYSCFG user register 5"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur5(pub u32); - impl Ur5 { - #[doc = "Mass erase secured area disabled for bank 1"] - pub const fn mesad_1(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Mass erase secured area disabled for bank 1"] - pub fn set_mesad_1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Write protection for flash bank 1"] - pub const fn wrpn_1(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Write protection for flash bank 1"] - pub fn set_wrpn_1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } - } - impl Default for Ur5 { - fn default() -> Ur5 { - Ur5(0) - } - } - #[doc = "compensation cell control/status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cccsr(pub u32); - impl Cccsr { - #[doc = "enable"] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "enable"] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Code selection"] - pub const fn cs(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Code selection"] - pub fn set_cs(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Compensation cell ready flag"] - pub const fn ready(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Compensation cell ready flag"] - pub fn set_ready(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "High-speed at low-voltage"] - pub const fn hslv(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "High-speed at low-voltage"] - pub fn set_hslv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Cccsr { - fn default() -> Cccsr { - Cccsr(0) - } - } - #[doc = "SYSCFG user register 4"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur4(pub u32); - impl Ur4 { - #[doc = "Mass Erase Protected Area Disabled for bank 1"] - pub const fn mepad_1(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Mass Erase Protected Area Disabled for bank 1"] - pub fn set_mepad_1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur4 { - fn default() -> Ur4 { - Ur4(0) - } - } - #[doc = "SYSCFG user register 10"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur10(pub u32); - impl Ur10 { - #[doc = "Protected area end address for bank 2"] - pub const fn pa_end_2(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Protected area end address for bank 2"] - pub fn set_pa_end_2(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Secured area start address for bank 2"] - pub const fn sa_beg_2(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x0fff; - val as u16 - } - #[doc = "Secured area start address for bank 2"] - pub fn set_sa_beg_2(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); - } - } - impl Default for Ur10 { - fn default() -> Ur10 { - Ur10(0) - } - } - #[doc = "SYSCFG user register 15"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur15(pub u32); - impl Ur15 { - #[doc = "Freeze independent watchdog in Standby mode"] - pub const fn fziwdgstb(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Freeze independent watchdog in Standby mode"] - pub fn set_fziwdgstb(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur15 { - fn default() -> Ur15 { - Ur15(0) - } - } - #[doc = "SYSCFG user register 3"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur3(pub u32); - impl Ur3 { - #[doc = "Boot Address 1"] - pub const fn boot_add1(&self) -> u16 { - let val = (self.0 >> 16usize) & 0xffff; - val as u16 - } - #[doc = "Boot Address 1"] - pub fn set_boot_add1(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); - } - } - impl Default for Ur3 { - fn default() -> Ur3 { - Ur3(0) - } - } - #[doc = "SYSCFG package register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pkgr(pub u32); - impl Pkgr { - #[doc = "Package"] - pub const fn pkg(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Package"] - pub fn set_pkg(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - } - impl Default for Pkgr { - fn default() -> Pkgr { - Pkgr(0) - } - } - #[doc = "SYSCFG user register 6"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur6(pub u32); - impl Ur6 { - #[doc = "Protected area start address for bank 1"] - pub const fn pa_beg_1(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Protected area start address for bank 1"] - pub fn set_pa_beg_1(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Protected area end address for bank 1"] - pub const fn pa_end_1(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x0fff; - val as u16 - } - #[doc = "Protected area end address for bank 1"] - pub fn set_pa_end_1(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); - } - } - impl Default for Ur6 { - fn default() -> Ur6 { - Ur6(0) - } - } - #[doc = "external interrupt configuration register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Exticr(pub u32); - impl Exticr { - #[doc = "EXTI x configuration (x = 4 to 7)"] - pub fn exti(&self, n: usize) -> u8 { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x0f; - val as u8 - } - #[doc = "EXTI x configuration (x = 4 to 7)"] - pub fn set_exti(&mut self, n: usize, val: u8) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); - } - } - impl Default for Exticr { - fn default() -> Exticr { - Exticr(0) - } - } - #[doc = "SYSCFG compensation cell value register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ccvr(pub u32); - impl Ccvr { - #[doc = "NMOS compensation value"] - pub const fn ncv(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "NMOS compensation value"] - pub fn set_ncv(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "PMOS compensation value"] - pub const fn pcv(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 - } - #[doc = "PMOS compensation value"] - pub fn set_pcv(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); - } - } - impl Default for Ccvr { - fn default() -> Ccvr { - Ccvr(0) - } - } #[doc = "peripheral mode configuration register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -3282,6 +5262,206 @@ pub mod syscfg_h7 { Pmcr(0) } } + #[doc = "SYSCFG user register 8"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur8(pub u32); + impl Ur8 { + #[doc = "Mass erase protected area disabled for bank 2"] + pub const fn mepad_2(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Mass erase protected area disabled for bank 2"] + pub fn set_mepad_2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Mass erase secured area disabled for bank 2"] + pub const fn mesad_2(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Mass erase secured area disabled for bank 2"] + pub fn set_mesad_2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur8 { + fn default() -> Ur8 { + Ur8(0) + } + } + #[doc = "SYSCFG compensation cell code register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cccr(pub u32); + impl Cccr { + #[doc = "NMOS compensation code"] + pub const fn ncc(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "NMOS compensation code"] + pub fn set_ncc(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "PMOS compensation code"] + pub const fn pcc(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "PMOS compensation code"] + pub fn set_pcc(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + } + impl Default for Cccr { + fn default() -> Cccr { + Cccr(0) + } + } + #[doc = "SYSCFG user register 12"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur12(pub u32); + impl Ur12 { + #[doc = "Secure mode"] + pub const fn secure(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Secure mode"] + pub fn set_secure(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur12 { + fn default() -> Ur12 { + Ur12(0) + } + } + #[doc = "SYSCFG user register 17"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur17(pub u32); + impl Ur17 { + #[doc = "I/O high speed / low voltage"] + pub const fn io_hslv(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "I/O high speed / low voltage"] + pub fn set_io_hslv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for Ur17 { + fn default() -> Ur17 { + Ur17(0) + } + } + #[doc = "SYSCFG user register 14"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur14(pub u32); + impl Ur14 { + #[doc = "D1 Stop Reset"] + pub const fn d1stprst(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "D1 Stop Reset"] + pub fn set_d1stprst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for Ur14 { + fn default() -> Ur14 { + Ur14(0) + } + } + #[doc = "SYSCFG user register 5"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur5(pub u32); + impl Ur5 { + #[doc = "Mass erase secured area disabled for bank 1"] + pub const fn mesad_1(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Mass erase secured area disabled for bank 1"] + pub fn set_mesad_1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Write protection for flash bank 1"] + pub const fn wrpn_1(&self) -> u8 { + let val = (self.0 >> 16usize) & 0xff; + val as u8 + } + #[doc = "Write protection for flash bank 1"] + pub fn set_wrpn_1(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); + } + } + impl Default for Ur5 { + fn default() -> Ur5 { + Ur5(0) + } + } + #[doc = "external interrupt configuration register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Exticr(pub u32); + impl Exticr { + #[doc = "EXTI x configuration (x = 4 to 7)"] + pub fn exti(&self, n: usize) -> u8 { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + val as u8 + } + #[doc = "EXTI x configuration (x = 4 to 7)"] + pub fn set_exti(&mut self, n: usize, val: u8) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); + } + } + impl Default for Exticr { + fn default() -> Exticr { + Exticr(0) + } + } + #[doc = "SYSCFG user register 10"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur10(pub u32); + impl Ur10 { + #[doc = "Protected area end address for bank 2"] + pub const fn pa_end_2(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area end address for bank 2"] + pub fn set_pa_end_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Secured area start address for bank 2"] + pub const fn sa_beg_2(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area start address for bank 2"] + pub fn set_sa_beg_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur10 { + fn default() -> Ur10 { + Ur10(0) + } + } #[doc = "SYSCFG power control register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -3302,6 +5482,256 @@ pub mod syscfg_h7 { Pwrcr(0) } } + #[doc = "compensation cell control/status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cccsr(pub u32); + impl Cccsr { + #[doc = "enable"] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "enable"] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Code selection"] + pub const fn cs(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Code selection"] + pub fn set_cs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Compensation cell ready flag"] + pub const fn ready(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Compensation cell ready flag"] + pub fn set_ready(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "High-speed at low-voltage"] + pub const fn hslv(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "High-speed at low-voltage"] + pub fn set_hslv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Cccsr { + fn default() -> Cccsr { + Cccsr(0) + } + } + #[doc = "SYSCFG user register 6"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur6(pub u32); + impl Ur6 { + #[doc = "Protected area start address for bank 1"] + pub const fn pa_beg_1(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area start address for bank 1"] + pub fn set_pa_beg_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Protected area end address for bank 1"] + pub const fn pa_end_1(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area end address for bank 1"] + pub fn set_pa_end_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur6 { + fn default() -> Ur6 { + Ur6(0) + } + } + #[doc = "SYSCFG user register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur2(pub u32); + impl Ur2 { + #[doc = "BOR_LVL Brownout Reset Threshold Level"] + pub const fn borh(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x03; + val as u8 + } + #[doc = "BOR_LVL Brownout Reset Threshold Level"] + pub fn set_borh(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); + } + #[doc = "Boot Address 0"] + pub const fn boot_add0(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "Boot Address 0"] + pub fn set_boot_add0(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + } + } + impl Default for Ur2 { + fn default() -> Ur2 { + Ur2(0) + } + } + #[doc = "SYSCFG user register 9"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur9(pub u32); + impl Ur9 { + #[doc = "Write protection for flash bank 2"] + pub const fn wrpn_2(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Write protection for flash bank 2"] + pub fn set_wrpn_2(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Protected area start address for bank 2"] + pub const fn pa_beg_2(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area start address for bank 2"] + pub fn set_pa_beg_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur9 { + fn default() -> Ur9 { + Ur9(0) + } + } + #[doc = "SYSCFG user register 11"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur11(pub u32); + impl Ur11 { + #[doc = "Secured area end address for bank 2"] + pub const fn sa_end_2(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area end address for bank 2"] + pub fn set_sa_end_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Independent Watchdog 1 mode"] + pub const fn iwdg1m(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Independent Watchdog 1 mode"] + pub fn set_iwdg1m(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur11 { + fn default() -> Ur11 { + Ur11(0) + } + } + #[doc = "SYSCFG compensation cell value register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccvr(pub u32); + impl Ccvr { + #[doc = "NMOS compensation value"] + pub const fn ncv(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "NMOS compensation value"] + pub fn set_ncv(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "PMOS compensation value"] + pub const fn pcv(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "PMOS compensation value"] + pub fn set_pcv(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + } + impl Default for Ccvr { + fn default() -> Ccvr { + Ccvr(0) + } + } + #[doc = "SYSCFG user register 0"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur0(pub u32); + impl Ur0 { + #[doc = "Bank Swap"] + pub const fn bks(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Bank Swap"] + pub fn set_bks(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Readout protection"] + pub const fn rdp(&self) -> u8 { + let val = (self.0 >> 16usize) & 0xff; + val as u8 + } + #[doc = "Readout protection"] + pub fn set_rdp(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); + } + } + impl Default for Ur0 { + fn default() -> Ur0 { + Ur0(0) + } + } + #[doc = "SYSCFG user register 16"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur16(pub u32); + impl Ur16 { + #[doc = "Freeze independent watchdog in Stop mode"] + pub const fn fziwdgstp(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Freeze independent watchdog in Stop mode"] + pub fn set_fziwdgstp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Private key programmed"] + pub const fn pkp(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Private key programmed"] + pub fn set_pkp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur16 { + fn default() -> Ur16 { + Ur16(0) + } + } } } pub mod rng_v1 { @@ -3327,6 +5757,35 @@ pub mod rng_v1 { } pub mod regs { use crate::generic::*; + #[doc = "control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Random number generator enable"] + pub const fn rngen(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Random number generator enable"] + pub fn set_rngen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Interrupt enable"] + pub const fn ie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Interrupt enable"] + pub fn set_ie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } #[doc = "status register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -3383,942 +5842,172 @@ pub mod rng_v1 { Sr(0) } } - #[doc = "control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr(pub u32); - impl Cr { - #[doc = "Random number generator enable"] - pub const fn rngen(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Random number generator enable"] - pub fn set_rngen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Interrupt enable"] - pub const fn ie(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Interrupt enable"] - pub fn set_ie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - } - impl Default for Cr { - fn default() -> Cr { - Cr(0) - } - } } } -pub mod usart_v1 { +pub mod syscfg_f4 { use crate::generic::*; - #[doc = "Universal synchronous asynchronous receiver transmitter"] + #[doc = "System configuration controller"] #[derive(Copy, Clone)] - pub struct Usart(pub *mut u8); - unsafe impl Send for Usart {} - unsafe impl Sync for Usart {} - impl Usart { - #[doc = "Status register"] - pub fn sr(self) -> Reg { + pub struct Syscfg(pub *mut u8); + unsafe impl Send for Syscfg {} + unsafe impl Sync for Syscfg {} + impl Syscfg { + #[doc = "memory remap register"] + pub fn memrm(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(0usize)) } } - #[doc = "Data register"] - pub fn dr(self) -> Reg { + #[doc = "peripheral mode configuration register"] + pub fn pmc(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(4usize)) } } - #[doc = "Baud rate register"] - pub fn brr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } + #[doc = "external interrupt configuration register"] + pub fn exticr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } } - #[doc = "Control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "Control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "Control register 3"] - pub fn cr3(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "Guard time and prescaler register"] - pub fn gtpr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } - } - } - #[doc = "Universal asynchronous receiver transmitter"] - #[derive(Copy, Clone)] - pub struct Uart(pub *mut u8); - unsafe impl Send for Uart {} - unsafe impl Sync for Uart {} - impl Uart { - #[doc = "Status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "Data register"] - pub fn dr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "Baud rate register"] - pub fn brr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "Control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "Control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "Control register 3"] - pub fn cr3(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct M(pub u8); - impl M { - #[doc = "8 data bits"] - pub const M8: Self = Self(0); - #[doc = "9 data bits"] - pub const M9: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpha(pub u8); - impl Cpha { - #[doc = "The first clock transition is the first data capture edge"] - pub const FIRST: Self = Self(0); - #[doc = "The second clock transition is the first data capture edge"] - pub const SECOND: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Irlp(pub u8); - impl Irlp { - #[doc = "Normal mode"] - pub const NORMAL: Self = Self(0); - #[doc = "Low-power mode"] - pub const LOWPOWER: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lbdl(pub u8); - impl Lbdl { - #[doc = "10-bit break detection"] - pub const LBDL10: Self = Self(0); - #[doc = "11-bit break detection"] - pub const LBDL11: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Sbk(pub u8); - impl Sbk { - #[doc = "No break character is transmitted"] - pub const NOBREAK: Self = Self(0); - #[doc = "Break character transmitted"] - pub const BREAK: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Hdsel(pub u8); - impl Hdsel { - #[doc = "Half duplex mode is not selected"] - pub const FULLDUPLEX: Self = Self(0); - #[doc = "Half duplex mode is selected"] - pub const HALFDUPLEX: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Rwu(pub u8); - impl Rwu { - #[doc = "Receiver in active mode"] - pub const ACTIVE: Self = Self(0); - #[doc = "Receiver in mute mode"] - pub const MUTE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Wake(pub u8); - impl Wake { - #[doc = "USART wakeup on idle line"] - pub const IDLELINE: Self = Self(0); - #[doc = "USART wakeup on address mark"] - pub const ADDRESSMARK: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Stop(pub u8); - impl Stop { - #[doc = "1 stop bit"] - pub const STOP1: Self = Self(0); - #[doc = "0.5 stop bits"] - pub const STOP0P5: Self = Self(0x01); - #[doc = "2 stop bits"] - pub const STOP2: Self = Self(0x02); - #[doc = "1.5 stop bits"] - pub const STOP1P5: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ps(pub u8); - impl Ps { - #[doc = "Even parity"] - pub const EVEN: Self = Self(0); - #[doc = "Odd parity"] - pub const ODD: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpol(pub u8); - impl Cpol { - #[doc = "Steady low value on CK pin outside transmission window"] - pub const LOW: Self = Self(0); - #[doc = "Steady high value on CK pin outside transmission window"] - pub const HIGH: Self = Self(0x01); + #[doc = "Compensation cell control register"] + pub fn cmpcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } } } pub mod regs { use crate::generic::*; - #[doc = "Control register 3"] + #[doc = "Compensation cell control register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr3Usart(pub u32); - impl Cr3Usart { - #[doc = "Error interrupt enable"] - pub const fn eie(&self) -> bool { + pub struct Cmpcr(pub u32); + impl Cmpcr { + #[doc = "Compensation cell power-down"] + pub const fn cmp_pd(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Error interrupt enable"] - pub fn set_eie(&mut self, val: bool) { + #[doc = "Compensation cell power-down"] + pub fn set_cmp_pd(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "IrDA mode enable"] - pub const fn iren(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "IrDA mode enable"] - pub fn set_iren(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "IrDA low-power"] - pub const fn irlp(&self) -> super::vals::Irlp { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Irlp(val as u8) - } - #[doc = "IrDA low-power"] - pub fn set_irlp(&mut self, val: super::vals::Irlp) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "Half-duplex selection"] - pub const fn hdsel(&self) -> super::vals::Hdsel { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Hdsel(val as u8) - } - #[doc = "Half-duplex selection"] - pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Smartcard NACK enable"] - pub const fn nack(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "Smartcard NACK enable"] - pub fn set_nack(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Smartcard mode enable"] - pub const fn scen(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Smartcard mode enable"] - pub fn set_scen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "DMA enable receiver"] - pub const fn dmar(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "DMA enable receiver"] - pub fn set_dmar(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "DMA enable transmitter"] - pub const fn dmat(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "DMA enable transmitter"] - pub fn set_dmat(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "RTS enable"] - pub const fn rtse(&self) -> bool { + #[doc = "READY"] + pub const fn ready(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "RTS enable"] - pub fn set_rtse(&mut self, val: bool) { + #[doc = "READY"] + pub fn set_ready(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } - #[doc = "CTS enable"] - pub const fn ctse(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "CTS enable"] - pub fn set_ctse(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "CTS interrupt enable"] - pub const fn ctsie(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "CTS interrupt enable"] - pub fn set_ctsie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + impl Default for Cmpcr { + fn default() -> Cmpcr { + Cmpcr(0) } } - impl Default for Cr3Usart { - fn default() -> Cr3Usart { - Cr3Usart(0) - } - } - #[doc = "Control register 3"] + #[doc = "external interrupt configuration register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr3(pub u32); - impl Cr3 { - #[doc = "Error interrupt enable"] - pub const fn eie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Error interrupt enable"] - pub fn set_eie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "IrDA mode enable"] - pub const fn iren(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "IrDA mode enable"] - pub fn set_iren(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "IrDA low-power"] - pub const fn irlp(&self) -> super::vals::Irlp { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Irlp(val as u8) - } - #[doc = "IrDA low-power"] - pub fn set_irlp(&mut self, val: super::vals::Irlp) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "Half-duplex selection"] - pub const fn hdsel(&self) -> super::vals::Hdsel { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Hdsel(val as u8) - } - #[doc = "Half-duplex selection"] - pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "DMA enable receiver"] - pub const fn dmar(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "DMA enable receiver"] - pub fn set_dmar(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "DMA enable transmitter"] - pub const fn dmat(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "DMA enable transmitter"] - pub fn set_dmat(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - } - impl Default for Cr3 { - fn default() -> Cr3 { - Cr3(0) - } - } - #[doc = "Baud rate register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Brr(pub u32); - impl Brr { - #[doc = "fraction of USARTDIV"] - pub const fn div_fraction(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; + pub struct Exticr(pub u32); + impl Exticr { + #[doc = "EXTI x configuration"] + pub fn exti(&self, n: usize) -> u8 { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; val as u8 } - #[doc = "fraction of USARTDIV"] - pub fn set_div_fraction(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "mantissa of USARTDIV"] - pub const fn div_mantissa(&self) -> u16 { - let val = (self.0 >> 4usize) & 0x0fff; - val as u16 - } - #[doc = "mantissa of USARTDIV"] - pub fn set_div_mantissa(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize); + #[doc = "EXTI x configuration"] + pub fn set_exti(&mut self, n: usize, val: u8) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); } } - impl Default for Brr { - fn default() -> Brr { - Brr(0) + impl Default for Exticr { + fn default() -> Exticr { + Exticr(0) } } - #[doc = "Control register 1"] + #[doc = "memory remap register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1(pub u32); - impl Cr1 { - #[doc = "Send break"] - pub const fn sbk(&self) -> super::vals::Sbk { - let val = (self.0 >> 0usize) & 0x01; - super::vals::Sbk(val as u8) + pub struct Memrm(pub u32); + impl Memrm { + #[doc = "Memory mapping selection"] + pub const fn mem_mode(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x07; + val as u8 } - #[doc = "Send break"] - pub fn set_sbk(&mut self, val: super::vals::Sbk) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); + #[doc = "Memory mapping selection"] + pub fn set_mem_mode(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); } - #[doc = "Receiver wakeup"] - pub const fn rwu(&self) -> super::vals::Rwu { - let val = (self.0 >> 1usize) & 0x01; - super::vals::Rwu(val as u8) - } - #[doc = "Receiver wakeup"] - pub fn set_rwu(&mut self, val: super::vals::Rwu) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); - } - #[doc = "Receiver enable"] - pub const fn re(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Receiver enable"] - pub fn set_re(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Transmitter enable"] - pub const fn te(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Transmitter enable"] - pub fn set_te(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "IDLE interrupt enable"] - pub const fn idleie(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "IDLE interrupt enable"] - pub fn set_idleie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "RXNE interrupt enable"] - pub const fn rxneie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "RXNE interrupt enable"] - pub fn set_rxneie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Transmission complete interrupt enable"] - pub const fn tcie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Transmission complete interrupt enable"] - pub fn set_tcie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "TXE interrupt enable"] - pub const fn txeie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "TXE interrupt enable"] - pub fn set_txeie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "PE interrupt enable"] - pub const fn peie(&self) -> bool { + #[doc = "Flash bank mode selection"] + pub const fn fb_mode(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "PE interrupt enable"] - pub fn set_peie(&mut self, val: bool) { + #[doc = "Flash bank mode selection"] + pub fn set_fb_mode(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } - #[doc = "Parity selection"] - pub const fn ps(&self) -> super::vals::Ps { - let val = (self.0 >> 9usize) & 0x01; - super::vals::Ps(val as u8) - } - #[doc = "Parity selection"] - pub fn set_ps(&mut self, val: super::vals::Ps) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); - } - #[doc = "Parity control enable"] - pub const fn pce(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "Parity control enable"] - pub fn set_pce(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "Wakeup method"] - pub const fn wake(&self) -> super::vals::Wake { - let val = (self.0 >> 11usize) & 0x01; - super::vals::Wake(val as u8) - } - #[doc = "Wakeup method"] - pub fn set_wake(&mut self, val: super::vals::Wake) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); - } - #[doc = "Word length"] - pub const fn m(&self) -> super::vals::M { - let val = (self.0 >> 12usize) & 0x01; - super::vals::M(val as u8) - } - #[doc = "Word length"] - pub fn set_m(&mut self, val: super::vals::M) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); - } - #[doc = "USART enable"] - pub const fn ue(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "USART enable"] - pub fn set_ue(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - } - impl Default for Cr1 { - fn default() -> Cr1 { - Cr1(0) - } - } - #[doc = "Guard time and prescaler register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Gtpr(pub u32); - impl Gtpr { - #[doc = "Prescaler value"] - pub const fn psc(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; + #[doc = "FMC memory mapping swap"] + pub const fn swp_fmc(&self) -> u8 { + let val = (self.0 >> 10usize) & 0x03; val as u8 } - #[doc = "Prescaler value"] - pub fn set_psc(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - #[doc = "Guard time value"] - pub const fn gt(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Guard time value"] - pub fn set_gt(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); + #[doc = "FMC memory mapping swap"] + pub fn set_swp_fmc(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize); } } - impl Default for Gtpr { - fn default() -> Gtpr { - Gtpr(0) + impl Default for Memrm { + fn default() -> Memrm { + Memrm(0) } } - #[doc = "Data register"] + #[doc = "peripheral mode configuration register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dr(pub u32); - impl Dr { - #[doc = "Data value"] - pub const fn dr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x01ff; - val as u16 + pub struct Pmc(pub u32); + impl Pmc { + #[doc = "ADC1DC2"] + pub const fn adc1dc2(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 } - #[doc = "Data value"] - pub fn set_dr(&mut self, val: u16) { - self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize); + #[doc = "ADC1DC2"] + pub fn set_adc1dc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "ADC2DC2"] + pub const fn adc2dc2(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "ADC2DC2"] + pub fn set_adc2dc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "ADC3DC2"] + pub const fn adc3dc2(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "ADC3DC2"] + pub fn set_adc3dc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Ethernet PHY interface selection"] + pub const fn mii_rmii_sel(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Ethernet PHY interface selection"] + pub fn set_mii_rmii_sel(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); } } - impl Default for Dr { - fn default() -> Dr { - Dr(0) - } - } - #[doc = "Status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Sr(pub u32); - impl Sr { - #[doc = "Parity error"] - pub const fn pe(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Parity error"] - pub fn set_pe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Framing error"] - pub const fn fe(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Framing error"] - pub fn set_fe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Noise error flag"] - pub const fn ne(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Noise error flag"] - pub fn set_ne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Overrun error"] - pub const fn ore(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Overrun error"] - pub fn set_ore(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "IDLE line detected"] - pub const fn idle(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "IDLE line detected"] - pub fn set_idle(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Read data register not empty"] - pub const fn rxne(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Read data register not empty"] - pub fn set_rxne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Transmission complete"] - pub const fn tc(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Transmission complete"] - pub fn set_tc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Transmit data register empty"] - pub const fn txe(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Transmit data register empty"] - pub fn set_txe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "LIN break detection flag"] - pub const fn lbd(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "LIN break detection flag"] - pub fn set_lbd(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for Sr { - fn default() -> Sr { - Sr(0) - } - } - #[doc = "Status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct SrUsart(pub u32); - impl SrUsart { - #[doc = "Parity error"] - pub const fn pe(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Parity error"] - pub fn set_pe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Framing error"] - pub const fn fe(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Framing error"] - pub fn set_fe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Noise error flag"] - pub const fn ne(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Noise error flag"] - pub fn set_ne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Overrun error"] - pub const fn ore(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Overrun error"] - pub fn set_ore(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "IDLE line detected"] - pub const fn idle(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "IDLE line detected"] - pub fn set_idle(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Read data register not empty"] - pub const fn rxne(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Read data register not empty"] - pub fn set_rxne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Transmission complete"] - pub const fn tc(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Transmission complete"] - pub fn set_tc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Transmit data register empty"] - pub const fn txe(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Transmit data register empty"] - pub fn set_txe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "LIN break detection flag"] - pub const fn lbd(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "LIN break detection flag"] - pub fn set_lbd(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "CTS flag"] - pub const fn cts(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "CTS flag"] - pub fn set_cts(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - } - impl Default for SrUsart { - fn default() -> SrUsart { - SrUsart(0) - } - } - #[doc = "Control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2(pub u32); - impl Cr2 { - #[doc = "Address of the USART node"] - pub const fn add(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Address of the USART node"] - pub fn set_add(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "lin break detection length"] - pub const fn lbdl(&self) -> super::vals::Lbdl { - let val = (self.0 >> 5usize) & 0x01; - super::vals::Lbdl(val as u8) - } - #[doc = "lin break detection length"] - pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); - } - #[doc = "LIN break detection interrupt enable"] - pub const fn lbdie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "LIN break detection interrupt enable"] - pub fn set_lbdie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "STOP bits"] - pub const fn stop(&self) -> super::vals::Stop { - let val = (self.0 >> 12usize) & 0x03; - super::vals::Stop(val as u8) - } - #[doc = "STOP bits"] - pub fn set_stop(&mut self, val: super::vals::Stop) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); - } - #[doc = "LIN mode enable"] - pub const fn linen(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "LIN mode enable"] - pub fn set_linen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - } - impl Default for Cr2 { - fn default() -> Cr2 { - Cr2(0) - } - } - #[doc = "Control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2Usart(pub u32); - impl Cr2Usart { - #[doc = "Address of the USART node"] - pub const fn add(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Address of the USART node"] - pub fn set_add(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "lin break detection length"] - pub const fn lbdl(&self) -> super::vals::Lbdl { - let val = (self.0 >> 5usize) & 0x01; - super::vals::Lbdl(val as u8) - } - #[doc = "lin break detection length"] - pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); - } - #[doc = "LIN break detection interrupt enable"] - pub const fn lbdie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "LIN break detection interrupt enable"] - pub fn set_lbdie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Last bit clock pulse"] - pub const fn lbcl(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Last bit clock pulse"] - pub fn set_lbcl(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Clock phase"] - pub const fn cpha(&self) -> super::vals::Cpha { - let val = (self.0 >> 9usize) & 0x01; - super::vals::Cpha(val as u8) - } - #[doc = "Clock phase"] - pub fn set_cpha(&mut self, val: super::vals::Cpha) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); - } - #[doc = "Clock polarity"] - pub const fn cpol(&self) -> super::vals::Cpol { - let val = (self.0 >> 10usize) & 0x01; - super::vals::Cpol(val as u8) - } - #[doc = "Clock polarity"] - pub fn set_cpol(&mut self, val: super::vals::Cpol) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); - } - #[doc = "Clock enable"] - pub const fn clken(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "Clock enable"] - pub fn set_clken(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "STOP bits"] - pub const fn stop(&self) -> super::vals::Stop { - let val = (self.0 >> 12usize) & 0x03; - super::vals::Stop(val as u8) - } - #[doc = "STOP bits"] - pub fn set_stop(&mut self, val: super::vals::Stop) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); - } - #[doc = "LIN mode enable"] - pub const fn linen(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "LIN mode enable"] - pub fn set_linen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - } - impl Default for Cr2Usart { - fn default() -> Cr2Usart { - Cr2Usart(0) + impl Default for Pmc { + fn default() -> Pmc { + Pmc(0) } } } @@ -4419,135 +6108,477 @@ pub mod sdmmc_v2 { } pub mod regs { use crate::generic::*; - #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."] + #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cmdr(pub u32); - impl Cmdr { - #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."] - pub const fn cmdindex(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; - val as u8 - } - #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."] - pub fn set_cmdindex(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); - } - #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."] - pub const fn cmdtrans(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."] - pub fn set_cmdtrans(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."] - pub const fn cmdstop(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."] - pub fn set_cmdstop(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."] - pub const fn waitresp(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x03; - val as u8 - } - #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."] - pub fn set_waitresp(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); - } - #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."] - pub const fn waitint(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."] - pub fn set_waitint(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."] - pub const fn waitpend(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."] - pub fn set_waitpend(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."] - pub const fn cpsmen(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."] - pub fn set_cpsmen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."] - pub const fn dthold(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."] - pub fn set_dthold(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"] - pub const fn bootmode(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"] - pub fn set_bootmode(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[doc = "Enable boot mode procedure."] - pub const fn booten(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[doc = "Enable boot mode procedure."] - pub fn set_booten(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } - #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."] - pub const fn cmdsuspend(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."] - pub fn set_cmdsuspend(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Cmdr { - fn default() -> Cmdr { - Cmdr(0) - } - } - #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Acktimer(pub u32); - impl Acktimer { - #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] - pub const fn acktime(&self) -> u32 { + pub struct Dcntr(pub u32); + impl Dcntr { + #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] + pub const fn datacount(&self) -> u32 { let val = (self.0 >> 0usize) & 0x01ff_ffff; val as u32 } - #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] - pub fn set_acktime(&mut self, val: u32) { + #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] + pub fn set_datacount(&mut self, val: u32) { self.0 = (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); } } - impl Default for Acktimer { - fn default() -> Acktimer { - Acktimer(0) + impl Default for Dcntr { + fn default() -> Dcntr { + Dcntr(0) + } + } + #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idmabsizer(pub u32); + impl Idmabsizer { + #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn idmabndt(&self) -> u8 { + let val = (self.0 >> 5usize) & 0xff; + val as u8 + } + #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_idmabndt(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 5usize)) | (((val as u32) & 0xff) << 5usize); + } + } + impl Default for Idmabsizer { + fn default() -> Idmabsizer { + Idmabsizer(0) + } + } + #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Maskr(pub u32); + impl Maskr { + #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."] + pub const fn ccrcfailie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."] + pub fn set_ccrcfailie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."] + pub const fn dcrcfailie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."] + pub fn set_dcrcfailie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."] + pub const fn ctimeoutie(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."] + pub fn set_ctimeoutie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."] + pub const fn dtimeoutie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."] + pub fn set_dtimeoutie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."] + pub const fn txunderrie(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."] + pub fn set_txunderrie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."] + pub const fn rxoverrie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."] + pub fn set_rxoverrie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."] + pub const fn cmdrendie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."] + pub fn set_cmdrendie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."] + pub const fn cmdsentie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."] + pub fn set_cmdsentie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."] + pub const fn dataendie(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."] + pub fn set_dataendie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."] + pub const fn dholdie(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."] + pub fn set_dholdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."] + pub const fn dbckendie(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."] + pub fn set_dbckendie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."] + pub const fn dabortie(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."] + pub fn set_dabortie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."] + pub const fn txfifoheie(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."] + pub fn set_txfifoheie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."] + pub const fn rxfifohfie(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."] + pub fn set_rxfifohfie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."] + pub const fn rxfifofie(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."] + pub fn set_rxfifofie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."] + pub const fn txfifoeie(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."] + pub fn set_txfifoeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."] + pub const fn busyd0endie(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."] + pub fn set_busyd0endie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."] + pub const fn sdioitie(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."] + pub fn set_sdioitie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."] + pub const fn ackfailie(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."] + pub fn set_ackfailie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."] + pub const fn acktimeoutie(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."] + pub fn set_acktimeoutie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."] + pub const fn vswendie(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."] + pub fn set_vswendie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."] + pub const fn ckstopie(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."] + pub fn set_ckstopie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."] + pub const fn idmabtcie(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."] + pub fn set_idmabtcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + } + impl Default for Maskr { + fn default() -> Maskr { + Maskr(0) + } + } + #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idmabase1r(pub u32); + impl Idmabase1r { + #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] + pub const fn idmabase1(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] + pub fn set_idmabase1(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Idmabase1r { + fn default() -> Idmabase1r { + Idmabase1r(0) + } + } + #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Icr(pub u32); + impl Icr { + #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] + pub const fn ccrcfailc(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] + pub fn set_ccrcfailc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] + pub const fn dcrcfailc(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] + pub fn set_dcrcfailc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] + pub const fn ctimeoutc(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] + pub fn set_ctimeoutc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] + pub const fn dtimeoutc(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] + pub fn set_dtimeoutc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] + pub const fn txunderrc(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] + pub fn set_txunderrc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] + pub const fn rxoverrc(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] + pub fn set_rxoverrc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] + pub const fn cmdrendc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] + pub fn set_cmdrendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] + pub const fn cmdsentc(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] + pub fn set_cmdsentc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] + pub const fn dataendc(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] + pub fn set_dataendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] + pub const fn dholdc(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] + pub fn set_dholdc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] + pub const fn dbckendc(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] + pub fn set_dbckendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] + pub const fn dabortc(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] + pub fn set_dabortc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] + pub const fn busyd0endc(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] + pub fn set_busyd0endc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] + pub const fn sdioitc(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] + pub fn set_sdioitc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] + pub const fn ackfailc(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] + pub fn set_ackfailc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] + pub const fn acktimeoutc(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] + pub fn set_acktimeoutc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] + pub const fn vswendc(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] + pub fn set_vswendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] + pub const fn ckstopc(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] + pub fn set_ckstopc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] + pub const fn idmatec(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] + pub fn set_idmatec(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] + pub const fn idmabtcc(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] + pub fn set_idmabtcc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + } + impl Default for Icr { + fn default() -> Icr { + Icr(0) } } #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"] @@ -4822,222 +6853,138 @@ pub mod sdmmc_v2 { Star(0) } } - #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."] + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Maskr(pub u32); - impl Maskr { - #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."] - pub const fn ccrcfailie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 + pub struct Resp1r(pub u32); + impl Resp1r { + #[doc = "see Table 432"] + pub const fn cardstatus1(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 } - #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."] - pub fn set_ccrcfailie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."] - pub const fn dcrcfailie(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."] - pub fn set_dcrcfailie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."] - pub const fn ctimeoutie(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."] - pub fn set_ctimeoutie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."] - pub const fn dtimeoutie(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."] - pub fn set_dtimeoutie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."] - pub const fn txunderrie(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."] - pub fn set_txunderrie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."] - pub const fn rxoverrie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."] - pub fn set_rxoverrie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."] - pub const fn cmdrendie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."] - pub fn set_cmdrendie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."] - pub const fn cmdsentie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."] - pub fn set_cmdsentie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."] - pub const fn dataendie(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."] - pub fn set_dataendie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."] - pub const fn dholdie(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."] - pub fn set_dholdie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."] - pub const fn dbckendie(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."] - pub fn set_dbckendie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."] - pub const fn dabortie(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."] - pub fn set_dabortie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."] - pub const fn txfifoheie(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."] - pub fn set_txfifoheie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."] - pub const fn rxfifohfie(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."] - pub fn set_rxfifohfie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } - #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."] - pub const fn rxfifofie(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."] - pub fn set_rxfifofie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."] - pub const fn txfifoeie(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."] - pub fn set_txfifoeie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."] - pub const fn busyd0endie(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."] - pub fn set_busyd0endie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."] - pub const fn sdioitie(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."] - pub fn set_sdioitie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."] - pub const fn ackfailie(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."] - pub fn set_ackfailie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."] - pub const fn acktimeoutie(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."] - pub fn set_acktimeoutie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."] - pub const fn vswendie(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."] - pub fn set_vswendie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."] - pub const fn ckstopie(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."] - pub fn set_ckstopie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."] - pub const fn idmabtcie(&self) -> bool { - let val = (self.0 >> 28usize) & 0x01; - val != 0 - } - #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."] - pub fn set_idmabtcie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + #[doc = "see Table 432"] + pub fn set_cardstatus1(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); } } - impl Default for Maskr { - fn default() -> Maskr { - Maskr(0) + impl Default for Resp1r { + fn default() -> Resp1r { + Resp1r(0) + } + } + #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dlenr(pub u32); + impl Dlenr { + #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."] + pub const fn datalength(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x01ff_ffff; + val as u32 + } + #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."] + pub fn set_datalength(&mut self, val: u32) { + self.0 = + (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); + } + } + impl Default for Dlenr { + fn default() -> Dlenr { + Dlenr(0) + } + } + #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Argr(pub u32); + impl Argr { + #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] + pub const fn cmdarg(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] + pub fn set_cmdarg(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Argr { + fn default() -> Argr { + Argr(0) + } + } + #[doc = "SDMMC IP version register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ver(pub u32); + impl Ver { + #[doc = "IP minor revision number."] + pub const fn minrev(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "IP minor revision number."] + pub fn set_minrev(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "IP major revision number."] + pub const fn majrev(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "IP major revision number."] + pub fn set_majrev(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + } + impl Default for Ver { + fn default() -> Ver { + Ver(0) + } + } + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Resp3r(pub u32); + impl Resp3r { + #[doc = "see Table404."] + pub const fn cardstatus3(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "see Table404."] + pub fn set_cardstatus3(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Resp3r { + fn default() -> Resp3r { + Resp3r(0) + } + } + #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Fifor(pub u32); + impl Fifor { + #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] + pub const fn fifodata(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] + pub fn set_fifodata(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Fifor { + fn default() -> Fifor { + Fifor(0) } } #[doc = "SDMMC power control register"] @@ -5087,237 +7034,152 @@ pub mod sdmmc_v2 { Power(0) } } - #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."] + #[doc = "SDMMC IP identification register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dlenr(pub u32); - impl Dlenr { - #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."] - pub const fn datalength(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x01ff_ffff; - val as u32 - } - #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."] - pub fn set_datalength(&mut self, val: u32) { - self.0 = - (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); - } - } - impl Default for Dlenr { - fn default() -> Dlenr { - Dlenr(0) - } - } - #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Icr(pub u32); - impl Icr { - #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] - pub const fn ccrcfailc(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] - pub fn set_ccrcfailc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] - pub const fn dcrcfailc(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] - pub fn set_dcrcfailc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] - pub const fn ctimeoutc(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] - pub fn set_ctimeoutc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] - pub const fn dtimeoutc(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] - pub fn set_dtimeoutc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] - pub const fn txunderrc(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] - pub fn set_txunderrc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] - pub const fn rxoverrc(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] - pub fn set_rxoverrc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] - pub const fn cmdrendc(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] - pub fn set_cmdrendc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] - pub const fn cmdsentc(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] - pub fn set_cmdsentc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] - pub const fn dataendc(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] - pub fn set_dataendc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] - pub const fn dholdc(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] - pub fn set_dholdc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] - pub const fn dbckendc(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] - pub fn set_dbckendc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] - pub const fn dabortc(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] - pub fn set_dabortc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] - pub const fn busyd0endc(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] - pub fn set_busyd0endc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] - pub const fn sdioitc(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] - pub fn set_sdioitc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] - pub const fn ackfailc(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] - pub fn set_ackfailc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] - pub const fn acktimeoutc(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] - pub fn set_acktimeoutc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] - pub const fn vswendc(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] - pub fn set_vswendc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] - pub const fn ckstopc(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] - pub fn set_ckstopc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] - pub const fn idmatec(&self) -> bool { - let val = (self.0 >> 27usize) & 0x01; - val != 0 - } - #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] - pub fn set_idmatec(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); - } - #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] - pub const fn idmabtcc(&self) -> bool { - let val = (self.0 >> 28usize) & 0x01; - val != 0 - } - #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] - pub fn set_idmabtcc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); - } - } - impl Default for Icr { - fn default() -> Icr { - Icr(0) - } - } - #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Resp1r(pub u32); - impl Resp1r { - #[doc = "see Table 432"] - pub const fn cardstatus1(&self) -> u32 { + pub struct Id(pub u32); + impl Id { + #[doc = "SDMMC IP identification."] + pub const fn ip_id(&self) -> u32 { let val = (self.0 >> 0usize) & 0xffff_ffff; val as u32 } - #[doc = "see Table 432"] - pub fn set_cardstatus1(&mut self, val: u32) { + #[doc = "SDMMC IP identification."] + pub fn set_ip_id(&mut self, val: u32) { self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); } } - impl Default for Resp1r { - fn default() -> Resp1r { - Resp1r(0) + impl Default for Id { + fn default() -> Id { + Id(0) + } + } + #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idmabase0r(pub u32); + impl Idmabase0r { + #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."] + pub const fn idmabase0(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."] + pub fn set_idmabase0(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Idmabase0r { + fn default() -> Idmabase0r { + Idmabase0r(0) + } + } + #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Acktimer(pub u32); + impl Acktimer { + #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] + pub const fn acktime(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x01ff_ffff; + val as u32 + } + #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] + pub fn set_acktime(&mut self, val: u32) { + self.0 = + (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); + } + } + impl Default for Acktimer { + fn default() -> Acktimer { + Acktimer(0) + } + } + #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Clkcr(pub u32); + impl Clkcr { + #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] + pub const fn clkdiv(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x03ff; + val as u16 + } + #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] + pub fn set_clkdiv(&mut self, val: u16) { + self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize); + } + #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] + pub const fn pwrsav(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] + pub fn set_pwrsav(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub const fn widbus(&self) -> u8 { + let val = (self.0 >> 14usize) & 0x03; + val as u8 + } + #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub fn set_widbus(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize); + } + #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] + pub const fn negedge(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] + pub fn set_negedge(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] + pub const fn hwfc_en(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] + pub fn set_hwfc_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] + pub const fn ddr(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] + pub fn set_ddr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub const fn busspeed(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub fn set_busspeed(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub const fn selclkrx(&self) -> u8 { + let val = (self.0 >> 20usize) & 0x03; + val as u8 + } + #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub fn set_selclkrx(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize); + } + } + impl Default for Clkcr { + fn default() -> Clkcr { + Clkcr(0) } } #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."] @@ -5421,303 +7283,114 @@ pub mod sdmmc_v2 { Dctrl(0) } } - #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."] + #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dcntr(pub u32); - impl Dcntr { - #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] - pub const fn datacount(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x01ff_ffff; - val as u32 + pub struct Cmdr(pub u32); + impl Cmdr { + #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."] + pub const fn cmdindex(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x3f; + val as u8 } - #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] - pub fn set_datacount(&mut self, val: u32) { - self.0 = - (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); + #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."] + pub fn set_cmdindex(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); } - } - impl Default for Dcntr { - fn default() -> Dcntr { - Dcntr(0) + #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."] + pub const fn cmdtrans(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 } - } - #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Clkcr(pub u32); - impl Clkcr { - #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] - pub const fn clkdiv(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x03ff; - val as u16 + #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."] + pub fn set_cmdtrans(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] - pub fn set_clkdiv(&mut self, val: u16) { - self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize); + #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."] + pub const fn cmdstop(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 } - #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] - pub const fn pwrsav(&self) -> bool { + #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."] + pub fn set_cmdstop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."] + pub const fn waitresp(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x03; + val as u8 + } + #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."] + pub fn set_waitresp(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); + } + #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."] + pub const fn waitint(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."] + pub fn set_waitint(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."] + pub const fn waitpend(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."] + pub fn set_waitpend(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."] + pub const fn cpsmen(&self) -> bool { let val = (self.0 >> 12usize) & 0x01; val != 0 } - #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] - pub fn set_pwrsav(&mut self, val: bool) { + #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."] + pub fn set_cpsmen(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); } - #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub const fn widbus(&self) -> u8 { - let val = (self.0 >> 14usize) & 0x03; - val as u8 + #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."] + pub const fn dthold(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 } - #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub fn set_widbus(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize); + #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."] + pub fn set_dthold(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); } - #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] - pub const fn negedge(&self) -> bool { + #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"] + pub const fn bootmode(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"] + pub fn set_bootmode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Enable boot mode procedure."] + pub const fn booten(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Enable boot mode procedure."] + pub fn set_booten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."] + pub const fn cmdsuspend(&self) -> bool { let val = (self.0 >> 16usize) & 0x01; val != 0 } - #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] - pub fn set_negedge(&mut self, val: bool) { + #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."] + pub fn set_cmdsuspend(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } - #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] - pub const fn hwfc_en(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] - pub fn set_hwfc_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] - pub const fn ddr(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] - pub fn set_ddr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub const fn busspeed(&self) -> bool { - let val = (self.0 >> 19usize) & 0x01; - val != 0 - } - #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub fn set_busspeed(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); - } - #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub const fn selclkrx(&self) -> u8 { - let val = (self.0 >> 20usize) & 0x03; - val as u8 - } - #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub fn set_selclkrx(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize); - } } - impl Default for Clkcr { - fn default() -> Clkcr { - Clkcr(0) - } - } - #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Argr(pub u32); - impl Argr { - #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] - pub const fn cmdarg(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] - pub fn set_cmdarg(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Argr { - fn default() -> Argr { - Argr(0) - } - } - #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idmactrlr(pub u32); - impl Idmactrlr { - #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn idmaen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_idmaen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn idmabmode(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_idmabmode(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."] - pub const fn idmabact(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."] - pub fn set_idmabact(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - } - impl Default for Idmactrlr { - fn default() -> Idmactrlr { - Idmactrlr(0) - } - } - #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Fifor(pub u32); - impl Fifor { - #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] - pub const fn fifodata(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] - pub fn set_fifodata(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Fifor { - fn default() -> Fifor { - Fifor(0) - } - } - #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dtimer(pub u32); - impl Dtimer { - #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] - pub const fn datatime(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] - pub fn set_datatime(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Dtimer { - fn default() -> Dtimer { - Dtimer(0) - } - } - #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Resp2r(pub u32); - impl Resp2r { - #[doc = "see Table404."] - pub const fn cardstatus2(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "see Table404."] - pub fn set_cardstatus2(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Resp2r { - fn default() -> Resp2r { - Resp2r(0) - } - } - #[doc = "SDMMC IP version register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ver(pub u32); - impl Ver { - #[doc = "IP minor revision number."] - pub const fn minrev(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "IP minor revision number."] - pub fn set_minrev(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "IP major revision number."] - pub const fn majrev(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 - } - #[doc = "IP major revision number."] - pub fn set_majrev(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); - } - } - impl Default for Ver { - fn default() -> Ver { - Ver(0) - } - } - #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Resp3r(pub u32); - impl Resp3r { - #[doc = "see Table404."] - pub const fn cardstatus3(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "see Table404."] - pub fn set_cardstatus3(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Resp3r { - fn default() -> Resp3r { - Resp3r(0) - } - } - #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idmabase1r(pub u32); - impl Idmabase1r { - #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] -are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] - pub const fn idmabase1(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] -are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] - pub fn set_idmabase1(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Idmabase1r { - fn default() -> Idmabase1r { - Idmabase1r(0) + impl Default for Cmdr { + fn default() -> Cmdr { + Cmdr(0) } } #[doc = "SDMMC command response register"] @@ -5761,70 +7434,995 @@ are always 0 and read only). This register can be written by firmware when DPSM Resp4r(0) } } - #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."] + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idmabase0r(pub u32); - impl Idmabase0r { - #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] -are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."] - pub const fn idmabase0(&self) -> u32 { + pub struct Resp2r(pub u32); + impl Resp2r { + #[doc = "see Table404."] + pub const fn cardstatus2(&self) -> u32 { let val = (self.0 >> 0usize) & 0xffff_ffff; val as u32 } - #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] -are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."] - pub fn set_idmabase0(&mut self, val: u32) { + #[doc = "see Table404."] + pub fn set_cardstatus2(&mut self, val: u32) { self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); } } - impl Default for Idmabase0r { - fn default() -> Idmabase0r { - Idmabase0r(0) + impl Default for Resp2r { + fn default() -> Resp2r { + Resp2r(0) } } - #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."] + #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idmabsizer(pub u32); - impl Idmabsizer { - #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn idmabndt(&self) -> u8 { - let val = (self.0 >> 5usize) & 0xff; + pub struct Idmactrlr(pub u32); + impl Idmactrlr { + #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn idmaen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_idmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn idmabmode(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_idmabmode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."] + pub const fn idmabact(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."] + pub fn set_idmabact(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + } + impl Default for Idmactrlr { + fn default() -> Idmactrlr { + Idmactrlr(0) + } + } + #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dtimer(pub u32); + impl Dtimer { + #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] + pub const fn datatime(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] + pub fn set_datatime(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Dtimer { + fn default() -> Dtimer { + Dtimer(0) + } + } + } +} +pub mod usart_v1 { + use crate::generic::*; + #[doc = "Universal asynchronous receiver transmitter"] + #[derive(Copy, Clone)] + pub struct Uart(pub *mut u8); + unsafe impl Send for Uart {} + unsafe impl Sync for Uart {} + impl Uart { + #[doc = "Status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Baud rate register"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Control register 3"] + pub fn cr3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + } + #[doc = "Universal synchronous asynchronous receiver transmitter"] + #[derive(Copy, Clone)] + pub struct Usart(pub *mut u8); + unsafe impl Send for Usart {} + unsafe impl Sync for Usart {} + impl Usart { + #[doc = "Status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Baud rate register"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Control register 3"] + pub fn cr3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "Guard time and prescaler register"] + pub fn gtpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "Status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Parity error"] + pub const fn pe(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Parity error"] + pub fn set_pe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Framing error"] + pub const fn fe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Framing error"] + pub fn set_fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Noise error flag"] + pub const fn ne(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Noise error flag"] + pub fn set_ne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Overrun error"] + pub const fn ore(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Overrun error"] + pub fn set_ore(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE line detected"] + pub const fn idle(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE line detected"] + pub fn set_idle(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Read data register not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Read data register not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete"] + pub const fn tc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete"] + pub fn set_tc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Transmit data register empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Transmit data register empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "LIN break detection flag"] + pub const fn lbd(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection flag"] + pub fn set_lbd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + #[doc = "Control register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr3Usart(pub u32); + impl Cr3Usart { + #[doc = "Error interrupt enable"] + pub const fn eie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_eie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "IrDA mode enable"] + pub const fn iren(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "IrDA mode enable"] + pub fn set_iren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "IrDA low-power"] + pub const fn irlp(&self) -> super::vals::Irlp { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Irlp(val as u8) + } + #[doc = "IrDA low-power"] + pub fn set_irlp(&mut self, val: super::vals::Irlp) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Half-duplex selection"] + pub const fn hdsel(&self) -> super::vals::Hdsel { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Hdsel(val as u8) + } + #[doc = "Half-duplex selection"] + pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Smartcard NACK enable"] + pub const fn nack(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Smartcard NACK enable"] + pub fn set_nack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Smartcard mode enable"] + pub const fn scen(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Smartcard mode enable"] + pub fn set_scen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "DMA enable receiver"] + pub const fn dmar(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "DMA enable receiver"] + pub fn set_dmar(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "DMA enable transmitter"] + pub const fn dmat(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "DMA enable transmitter"] + pub fn set_dmat(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "RTS enable"] + pub const fn rtse(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "RTS enable"] + pub fn set_rtse(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "CTS enable"] + pub const fn ctse(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "CTS enable"] + pub fn set_ctse(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "CTS interrupt enable"] + pub const fn ctsie(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "CTS interrupt enable"] + pub fn set_ctsie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + } + impl Default for Cr3Usart { + fn default() -> Cr3Usart { + Cr3Usart(0) + } + } + #[doc = "Control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1(pub u32); + impl Cr1 { + #[doc = "Send break"] + pub const fn sbk(&self) -> super::vals::Sbk { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Sbk(val as u8) + } + #[doc = "Send break"] + pub fn set_sbk(&mut self, val: super::vals::Sbk) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); + } + #[doc = "Receiver wakeup"] + pub const fn rwu(&self) -> super::vals::Rwu { + let val = (self.0 >> 1usize) & 0x01; + super::vals::Rwu(val as u8) + } + #[doc = "Receiver wakeup"] + pub fn set_rwu(&mut self, val: super::vals::Rwu) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); + } + #[doc = "Receiver enable"] + pub const fn re(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Receiver enable"] + pub fn set_re(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Transmitter enable"] + pub const fn te(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Transmitter enable"] + pub fn set_te(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE interrupt enable"] + pub const fn idleie(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE interrupt enable"] + pub fn set_idleie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "RXNE interrupt enable"] + pub const fn rxneie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "RXNE interrupt enable"] + pub fn set_rxneie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "TXE interrupt enable"] + pub const fn txeie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "TXE interrupt enable"] + pub fn set_txeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "PE interrupt enable"] + pub const fn peie(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "PE interrupt enable"] + pub fn set_peie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Parity selection"] + pub const fn ps(&self) -> super::vals::Ps { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Ps(val as u8) + } + #[doc = "Parity selection"] + pub fn set_ps(&mut self, val: super::vals::Ps) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Parity control enable"] + pub const fn pce(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Parity control enable"] + pub fn set_pce(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Wakeup method"] + pub const fn wake(&self) -> super::vals::Wake { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Wake(val as u8) + } + #[doc = "Wakeup method"] + pub fn set_wake(&mut self, val: super::vals::Wake) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "Word length"] + pub const fn m(&self) -> super::vals::M { + let val = (self.0 >> 12usize) & 0x01; + super::vals::M(val as u8) + } + #[doc = "Word length"] + pub fn set_m(&mut self, val: super::vals::M) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "USART enable"] + pub const fn ue(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "USART enable"] + pub fn set_ue(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + } + impl Default for Cr1 { + fn default() -> Cr1 { + Cr1(0) + } + } + #[doc = "Control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2(pub u32); + impl Cr2 { + #[doc = "Address of the USART node"] + pub const fn add(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; val as u8 } - #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_idmabndt(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 5usize)) | (((val as u32) & 0xff) << 5usize); + #[doc = "Address of the USART node"] + pub fn set_add(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "lin break detection length"] + pub const fn lbdl(&self) -> super::vals::Lbdl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Lbdl(val as u8) + } + #[doc = "lin break detection length"] + pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "LIN break detection interrupt enable"] + pub const fn lbdie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection interrupt enable"] + pub fn set_lbdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "STOP bits"] + pub const fn stop(&self) -> super::vals::Stop { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Stop(val as u8) + } + #[doc = "STOP bits"] + pub fn set_stop(&mut self, val: super::vals::Stop) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "LIN mode enable"] + pub const fn linen(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "LIN mode enable"] + pub fn set_linen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); } } - impl Default for Idmabsizer { - fn default() -> Idmabsizer { - Idmabsizer(0) + impl Default for Cr2 { + fn default() -> Cr2 { + Cr2(0) } } - #[doc = "SDMMC IP identification register"] + #[doc = "Control register 2"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Id(pub u32); - impl Id { - #[doc = "SDMMC IP identification."] - pub const fn ip_id(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 + pub struct Cr2Usart(pub u32); + impl Cr2Usart { + #[doc = "Address of the USART node"] + pub const fn add(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 } - #[doc = "SDMMC IP identification."] - pub fn set_ip_id(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + #[doc = "Address of the USART node"] + pub fn set_add(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "lin break detection length"] + pub const fn lbdl(&self) -> super::vals::Lbdl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Lbdl(val as u8) + } + #[doc = "lin break detection length"] + pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "LIN break detection interrupt enable"] + pub const fn lbdie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection interrupt enable"] + pub fn set_lbdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Last bit clock pulse"] + pub const fn lbcl(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Last bit clock pulse"] + pub fn set_lbcl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Clock phase"] + pub const fn cpha(&self) -> super::vals::Cpha { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Cpha(val as u8) + } + #[doc = "Clock phase"] + pub fn set_cpha(&mut self, val: super::vals::Cpha) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Clock polarity"] + pub const fn cpol(&self) -> super::vals::Cpol { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Cpol(val as u8) + } + #[doc = "Clock polarity"] + pub fn set_cpol(&mut self, val: super::vals::Cpol) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Clock enable"] + pub const fn clken(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Clock enable"] + pub fn set_clken(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "STOP bits"] + pub const fn stop(&self) -> super::vals::Stop { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Stop(val as u8) + } + #[doc = "STOP bits"] + pub fn set_stop(&mut self, val: super::vals::Stop) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "LIN mode enable"] + pub const fn linen(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "LIN mode enable"] + pub fn set_linen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); } } - impl Default for Id { - fn default() -> Id { - Id(0) + impl Default for Cr2Usart { + fn default() -> Cr2Usart { + Cr2Usart(0) } } + #[doc = "Control register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr3(pub u32); + impl Cr3 { + #[doc = "Error interrupt enable"] + pub const fn eie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_eie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "IrDA mode enable"] + pub const fn iren(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "IrDA mode enable"] + pub fn set_iren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "IrDA low-power"] + pub const fn irlp(&self) -> super::vals::Irlp { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Irlp(val as u8) + } + #[doc = "IrDA low-power"] + pub fn set_irlp(&mut self, val: super::vals::Irlp) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Half-duplex selection"] + pub const fn hdsel(&self) -> super::vals::Hdsel { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Hdsel(val as u8) + } + #[doc = "Half-duplex selection"] + pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "DMA enable receiver"] + pub const fn dmar(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "DMA enable receiver"] + pub fn set_dmar(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "DMA enable transmitter"] + pub const fn dmat(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "DMA enable transmitter"] + pub fn set_dmat(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for Cr3 { + fn default() -> Cr3 { + Cr3(0) + } + } + #[doc = "Baud rate register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Brr(pub u32); + impl Brr { + #[doc = "fraction of USARTDIV"] + pub const fn div_fraction(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "fraction of USARTDIV"] + pub fn set_div_fraction(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "mantissa of USARTDIV"] + pub const fn div_mantissa(&self) -> u16 { + let val = (self.0 >> 4usize) & 0x0fff; + val as u16 + } + #[doc = "mantissa of USARTDIV"] + pub fn set_div_mantissa(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize); + } + } + impl Default for Brr { + fn default() -> Brr { + Brr(0) + } + } + #[doc = "Data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dr(pub u32); + impl Dr { + #[doc = "Data value"] + pub const fn dr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x01ff; + val as u16 + } + #[doc = "Data value"] + pub fn set_dr(&mut self, val: u16) { + self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize); + } + } + impl Default for Dr { + fn default() -> Dr { + Dr(0) + } + } + #[doc = "Status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrUsart(pub u32); + impl SrUsart { + #[doc = "Parity error"] + pub const fn pe(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Parity error"] + pub fn set_pe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Framing error"] + pub const fn fe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Framing error"] + pub fn set_fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Noise error flag"] + pub const fn ne(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Noise error flag"] + pub fn set_ne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Overrun error"] + pub const fn ore(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Overrun error"] + pub fn set_ore(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE line detected"] + pub const fn idle(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE line detected"] + pub fn set_idle(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Read data register not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Read data register not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete"] + pub const fn tc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete"] + pub fn set_tc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Transmit data register empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Transmit data register empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "LIN break detection flag"] + pub const fn lbd(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection flag"] + pub fn set_lbd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "CTS flag"] + pub const fn cts(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "CTS flag"] + pub fn set_cts(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + } + impl Default for SrUsart { + fn default() -> SrUsart { + SrUsart(0) + } + } + #[doc = "Guard time and prescaler register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Gtpr(pub u32); + impl Gtpr { + #[doc = "Prescaler value"] + pub const fn psc(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Prescaler value"] + pub fn set_psc(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Guard time value"] + pub const fn gt(&self) -> u8 { + let val = (self.0 >> 8usize) & 0xff; + val as u8 + } + #[doc = "Guard time value"] + pub fn set_gt(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); + } + } + impl Default for Gtpr { + fn default() -> Gtpr { + Gtpr(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpol(pub u8); + impl Cpol { + #[doc = "Steady low value on CK pin outside transmission window"] + pub const LOW: Self = Self(0); + #[doc = "Steady high value on CK pin outside transmission window"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lbdl(pub u8); + impl Lbdl { + #[doc = "10-bit break detection"] + pub const LBDL10: Self = Self(0); + #[doc = "11-bit break detection"] + pub const LBDL11: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Wake(pub u8); + impl Wake { + #[doc = "USART wakeup on idle line"] + pub const IDLELINE: Self = Self(0); + #[doc = "USART wakeup on address mark"] + pub const ADDRESSMARK: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRST: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECOND: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Sbk(pub u8); + impl Sbk { + #[doc = "No break character is transmitted"] + pub const NOBREAK: Self = Self(0); + #[doc = "Break character transmitted"] + pub const BREAK: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rwu(pub u8); + impl Rwu { + #[doc = "Receiver in active mode"] + pub const ACTIVE: Self = Self(0); + #[doc = "Receiver in mute mode"] + pub const MUTE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ps(pub u8); + impl Ps { + #[doc = "Even parity"] + pub const EVEN: Self = Self(0); + #[doc = "Odd parity"] + pub const ODD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Irlp(pub u8); + impl Irlp { + #[doc = "Normal mode"] + pub const NORMAL: Self = Self(0); + #[doc = "Low-power mode"] + pub const LOWPOWER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Hdsel(pub u8); + impl Hdsel { + #[doc = "Half duplex mode is not selected"] + pub const FULLDUPLEX: Self = Self(0); + #[doc = "Half duplex mode is selected"] + pub const HALFDUPLEX: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Stop(pub u8); + impl Stop { + #[doc = "1 stop bit"] + pub const STOP1: Self = Self(0); + #[doc = "0.5 stop bits"] + pub const STOP0P5: Self = Self(0x01); + #[doc = "2 stop bits"] + pub const STOP2: Self = Self(0x02); + #[doc = "1.5 stop bits"] + pub const STOP1P5: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct M(pub u8); + impl M { + #[doc = "8 data bits"] + pub const M8: Self = Self(0); + #[doc = "9 data bits"] + pub const M9: Self = Self(0x01); + } } } pub mod spi_v2 { @@ -5868,6 +8466,104 @@ pub mod spi_v2 { use crate::generic::*; #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mstr(pub u8); + impl Mstr { + #[doc = "Slave configuration"] + pub const SLAVE: Self = Self(0); + #[doc = "Master configuration"] + pub const MASTER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidimode(pub u8); + impl Bidimode { + #[doc = "2-line unidirectional data mode selected"] + pub const UNIDIRECTIONAL: Self = Self(0); + #[doc = "1-line bidirectional data mode selected"] + pub const BIDIRECTIONAL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Crcnext(pub u8); + impl Crcnext { + #[doc = "Next transmit value is from Tx buffer"] + pub const TXBUFFER: Self = Self(0); + #[doc = "Next transmit value is from Tx CRC register"] + pub const CRC: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct LdmaRx(pub u8); + impl LdmaRx { + #[doc = "Number of data to transfer for receive is even"] + pub const EVEN: Self = Self(0); + #[doc = "Number of data to transfer for receive is odd"] + pub const ODD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lsbfirst(pub u8); + impl Lsbfirst { + #[doc = "Data is transmitted/received with the MSB first"] + pub const MSBFIRST: Self = Self(0); + #[doc = "Data is transmitted/received with the LSB first"] + pub const LSBFIRST: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frlvlr(pub u8); + impl Frlvlr { + #[doc = "Rx FIFO Empty"] + pub const EMPTY: Self = Self(0); + #[doc = "Rx 1/4 FIFO"] + pub const QUARTER: Self = Self(0x01); + #[doc = "Rx 1/2 FIFO"] + pub const HALF: Self = Self(0x02); + #[doc = "Rx FIFO full"] + pub const FULL: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ftlvlr(pub u8); + impl Ftlvlr { + #[doc = "Tx FIFO Empty"] + pub const EMPTY: Self = Self(0); + #[doc = "Tx 1/4 FIFO"] + pub const QUARTER: Self = Self(0x01); + #[doc = "Tx 1/2 FIFO"] + pub const HALF: Self = Self(0x02); + #[doc = "Tx FIFO full"] + pub const FULL: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpol(pub u8); + impl Cpol { + #[doc = "CK to 0 when idle"] + pub const IDLELOW: Self = Self(0); + #[doc = "CK to 1 when idle"] + pub const IDLEHIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidioe(pub u8); + impl Bidioe { + #[doc = "Output disabled (receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0); + #[doc = "Output enabled (transmit-only mode)"] + pub const OUTPUTENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frxth(pub u8); + impl Frxth { + #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"] + pub const HALF: Self = Self(0); + #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"] + pub const QUARTER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Br(pub u8); impl Br { #[doc = "f_PCLK / 2"] @@ -5889,60 +8585,6 @@ pub mod spi_v2 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lsbfirst(pub u8); - impl Lsbfirst { - #[doc = "Data is transmitted/received with the MSB first"] - pub const MSBFIRST: Self = Self(0); - #[doc = "Data is transmitted/received with the LSB first"] - pub const LSBFIRST: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct LdmaTx(pub u8); - impl LdmaTx { - #[doc = "Number of data to transfer for transmit is even"] - pub const EVEN: Self = Self(0); - #[doc = "Number of data to transfer for transmit is odd"] - pub const ODD: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frf(pub u8); - impl Frf { - #[doc = "SPI Motorola mode"] - pub const MOTOROLA: Self = Self(0); - #[doc = "SPI TI mode"] - pub const TI: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bidioe(pub u8); - impl Bidioe { - #[doc = "Output disabled (receive-only mode)"] - pub const OUTPUTDISABLED: Self = Self(0); - #[doc = "Output enabled (transmit-only mode)"] - pub const OUTPUTENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frer(pub u8); - impl Frer { - #[doc = "No frame format error"] - pub const NOERROR: Self = Self(0); - #[doc = "A frame format error occurred"] - pub const ERROR: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Crcnext(pub u8); - impl Crcnext { - #[doc = "Next transmit value is from Tx buffer"] - pub const TXBUFFER: Self = Self(0); - #[doc = "Next transmit value is from Tx CRC register"] - pub const CRC: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Ds(pub u8); impl Ds { #[doc = "4-bit"] @@ -5974,43 +8616,12 @@ pub mod spi_v2 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpha(pub u8); - impl Cpha { - #[doc = "The first clock transition is the first data capture edge"] - pub const FIRSTEDGE: Self = Self(0); - #[doc = "The second clock transition is the first data capture edge"] - pub const SECONDEDGE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frlvlr(pub u8); - impl Frlvlr { - #[doc = "Rx FIFO Empty"] - pub const EMPTY: Self = Self(0); - #[doc = "Rx 1/4 FIFO"] - pub const QUARTER: Self = Self(0x01); - #[doc = "Rx 1/2 FIFO"] - pub const HALF: Self = Self(0x02); - #[doc = "Rx FIFO full"] - pub const FULL: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bidimode(pub u8); - impl Bidimode { - #[doc = "2-line unidirectional data mode selected"] - pub const UNIDIRECTIONAL: Self = Self(0); - #[doc = "1-line bidirectional data mode selected"] - pub const BIDIRECTIONAL: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mstr(pub u8); - impl Mstr { - #[doc = "Slave configuration"] - pub const SLAVE: Self = Self(0); - #[doc = "Master configuration"] - pub const MASTER: Self = Self(0x01); + pub struct Rxonly(pub u8); + impl Rxonly { + #[doc = "Full duplex (Transmit and receive)"] + pub const FULLDUPLEX: Self = Self(0); + #[doc = "Output disabled (Receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] @@ -6023,56 +8634,215 @@ pub mod spi_v2 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Rxonly(pub u8); - impl Rxonly { - #[doc = "Full duplex (Transmit and receive)"] - pub const FULLDUPLEX: Self = Self(0); - #[doc = "Output disabled (Receive-only mode)"] - pub const OUTPUTDISABLED: Self = Self(0x01); + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRSTEDGE: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECONDEDGE: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ftlvlr(pub u8); - impl Ftlvlr { - #[doc = "Tx FIFO Empty"] - pub const EMPTY: Self = Self(0); - #[doc = "Tx 1/4 FIFO"] - pub const QUARTER: Self = Self(0x01); - #[doc = "Tx 1/2 FIFO"] - pub const HALF: Self = Self(0x02); - #[doc = "Tx FIFO full"] - pub const FULL: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frxth(pub u8); - impl Frxth { - #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"] - pub const HALF: Self = Self(0); - #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"] - pub const QUARTER: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct LdmaRx(pub u8); - impl LdmaRx { - #[doc = "Number of data to transfer for receive is even"] + pub struct LdmaTx(pub u8); + impl LdmaTx { + #[doc = "Number of data to transfer for transmit is even"] pub const EVEN: Self = Self(0); - #[doc = "Number of data to transfer for receive is odd"] + #[doc = "Number of data to transfer for transmit is odd"] pub const ODD: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpol(pub u8); - impl Cpol { - #[doc = "CK to 0 when idle"] - pub const IDLELOW: Self = Self(0); - #[doc = "CK to 1 when idle"] - pub const IDLEHIGH: Self = Self(0x01); + pub struct Frf(pub u8); + impl Frf { + #[doc = "SPI Motorola mode"] + pub const MOTOROLA: Self = Self(0); + #[doc = "SPI TI mode"] + pub const TI: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frer(pub u8); + impl Frer { + #[doc = "No frame format error"] + pub const NOERROR: Self = Self(0); + #[doc = "A frame format error occurred"] + pub const ERROR: Self = Self(0x01); } } pub mod regs { use crate::generic::*; + #[doc = "data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dr(pub u32); + impl Dr { + #[doc = "Data register"] + pub const fn dr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Data register"] + pub fn set_dr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Dr { + fn default() -> Dr { + Dr(0) + } + } + #[doc = "CRC polynomial register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Crcpr(pub u32); + impl Crcpr { + #[doc = "CRC polynomial register"] + pub const fn crcpoly(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "CRC polynomial register"] + pub fn set_crcpoly(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Crcpr { + fn default() -> Crcpr { + Crcpr(0) + } + } + #[doc = "RX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rxcrcr(pub u32); + impl Rxcrcr { + #[doc = "Rx CRC register"] + pub const fn rx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Rx CRC register"] + pub fn set_rx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Rxcrcr { + fn default() -> Rxcrcr { + Rxcrcr(0) + } + } + #[doc = "TX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Txcrcr(pub u32); + impl Txcrcr { + #[doc = "Tx CRC register"] + pub const fn tx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Tx CRC register"] + pub fn set_tx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Txcrcr { + fn default() -> Txcrcr { + Txcrcr(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Receive buffer not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Receive buffer not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Transmit buffer empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Transmit buffer empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "CRC error flag"] + pub const fn crcerr(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "CRC error flag"] + pub fn set_crcerr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Mode fault"] + pub const fn modf(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Mode fault"] + pub fn set_modf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Overrun flag"] + pub const fn ovr(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Overrun flag"] + pub fn set_ovr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Busy flag"] + pub const fn bsy(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Busy flag"] + pub fn set_bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Frame format error"] + pub const fn fre(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Frame format error"] + pub fn set_fre(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "FIFO reception level"] + pub const fn frlvl(&self) -> u8 { + let val = (self.0 >> 9usize) & 0x03; + val as u8 + } + #[doc = "FIFO reception level"] + pub fn set_frlvl(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 9usize)) | (((val as u32) & 0x03) << 9usize); + } + #[doc = "FIFO Transmission Level"] + pub const fn ftlvl(&self) -> u8 { + let val = (self.0 >> 11usize) & 0x03; + val as u8 + } + #[doc = "FIFO Transmission Level"] + pub fn set_ftlvl(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 11usize)) | (((val as u32) & 0x03) << 11usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } #[doc = "control register 1"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -6210,98 +8980,6 @@ pub mod spi_v2 { Cr1(0) } } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Sr(pub u32); - impl Sr { - #[doc = "Receive buffer not empty"] - pub const fn rxne(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Receive buffer not empty"] - pub fn set_rxne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Transmit buffer empty"] - pub const fn txe(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Transmit buffer empty"] - pub fn set_txe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "CRC error flag"] - pub const fn crcerr(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "CRC error flag"] - pub fn set_crcerr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Mode fault"] - pub const fn modf(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Mode fault"] - pub fn set_modf(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Overrun flag"] - pub const fn ovr(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Overrun flag"] - pub fn set_ovr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Busy flag"] - pub const fn bsy(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Busy flag"] - pub fn set_bsy(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Frame format error"] - pub const fn fre(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Frame format error"] - pub fn set_fre(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "FIFO reception level"] - pub const fn frlvl(&self) -> u8 { - let val = (self.0 >> 9usize) & 0x03; - val as u8 - } - #[doc = "FIFO reception level"] - pub fn set_frlvl(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 9usize)) | (((val as u32) & 0x03) << 9usize); - } - #[doc = "FIFO Transmission Level"] - pub const fn ftlvl(&self) -> u8 { - let val = (self.0 >> 11usize) & 0x03; - val as u8 - } - #[doc = "FIFO Transmission Level"] - pub fn set_ftlvl(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 11usize)) | (((val as u32) & 0x03) << 11usize); - } - } - impl Default for Sr { - fn default() -> Sr { - Sr(0) - } - } #[doc = "control register 2"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -6421,2683 +9099,5 @@ pub mod spi_v2 { Cr2(0) } } - #[doc = "data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dr(pub u32); - impl Dr { - #[doc = "Data register"] - pub const fn dr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Data register"] - pub fn set_dr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Dr { - fn default() -> Dr { - Dr(0) - } - } - #[doc = "CRC polynomial register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Crcpr(pub u32); - impl Crcpr { - #[doc = "CRC polynomial register"] - pub const fn crcpoly(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "CRC polynomial register"] - pub fn set_crcpoly(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Crcpr { - fn default() -> Crcpr { - Crcpr(0) - } - } - #[doc = "RX CRC register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Rxcrcr(pub u32); - impl Rxcrcr { - #[doc = "Rx CRC register"] - pub const fn rx_crc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Rx CRC register"] - pub fn set_rx_crc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Rxcrcr { - fn default() -> Rxcrcr { - Rxcrcr(0) - } - } - #[doc = "TX CRC register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Txcrcr(pub u32); - impl Txcrcr { - #[doc = "Tx CRC register"] - pub const fn tx_crc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Tx CRC register"] - pub fn set_tx_crc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Txcrcr { - fn default() -> Txcrcr { - Txcrcr(0) - } - } - } -} -pub mod dma_v2 { - use crate::generic::*; - #[doc = "DMA controller"] - #[derive(Copy, Clone)] - pub struct Dma(pub *mut u8); - unsafe impl Send for Dma {} - unsafe impl Sync for Dma {} - impl Dma { - #[doc = "low interrupt status register"] - pub fn isr(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) } - } - #[doc = "low interrupt flag clear register"] - pub fn ifcr(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } - } - #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"] - pub fn st(self, n: usize) -> St { - assert!(n < 8usize); - unsafe { St(self.0.add(16usize + n * 24usize)) } - } - } - #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"] - #[derive(Copy, Clone)] - pub struct St(pub *mut u8); - unsafe impl Send for St {} - unsafe impl Sync for St {} - impl St { - #[doc = "stream x configuration register"] - pub fn cr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "stream x number of data register"] - pub fn ndtr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "stream x peripheral address register"] - pub fn par(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "stream x memory 0 address register"] - pub fn m0ar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "stream x memory 1 address register"] - pub fn m1ar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "stream x FIFO control register"] - pub fn fcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pincos(pub u8); - impl Pincos { - #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] - pub const PSIZE: Self = Self(0); - #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] - pub const FIXED4: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Fs(pub u8); - impl Fs { - #[doc = "0 < fifo_level < 1/4"] - pub const QUARTER1: Self = Self(0); - #[doc = "1/4 <= fifo_level < 1/2"] - pub const QUARTER2: Self = Self(0x01); - #[doc = "1/2 <= fifo_level < 3/4"] - pub const QUARTER3: Self = Self(0x02); - #[doc = "3/4 <= fifo_level < full"] - pub const QUARTER4: Self = Self(0x03); - #[doc = "FIFO is empty"] - pub const EMPTY: Self = Self(0x04); - #[doc = "FIFO is full"] - pub const FULL: Self = Self(0x05); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Burst(pub u8); - impl Burst { - #[doc = "Single transfer"] - pub const SINGLE: Self = Self(0); - #[doc = "Incremental burst of 4 beats"] - pub const INCR4: Self = Self(0x01); - #[doc = "Incremental burst of 8 beats"] - pub const INCR8: Self = Self(0x02); - #[doc = "Incremental burst of 16 beats"] - pub const INCR16: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dbm(pub u8); - impl Dbm { - #[doc = "No buffer switching at the end of transfer"] - pub const DISABLED: Self = Self(0); - #[doc = "Memory target switched at the end of the DMA transfer"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Inc(pub u8); - impl Inc { - #[doc = "Address pointer is fixed"] - pub const FIXED: Self = Self(0); - #[doc = "Address pointer is incremented after each data transfer"] - pub const INCREMENTED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dir(pub u8); - impl Dir { - #[doc = "Peripheral-to-memory"] - pub const PERIPHERALTOMEMORY: Self = Self(0); - #[doc = "Memory-to-peripheral"] - pub const MEMORYTOPERIPHERAL: Self = Self(0x01); - #[doc = "Memory-to-memory"] - pub const MEMORYTOMEMORY: Self = Self(0x02); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pfctrl(pub u8); - impl Pfctrl { - #[doc = "The DMA is the flow controller"] - pub const DMA: Self = Self(0); - #[doc = "The peripheral is the flow controller"] - pub const PERIPHERAL: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pl(pub u8); - impl Pl { - #[doc = "Low"] - pub const LOW: Self = Self(0); - #[doc = "Medium"] - pub const MEDIUM: Self = Self(0x01); - #[doc = "High"] - pub const HIGH: Self = Self(0x02); - #[doc = "Very high"] - pub const VERYHIGH: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Circ(pub u8); - impl Circ { - #[doc = "Circular mode disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Circular mode enabled"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Fth(pub u8); - impl Fth { - #[doc = "1/4 full FIFO"] - pub const QUARTER: Self = Self(0); - #[doc = "1/2 full FIFO"] - pub const HALF: Self = Self(0x01); - #[doc = "3/4 full FIFO"] - pub const THREEQUARTERS: Self = Self(0x02); - #[doc = "Full FIFO"] - pub const FULL: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ct(pub u8); - impl Ct { - #[doc = "The current target memory is Memory 0"] - pub const MEMORY0: Self = Self(0); - #[doc = "The current target memory is Memory 1"] - pub const MEMORY1: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dmdis(pub u8); - impl Dmdis { - #[doc = "Direct mode is enabled"] - pub const ENABLED: Self = Self(0); - #[doc = "Direct mode is disabled"] - pub const DISABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Size(pub u8); - impl Size { - #[doc = "Byte (8-bit)"] - pub const BITS8: Self = Self(0); - #[doc = "Half-word (16-bit)"] - pub const BITS16: Self = Self(0x01); - #[doc = "Word (32-bit)"] - pub const BITS32: Self = Self(0x02); - } - } - pub mod regs { - use crate::generic::*; - #[doc = "low interrupt flag clear register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ifcr(pub u32); - impl Ifcr { - #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"] - pub fn cfeif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"] - pub fn set_cfeif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"] - pub fn cdmeif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"] - pub fn set_cdmeif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"] - pub fn cteif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"] - pub fn set_cteif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"] - pub fn chtif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"] - pub fn set_chtif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"] - pub fn ctcif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"] - pub fn set_ctcif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Ifcr { - fn default() -> Ifcr { - Ifcr(0) - } - } - #[doc = "stream x FIFO control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Fcr(pub u32); - impl Fcr { - #[doc = "FIFO threshold selection"] - pub const fn fth(&self) -> super::vals::Fth { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Fth(val as u8) - } - #[doc = "FIFO threshold selection"] - pub fn set_fth(&mut self, val: super::vals::Fth) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize); - } - #[doc = "Direct mode disable"] - pub const fn dmdis(&self) -> super::vals::Dmdis { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Dmdis(val as u8) - } - #[doc = "Direct mode disable"] - pub fn set_dmdis(&mut self, val: super::vals::Dmdis) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "FIFO status"] - pub const fn fs(&self) -> super::vals::Fs { - let val = (self.0 >> 3usize) & 0x07; - super::vals::Fs(val as u8) - } - #[doc = "FIFO status"] - pub fn set_fs(&mut self, val: super::vals::Fs) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); - } - #[doc = "FIFO error interrupt enable"] - pub const fn feie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "FIFO error interrupt enable"] - pub fn set_feie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - } - impl Default for Fcr { - fn default() -> Fcr { - Fcr(0) - } - } - #[doc = "stream x number of data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ndtr(pub u32); - impl Ndtr { - #[doc = "Number of data items to transfer"] - pub const fn ndt(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Number of data items to transfer"] - pub fn set_ndt(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Ndtr { - fn default() -> Ndtr { - Ndtr(0) - } - } - #[doc = "low interrupt status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Isr(pub u32); - impl Isr { - #[doc = "Stream x FIFO error interrupt flag (x=3..0)"] - pub fn feif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x FIFO error interrupt flag (x=3..0)"] - pub fn set_feif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x direct mode error interrupt flag (x=3..0)"] - pub fn dmeif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x direct mode error interrupt flag (x=3..0)"] - pub fn set_dmeif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x transfer error interrupt flag (x=3..0)"] - pub fn teif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x transfer error interrupt flag (x=3..0)"] - pub fn set_teif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x half transfer interrupt flag (x=3..0)"] - pub fn htif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x half transfer interrupt flag (x=3..0)"] - pub fn set_htif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"] - pub fn tcif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"] - pub fn set_tcif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Isr { - fn default() -> Isr { - Isr(0) - } - } - #[doc = "stream x configuration register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr(pub u32); - impl Cr { - #[doc = "Stream enable / flag stream ready when read low"] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Stream enable / flag stream ready when read low"] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Direct mode error interrupt enable"] - pub const fn dmeie(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Direct mode error interrupt enable"] - pub fn set_dmeie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Transfer error interrupt enable"] - pub const fn teie(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Transfer error interrupt enable"] - pub fn set_teie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Half transfer interrupt enable"] - pub const fn htie(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Half transfer interrupt enable"] - pub fn set_htie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Transfer complete interrupt enable"] - pub const fn tcie(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "Transfer complete interrupt enable"] - pub fn set_tcie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Peripheral flow controller"] - pub const fn pfctrl(&self) -> super::vals::Pfctrl { - let val = (self.0 >> 5usize) & 0x01; - super::vals::Pfctrl(val as u8) - } - #[doc = "Peripheral flow controller"] - pub fn set_pfctrl(&mut self, val: super::vals::Pfctrl) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); - } - #[doc = "Data transfer direction"] - pub const fn dir(&self) -> super::vals::Dir { - let val = (self.0 >> 6usize) & 0x03; - super::vals::Dir(val as u8) - } - #[doc = "Data transfer direction"] - pub fn set_dir(&mut self, val: super::vals::Dir) { - self.0 = (self.0 & !(0x03 << 6usize)) | (((val.0 as u32) & 0x03) << 6usize); - } - #[doc = "Circular mode"] - pub const fn circ(&self) -> super::vals::Circ { - let val = (self.0 >> 8usize) & 0x01; - super::vals::Circ(val as u8) - } - #[doc = "Circular mode"] - pub fn set_circ(&mut self, val: super::vals::Circ) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize); - } - #[doc = "Peripheral increment mode"] - pub const fn pinc(&self) -> super::vals::Inc { - let val = (self.0 >> 9usize) & 0x01; - super::vals::Inc(val as u8) - } - #[doc = "Peripheral increment mode"] - pub fn set_pinc(&mut self, val: super::vals::Inc) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); - } - #[doc = "Memory increment mode"] - pub const fn minc(&self) -> super::vals::Inc { - let val = (self.0 >> 10usize) & 0x01; - super::vals::Inc(val as u8) - } - #[doc = "Memory increment mode"] - pub fn set_minc(&mut self, val: super::vals::Inc) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); - } - #[doc = "Peripheral data size"] - pub const fn psize(&self) -> super::vals::Size { - let val = (self.0 >> 11usize) & 0x03; - super::vals::Size(val as u8) - } - #[doc = "Peripheral data size"] - pub fn set_psize(&mut self, val: super::vals::Size) { - self.0 = (self.0 & !(0x03 << 11usize)) | (((val.0 as u32) & 0x03) << 11usize); - } - #[doc = "Memory data size"] - pub const fn msize(&self) -> super::vals::Size { - let val = (self.0 >> 13usize) & 0x03; - super::vals::Size(val as u8) - } - #[doc = "Memory data size"] - pub fn set_msize(&mut self, val: super::vals::Size) { - self.0 = (self.0 & !(0x03 << 13usize)) | (((val.0 as u32) & 0x03) << 13usize); - } - #[doc = "Peripheral increment offset size"] - pub const fn pincos(&self) -> super::vals::Pincos { - let val = (self.0 >> 15usize) & 0x01; - super::vals::Pincos(val as u8) - } - #[doc = "Peripheral increment offset size"] - pub fn set_pincos(&mut self, val: super::vals::Pincos) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); - } - #[doc = "Priority level"] - pub const fn pl(&self) -> super::vals::Pl { - let val = (self.0 >> 16usize) & 0x03; - super::vals::Pl(val as u8) - } - #[doc = "Priority level"] - pub fn set_pl(&mut self, val: super::vals::Pl) { - self.0 = (self.0 & !(0x03 << 16usize)) | (((val.0 as u32) & 0x03) << 16usize); - } - #[doc = "Double buffer mode"] - pub const fn dbm(&self) -> super::vals::Dbm { - let val = (self.0 >> 18usize) & 0x01; - super::vals::Dbm(val as u8) - } - #[doc = "Double buffer mode"] - pub fn set_dbm(&mut self, val: super::vals::Dbm) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize); - } - #[doc = "Current target (only in double buffer mode)"] - pub const fn ct(&self) -> super::vals::Ct { - let val = (self.0 >> 19usize) & 0x01; - super::vals::Ct(val as u8) - } - #[doc = "Current target (only in double buffer mode)"] - pub fn set_ct(&mut self, val: super::vals::Ct) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize); - } - #[doc = "Peripheral burst transfer configuration"] - pub const fn pburst(&self) -> super::vals::Burst { - let val = (self.0 >> 21usize) & 0x03; - super::vals::Burst(val as u8) - } - #[doc = "Peripheral burst transfer configuration"] - pub fn set_pburst(&mut self, val: super::vals::Burst) { - self.0 = (self.0 & !(0x03 << 21usize)) | (((val.0 as u32) & 0x03) << 21usize); - } - #[doc = "Memory burst transfer configuration"] - pub const fn mburst(&self) -> super::vals::Burst { - let val = (self.0 >> 23usize) & 0x03; - super::vals::Burst(val as u8) - } - #[doc = "Memory burst transfer configuration"] - pub fn set_mburst(&mut self, val: super::vals::Burst) { - self.0 = (self.0 & !(0x03 << 23usize)) | (((val.0 as u32) & 0x03) << 23usize); - } - #[doc = "Channel selection"] - pub const fn chsel(&self) -> u8 { - let val = (self.0 >> 25usize) & 0x0f; - val as u8 - } - #[doc = "Channel selection"] - pub fn set_chsel(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 25usize)) | (((val as u32) & 0x0f) << 25usize); - } - } - impl Default for Cr { - fn default() -> Cr { - Cr(0) - } - } - } -} -pub mod timer_v1 { - use crate::generic::*; - #[doc = "General purpose 32-bit timer"] - #[derive(Copy, Clone)] - pub struct TimGp32(pub *mut u8); - unsafe impl Send for TimGp32 {} - unsafe impl Sync for TimGp32 {} - impl TimGp32 { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "slave mode control register"] - pub fn smcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "DMA/Interrupt enable register"] - pub fn dier(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "event generation register"] - pub fn egr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "capture/compare mode register 1 (input mode)"] - pub fn ccmr_input(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare mode register 1 (output mode)"] - pub fn ccmr_output(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare enable register"] - pub fn ccer(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(32usize)) } - } - #[doc = "counter"] - pub fn cnt(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - #[doc = "prescaler"] - pub fn psc(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(40usize)) } - } - #[doc = "auto-reload register"] - pub fn arr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(44usize)) } - } - #[doc = "capture/compare register"] - pub fn ccr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } - } - #[doc = "DMA control register"] - pub fn dcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(72usize)) } - } - #[doc = "DMA address for full transfer"] - pub fn dmar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(76usize)) } - } - } - #[doc = "Advanced-timers"] - #[derive(Copy, Clone)] - pub struct TimAdv(pub *mut u8); - unsafe impl Send for TimAdv {} - unsafe impl Sync for TimAdv {} - impl TimAdv { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "slave mode control register"] - pub fn smcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "DMA/Interrupt enable register"] - pub fn dier(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "event generation register"] - pub fn egr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "capture/compare mode register 1 (input mode)"] - pub fn ccmr_input(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare mode register 1 (output mode)"] - pub fn ccmr_output(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare enable register"] - pub fn ccer(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(32usize)) } - } - #[doc = "counter"] - pub fn cnt(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - #[doc = "prescaler"] - pub fn psc(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(40usize)) } - } - #[doc = "auto-reload register"] - pub fn arr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(44usize)) } - } - #[doc = "repetition counter register"] - pub fn rcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(48usize)) } - } - #[doc = "capture/compare register"] - pub fn ccr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } - } - #[doc = "break and dead-time register"] - pub fn bdtr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(68usize)) } - } - #[doc = "DMA control register"] - pub fn dcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(72usize)) } - } - #[doc = "DMA address for full transfer"] - pub fn dmar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(76usize)) } - } - } - #[doc = "General purpose 16-bit timer"] - #[derive(Copy, Clone)] - pub struct TimGp16(pub *mut u8); - unsafe impl Send for TimGp16 {} - unsafe impl Sync for TimGp16 {} - impl TimGp16 { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "slave mode control register"] - pub fn smcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "DMA/Interrupt enable register"] - pub fn dier(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "event generation register"] - pub fn egr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "capture/compare mode register 1 (input mode)"] - pub fn ccmr_input(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare mode register 1 (output mode)"] - pub fn ccmr_output(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare enable register"] - pub fn ccer(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(32usize)) } - } - #[doc = "counter"] - pub fn cnt(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - #[doc = "prescaler"] - pub fn psc(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(40usize)) } - } - #[doc = "auto-reload register"] - pub fn arr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(44usize)) } - } - #[doc = "capture/compare register"] - pub fn ccr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } - } - #[doc = "DMA control register"] - pub fn dcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(72usize)) } - } - #[doc = "DMA address for full transfer"] - pub fn dmar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(76usize)) } - } - } - #[doc = "Basic timer"] - #[derive(Copy, Clone)] - pub struct TimBasic(pub *mut u8); - unsafe impl Send for TimBasic {} - unsafe impl Sync for TimBasic {} - impl TimBasic { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "DMA/Interrupt enable register"] - pub fn dier(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "event generation register"] - pub fn egr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "counter"] - pub fn cnt(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - #[doc = "prescaler"] - pub fn psc(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(40usize)) } - } - #[doc = "auto-reload register"] - pub fn arr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(44usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "capture/compare mode register 1 (input mode)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcmrInput(pub u32); - impl CcmrInput { - #[doc = "Capture/Compare 1 selection"] - pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs { - assert!(n < 2usize); - let offs = 0usize + n * 8usize; - let val = (self.0 >> offs) & 0x03; - super::vals::CcmrInputCcs(val as u8) - } - #[doc = "Capture/Compare 1 selection"] - pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) { - assert!(n < 2usize); - let offs = 0usize + n * 8usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - #[doc = "Input capture 1 prescaler"] - pub fn icpsc(&self, n: usize) -> u8 { - assert!(n < 2usize); - let offs = 2usize + n * 8usize; - let val = (self.0 >> offs) & 0x03; - val as u8 - } - #[doc = "Input capture 1 prescaler"] - pub fn set_icpsc(&mut self, n: usize, val: u8) { - assert!(n < 2usize); - let offs = 2usize + n * 8usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs); - } - #[doc = "Input capture 1 filter"] - pub fn icf(&self, n: usize) -> super::vals::Icf { - assert!(n < 2usize); - let offs = 4usize + n * 8usize; - let val = (self.0 >> offs) & 0x0f; - super::vals::Icf(val as u8) - } - #[doc = "Input capture 1 filter"] - pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) { - assert!(n < 2usize); - let offs = 4usize + n * 8usize; - self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); - } - } - impl Default for CcmrInput { - fn default() -> CcmrInput { - CcmrInput(0) - } - } - #[doc = "capture/compare mode register 2 (output mode)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcmrOutput(pub u32); - impl CcmrOutput { - #[doc = "Capture/Compare 3 selection"] - pub fn ccs(&self, n: usize) -> super::vals::CcmrOutputCcs { - assert!(n < 2usize); - let offs = 0usize + n * 8usize; - let val = (self.0 >> offs) & 0x03; - super::vals::CcmrOutputCcs(val as u8) - } - #[doc = "Capture/Compare 3 selection"] - pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrOutputCcs) { - assert!(n < 2usize); - let offs = 0usize + n * 8usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - #[doc = "Output compare 3 fast enable"] - pub fn ocfe(&self, n: usize) -> bool { - assert!(n < 2usize); - let offs = 2usize + n * 8usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Output compare 3 fast enable"] - pub fn set_ocfe(&mut self, n: usize, val: bool) { - assert!(n < 2usize); - let offs = 2usize + n * 8usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Output compare 3 preload enable"] - pub fn ocpe(&self, n: usize) -> super::vals::Ocpe { - assert!(n < 2usize); - let offs = 3usize + n * 8usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Ocpe(val as u8) - } - #[doc = "Output compare 3 preload enable"] - pub fn set_ocpe(&mut self, n: usize, val: super::vals::Ocpe) { - assert!(n < 2usize); - let offs = 3usize + n * 8usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - #[doc = "Output compare 3 mode"] - pub fn ocm(&self, n: usize) -> super::vals::Ocm { - assert!(n < 2usize); - let offs = 4usize + n * 8usize; - let val = (self.0 >> offs) & 0x07; - super::vals::Ocm(val as u8) - } - #[doc = "Output compare 3 mode"] - pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) { - assert!(n < 2usize); - let offs = 4usize + n * 8usize; - self.0 = (self.0 & !(0x07 << offs)) | (((val.0 as u32) & 0x07) << offs); - } - #[doc = "Output compare 3 clear enable"] - pub fn occe(&self, n: usize) -> bool { - assert!(n < 2usize); - let offs = 7usize + n * 8usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Output compare 3 clear enable"] - pub fn set_occe(&mut self, n: usize, val: bool) { - assert!(n < 2usize); - let offs = 7usize + n * 8usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for CcmrOutput { - fn default() -> CcmrOutput { - CcmrOutput(0) - } - } - #[doc = "event generation register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct EgrGp(pub u32); - impl EgrGp { - #[doc = "Update generation"] - pub const fn ug(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update generation"] - pub fn set_ug(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare 1 generation"] - pub fn ccg(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/compare 1 generation"] - pub fn set_ccg(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare control update generation"] - pub const fn comg(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Capture/Compare control update generation"] - pub fn set_comg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger generation"] - pub const fn tg(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger generation"] - pub fn set_tg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break generation"] - pub const fn bg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break generation"] - pub fn set_bg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - } - impl Default for EgrGp { - fn default() -> EgrGp { - EgrGp(0) - } - } - #[doc = "counter"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cnt16(pub u32); - impl Cnt16 { - #[doc = "counter value"] - pub const fn cnt(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "counter value"] - pub fn set_cnt(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Cnt16 { - fn default() -> Cnt16 { - Cnt16(0) - } - } - #[doc = "control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2Adv(pub u32); - impl Cr2Adv { - #[doc = "Capture/compare preloaded control"] - pub const fn ccpc(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Capture/compare preloaded control"] - pub fn set_ccpc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare control update selection"] - pub const fn ccus(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Capture/compare control update selection"] - pub fn set_ccus(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Capture/compare DMA selection"] - pub const fn ccds(&self) -> super::vals::Ccds { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Ccds(val as u8) - } - #[doc = "Capture/compare DMA selection"] - pub fn set_ccds(&mut self, val: super::vals::Ccds) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Master mode selection"] - pub const fn mms(&self) -> super::vals::Mms { - let val = (self.0 >> 4usize) & 0x07; - super::vals::Mms(val as u8) - } - #[doc = "Master mode selection"] - pub fn set_mms(&mut self, val: super::vals::Mms) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); - } - #[doc = "TI1 selection"] - pub const fn ti1s(&self) -> super::vals::Tis { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Tis(val as u8) - } - #[doc = "TI1 selection"] - pub fn set_ti1s(&mut self, val: super::vals::Tis) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Output Idle state 1"] - pub fn ois(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 8usize + n * 2usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Output Idle state 1"] - pub fn set_ois(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 8usize + n * 2usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Output Idle state 1"] - pub const fn ois1n(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Output Idle state 1"] - pub fn set_ois1n(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Output Idle state 2"] - pub const fn ois2n(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "Output Idle state 2"] - pub fn set_ois2n(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "Output Idle state 3"] - pub const fn ois3n(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "Output Idle state 3"] - pub fn set_ois3n(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - } - impl Default for Cr2Adv { - fn default() -> Cr2Adv { - Cr2Adv(0) - } - } - #[doc = "auto-reload register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Arr32(pub u32); - impl Arr32 { - #[doc = "Auto-reload value"] - pub const fn arr(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Auto-reload value"] - pub fn set_arr(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Arr32 { - fn default() -> Arr32 { - Arr32(0) - } - } - #[doc = "DMA/Interrupt enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct DierGp(pub u32); - impl DierGp { - #[doc = "Update interrupt enable"] - pub const fn uie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt enable"] - pub fn set_uie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/Compare 1 interrupt enable"] - pub fn ccie(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 interrupt enable"] - pub fn set_ccie(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Trigger interrupt enable"] - pub const fn tie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger interrupt enable"] - pub fn set_tie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Update DMA request enable"] - pub const fn ude(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Update DMA request enable"] - pub fn set_ude(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Capture/Compare 1 DMA request enable"] - pub fn ccde(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 DMA request enable"] - pub fn set_ccde(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Trigger DMA request enable"] - pub const fn tde(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Trigger DMA request enable"] - pub fn set_tde(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - } - impl Default for DierGp { - fn default() -> DierGp { - DierGp(0) - } - } - #[doc = "control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2Gp(pub u32); - impl Cr2Gp { - #[doc = "Capture/compare DMA selection"] - pub const fn ccds(&self) -> super::vals::Ccds { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Ccds(val as u8) - } - #[doc = "Capture/compare DMA selection"] - pub fn set_ccds(&mut self, val: super::vals::Ccds) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Master mode selection"] - pub const fn mms(&self) -> super::vals::Mms { - let val = (self.0 >> 4usize) & 0x07; - super::vals::Mms(val as u8) - } - #[doc = "Master mode selection"] - pub fn set_mms(&mut self, val: super::vals::Mms) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); - } - #[doc = "TI1 selection"] - pub const fn ti1s(&self) -> super::vals::Tis { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Tis(val as u8) - } - #[doc = "TI1 selection"] - pub fn set_ti1s(&mut self, val: super::vals::Tis) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - } - impl Default for Cr2Gp { - fn default() -> Cr2Gp { - Cr2Gp(0) - } - } - #[doc = "capture/compare register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ccr16(pub u32); - impl Ccr16 { - #[doc = "Capture/Compare 1 value"] - pub const fn ccr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Capture/Compare 1 value"] - pub fn set_ccr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Ccr16 { - fn default() -> Ccr16 { - Ccr16(0) - } - } - #[doc = "capture/compare enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcerAdv(pub u32); - impl CcerAdv { - #[doc = "Capture/Compare 1 output enable"] - pub fn cce(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output enable"] - pub fn set_cce(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn ccp(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn set_ccp(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 complementary output enable"] - pub fn ccne(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 2usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 complementary output enable"] - pub fn set_ccne(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 2usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn ccnp(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 3usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn set_ccnp(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 3usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for CcerAdv { - fn default() -> CcerAdv { - CcerAdv(0) - } - } - #[doc = "DMA/Interrupt enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct DierBasic(pub u32); - impl DierBasic { - #[doc = "Update interrupt enable"] - pub const fn uie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt enable"] - pub fn set_uie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Update DMA request enable"] - pub const fn ude(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Update DMA request enable"] - pub fn set_ude(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for DierBasic { - fn default() -> DierBasic { - DierBasic(0) - } - } - #[doc = "event generation register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct EgrAdv(pub u32); - impl EgrAdv { - #[doc = "Update generation"] - pub const fn ug(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update generation"] - pub fn set_ug(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare 1 generation"] - pub fn ccg(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/compare 1 generation"] - pub fn set_ccg(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare control update generation"] - pub const fn comg(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Capture/Compare control update generation"] - pub fn set_comg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger generation"] - pub const fn tg(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger generation"] - pub fn set_tg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break generation"] - pub const fn bg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break generation"] - pub fn set_bg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - } - impl Default for EgrAdv { - fn default() -> EgrAdv { - EgrAdv(0) - } - } - #[doc = "control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2Basic(pub u32); - impl Cr2Basic { - #[doc = "Master mode selection"] - pub const fn mms(&self) -> super::vals::Mms { - let val = (self.0 >> 4usize) & 0x07; - super::vals::Mms(val as u8) - } - #[doc = "Master mode selection"] - pub fn set_mms(&mut self, val: super::vals::Mms) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); - } - } - impl Default for Cr2Basic { - fn default() -> Cr2Basic { - Cr2Basic(0) - } - } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct SrGp(pub u32); - impl SrGp { - #[doc = "Update interrupt flag"] - pub const fn uif(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt flag"] - pub fn set_uif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare 1 interrupt flag"] - pub fn ccif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/compare 1 interrupt flag"] - pub fn set_ccif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "COM interrupt flag"] - pub const fn comif(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "COM interrupt flag"] - pub fn set_comif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger interrupt flag"] - pub const fn tif(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger interrupt flag"] - pub fn set_tif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break interrupt flag"] - pub const fn bif(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break interrupt flag"] - pub fn set_bif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Capture/Compare 1 overcapture flag"] - pub fn ccof(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 overcapture flag"] - pub fn set_ccof(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for SrGp { - fn default() -> SrGp { - SrGp(0) - } - } - #[doc = "event generation register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct EgrBasic(pub u32); - impl EgrBasic { - #[doc = "Update generation"] - pub const fn ug(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update generation"] - pub fn set_ug(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for EgrBasic { - fn default() -> EgrBasic { - EgrBasic(0) - } - } - #[doc = "control register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1Gp(pub u32); - impl Cr1Gp { - #[doc = "Counter enable"] - pub const fn cen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Counter enable"] - pub fn set_cen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Update disable"] - pub const fn udis(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Update disable"] - pub fn set_udis(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Update request source"] - pub const fn urs(&self) -> super::vals::Urs { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Urs(val as u8) - } - #[doc = "Update request source"] - pub fn set_urs(&mut self, val: super::vals::Urs) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "One-pulse mode"] - pub const fn opm(&self) -> super::vals::Opm { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Opm(val as u8) - } - #[doc = "One-pulse mode"] - pub fn set_opm(&mut self, val: super::vals::Opm) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Direction"] - pub const fn dir(&self) -> super::vals::Dir { - let val = (self.0 >> 4usize) & 0x01; - super::vals::Dir(val as u8) - } - #[doc = "Direction"] - pub fn set_dir(&mut self, val: super::vals::Dir) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); - } - #[doc = "Center-aligned mode selection"] - pub const fn cms(&self) -> super::vals::Cms { - let val = (self.0 >> 5usize) & 0x03; - super::vals::Cms(val as u8) - } - #[doc = "Center-aligned mode selection"] - pub fn set_cms(&mut self, val: super::vals::Cms) { - self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize); - } - #[doc = "Auto-reload preload enable"] - pub const fn arpe(&self) -> super::vals::Arpe { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Arpe(val as u8) - } - #[doc = "Auto-reload preload enable"] - pub fn set_arpe(&mut self, val: super::vals::Arpe) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Clock division"] - pub const fn ckd(&self) -> super::vals::Ckd { - let val = (self.0 >> 8usize) & 0x03; - super::vals::Ckd(val as u8) - } - #[doc = "Clock division"] - pub fn set_ckd(&mut self, val: super::vals::Ckd) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); - } - } - impl Default for Cr1Gp { - fn default() -> Cr1Gp { - Cr1Gp(0) - } - } - #[doc = "prescaler"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Psc(pub u32); - impl Psc { - #[doc = "Prescaler value"] - pub const fn psc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Prescaler value"] - pub fn set_psc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Psc { - fn default() -> Psc { - Psc(0) - } - } - #[doc = "capture/compare enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcerGp(pub u32); - impl CcerGp { - #[doc = "Capture/Compare 1 output enable"] - pub fn cce(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output enable"] - pub fn set_cce(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn ccp(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn set_ccp(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn ccnp(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 3usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn set_ccnp(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 3usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for CcerGp { - fn default() -> CcerGp { - CcerGp(0) - } - } - #[doc = "DMA/Interrupt enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct DierAdv(pub u32); - impl DierAdv { - #[doc = "Update interrupt enable"] - pub const fn uie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt enable"] - pub fn set_uie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/Compare 1 interrupt enable"] - pub fn ccie(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 interrupt enable"] - pub fn set_ccie(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "COM interrupt enable"] - pub const fn comie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "COM interrupt enable"] - pub fn set_comie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger interrupt enable"] - pub const fn tie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger interrupt enable"] - pub fn set_tie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break interrupt enable"] - pub const fn bie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break interrupt enable"] - pub fn set_bie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Update DMA request enable"] - pub const fn ude(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Update DMA request enable"] - pub fn set_ude(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Capture/Compare 1 DMA request enable"] - pub fn ccde(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 DMA request enable"] - pub fn set_ccde(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "COM DMA request enable"] - pub const fn comde(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "COM DMA request enable"] - pub fn set_comde(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[doc = "Trigger DMA request enable"] - pub const fn tde(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Trigger DMA request enable"] - pub fn set_tde(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - } - impl Default for DierAdv { - fn default() -> DierAdv { - DierAdv(0) - } - } - #[doc = "slave mode control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Smcr(pub u32); - impl Smcr { - #[doc = "Slave mode selection"] - pub const fn sms(&self) -> super::vals::Sms { - let val = (self.0 >> 0usize) & 0x07; - super::vals::Sms(val as u8) - } - #[doc = "Slave mode selection"] - pub fn set_sms(&mut self, val: super::vals::Sms) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize); - } - #[doc = "Trigger selection"] - pub const fn ts(&self) -> super::vals::Ts { - let val = (self.0 >> 4usize) & 0x07; - super::vals::Ts(val as u8) - } - #[doc = "Trigger selection"] - pub fn set_ts(&mut self, val: super::vals::Ts) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); - } - #[doc = "Master/Slave mode"] - pub const fn msm(&self) -> super::vals::Msm { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Msm(val as u8) - } - #[doc = "Master/Slave mode"] - pub fn set_msm(&mut self, val: super::vals::Msm) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "External trigger filter"] - pub const fn etf(&self) -> super::vals::Etf { - let val = (self.0 >> 8usize) & 0x0f; - super::vals::Etf(val as u8) - } - #[doc = "External trigger filter"] - pub fn set_etf(&mut self, val: super::vals::Etf) { - self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); - } - #[doc = "External trigger prescaler"] - pub const fn etps(&self) -> super::vals::Etps { - let val = (self.0 >> 12usize) & 0x03; - super::vals::Etps(val as u8) - } - #[doc = "External trigger prescaler"] - pub fn set_etps(&mut self, val: super::vals::Etps) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); - } - #[doc = "External clock enable"] - pub const fn ece(&self) -> super::vals::Ece { - let val = (self.0 >> 14usize) & 0x01; - super::vals::Ece(val as u8) - } - #[doc = "External clock enable"] - pub fn set_ece(&mut self, val: super::vals::Ece) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); - } - #[doc = "External trigger polarity"] - pub const fn etp(&self) -> super::vals::Etp { - let val = (self.0 >> 15usize) & 0x01; - super::vals::Etp(val as u8) - } - #[doc = "External trigger polarity"] - pub fn set_etp(&mut self, val: super::vals::Etp) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); - } - } - impl Default for Smcr { - fn default() -> Smcr { - Smcr(0) - } - } - #[doc = "DMA control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dcr(pub u32); - impl Dcr { - #[doc = "DMA base address"] - pub const fn dba(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x1f; - val as u8 - } - #[doc = "DMA base address"] - pub fn set_dba(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); - } - #[doc = "DMA burst length"] - pub const fn dbl(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x1f; - val as u8 - } - #[doc = "DMA burst length"] - pub fn set_dbl(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); - } - } - impl Default for Dcr { - fn default() -> Dcr { - Dcr(0) - } - } - #[doc = "capture/compare register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ccr32(pub u32); - impl Ccr32 { - #[doc = "Capture/Compare 1 value"] - pub const fn ccr(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Capture/Compare 1 value"] - pub fn set_ccr(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Ccr32 { - fn default() -> Ccr32 { - Ccr32(0) - } - } - #[doc = "auto-reload register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Arr16(pub u32); - impl Arr16 { - #[doc = "Auto-reload value"] - pub const fn arr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Auto-reload value"] - pub fn set_arr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Arr16 { - fn default() -> Arr16 { - Arr16(0) - } - } - #[doc = "DMA address for full transfer"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dmar(pub u32); - impl Dmar { - #[doc = "DMA register for burst accesses"] - pub const fn dmab(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "DMA register for burst accesses"] - pub fn set_dmab(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Dmar { - fn default() -> Dmar { - Dmar(0) - } - } - #[doc = "counter"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cnt32(pub u32); - impl Cnt32 { - #[doc = "counter value"] - pub const fn cnt(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "counter value"] - pub fn set_cnt(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Cnt32 { - fn default() -> Cnt32 { - Cnt32(0) - } - } - #[doc = "break and dead-time register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Bdtr(pub u32); - impl Bdtr { - #[doc = "Dead-time generator setup"] - pub const fn dtg(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Dead-time generator setup"] - pub fn set_dtg(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - #[doc = "Lock configuration"] - pub const fn lock(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x03; - val as u8 - } - #[doc = "Lock configuration"] - pub fn set_lock(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); - } - #[doc = "Off-state selection for Idle mode"] - pub const fn ossi(&self) -> super::vals::Ossi { - let val = (self.0 >> 10usize) & 0x01; - super::vals::Ossi(val as u8) - } - #[doc = "Off-state selection for Idle mode"] - pub fn set_ossi(&mut self, val: super::vals::Ossi) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); - } - #[doc = "Off-state selection for Run mode"] - pub const fn ossr(&self) -> super::vals::Ossr { - let val = (self.0 >> 11usize) & 0x01; - super::vals::Ossr(val as u8) - } - #[doc = "Off-state selection for Run mode"] - pub fn set_ossr(&mut self, val: super::vals::Ossr) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); - } - #[doc = "Break enable"] - pub const fn bke(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[doc = "Break enable"] - pub fn set_bke(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[doc = "Break polarity"] - pub const fn bkp(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "Break polarity"] - pub fn set_bkp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[doc = "Automatic output enable"] - pub const fn aoe(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Automatic output enable"] - pub fn set_aoe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[doc = "Main output enable"] - pub const fn moe(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[doc = "Main output enable"] - pub fn set_moe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } - } - impl Default for Bdtr { - fn default() -> Bdtr { - Bdtr(0) - } - } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct SrAdv(pub u32); - impl SrAdv { - #[doc = "Update interrupt flag"] - pub const fn uif(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt flag"] - pub fn set_uif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare 1 interrupt flag"] - pub fn ccif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/compare 1 interrupt flag"] - pub fn set_ccif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "COM interrupt flag"] - pub const fn comif(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "COM interrupt flag"] - pub fn set_comif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger interrupt flag"] - pub const fn tif(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger interrupt flag"] - pub fn set_tif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break interrupt flag"] - pub const fn bif(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break interrupt flag"] - pub fn set_bif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Capture/Compare 1 overcapture flag"] - pub fn ccof(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 overcapture flag"] - pub fn set_ccof(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for SrAdv { - fn default() -> SrAdv { - SrAdv(0) - } - } - #[doc = "repetition counter register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Rcr(pub u32); - impl Rcr { - #[doc = "Repetition counter value"] - pub const fn rep(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Repetition counter value"] - pub fn set_rep(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - } - impl Default for Rcr { - fn default() -> Rcr { - Rcr(0) - } - } - #[doc = "control register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1Basic(pub u32); - impl Cr1Basic { - #[doc = "Counter enable"] - pub const fn cen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Counter enable"] - pub fn set_cen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Update disable"] - pub const fn udis(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Update disable"] - pub fn set_udis(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Update request source"] - pub const fn urs(&self) -> super::vals::Urs { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Urs(val as u8) - } - #[doc = "Update request source"] - pub fn set_urs(&mut self, val: super::vals::Urs) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "One-pulse mode"] - pub const fn opm(&self) -> super::vals::Opm { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Opm(val as u8) - } - #[doc = "One-pulse mode"] - pub fn set_opm(&mut self, val: super::vals::Opm) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Auto-reload preload enable"] - pub const fn arpe(&self) -> super::vals::Arpe { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Arpe(val as u8) - } - #[doc = "Auto-reload preload enable"] - pub fn set_arpe(&mut self, val: super::vals::Arpe) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - } - impl Default for Cr1Basic { - fn default() -> Cr1Basic { - Cr1Basic(0) - } - } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct SrBasic(pub u32); - impl SrBasic { - #[doc = "Update interrupt flag"] - pub const fn uif(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt flag"] - pub fn set_uif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for SrBasic { - fn default() -> SrBasic { - SrBasic(0) - } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cms(pub u8); - impl Cms { - #[doc = "The counter counts up or down depending on the direction bit"] - pub const EDGEALIGNED: Self = Self(0); - #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] - pub const CENTERALIGNED1: Self = Self(0x01); - #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] - pub const CENTERALIGNED2: Self = Self(0x02); - #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] - pub const CENTERALIGNED3: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Tis(pub u8); - impl Tis { - #[doc = "The TIMx_CH1 pin is connected to TI1 input"] - pub const NORMAL: Self = Self(0); - #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"] - pub const XOR: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Msm(pub u8); - impl Msm { - #[doc = "No action"] - pub const NOSYNC: Self = Self(0); - #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."] - pub const SYNC: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mms(pub u8); - impl Mms { - #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"] - pub const RESET: Self = Self(0); - #[doc = "The counter enable signal, CNT_EN, is used as trigger output"] - pub const ENABLE: Self = Self(0x01); - #[doc = "The update event is selected as trigger output"] - pub const UPDATE: Self = Self(0x02); - #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"] - pub const COMPAREPULSE: Self = Self(0x03); - #[doc = "OC1REF signal is used as trigger output"] - pub const COMPAREOC1: Self = Self(0x04); - #[doc = "OC2REF signal is used as trigger output"] - pub const COMPAREOC2: Self = Self(0x05); - #[doc = "OC3REF signal is used as trigger output"] - pub const COMPAREOC3: Self = Self(0x06); - #[doc = "OC4REF signal is used as trigger output"] - pub const COMPAREOC4: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dir(pub u8); - impl Dir { - #[doc = "Counter used as upcounter"] - pub const UP: Self = Self(0); - #[doc = "Counter used as downcounter"] - pub const DOWN: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Arpe(pub u8); - impl Arpe { - #[doc = "TIMx_APRR register is not buffered"] - pub const DISABLED: Self = Self(0); - #[doc = "TIMx_APRR register is buffered"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Sms(pub u8); - impl Sms { - #[doc = "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] - pub const DISABLED: Self = Self(0); - #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."] - pub const ENCODER_MODE_1: Self = Self(0x01); - #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."] - pub const ENCODER_MODE_2: Self = Self(0x02); - #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."] - pub const ENCODER_MODE_3: Self = Self(0x03); - #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."] - pub const RESET_MODE: Self = Self(0x04); - #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."] - pub const GATED_MODE: Self = Self(0x05); - #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."] - pub const TRIGGER_MODE: Self = Self(0x06); - #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."] - pub const EXT_CLOCK_MODE: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ocm(pub u8); - impl Ocm { - #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] - pub const FROZEN: Self = Self(0); - #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] - pub const ACTIVEONMATCH: Self = Self(0x01); - #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] - pub const INACTIVEONMATCH: Self = Self(0x02); - #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] - pub const TOGGLE: Self = Self(0x03); - #[doc = "OCyREF is forced low"] - pub const FORCEINACTIVE: Self = Self(0x04); - #[doc = "OCyREF is forced high"] - pub const FORCEACTIVE: Self = Self(0x05); - #[doc = "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active"] - pub const PWMMODE1: Self = Self(0x06); - #[doc = "Inversely to PwmMode1"] - pub const PWMMODE2: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ocpe(pub u8); - impl Ocpe { - #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"] - pub const DISABLED: Self = Self(0); - #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ckd(pub u8); - impl Ckd { - #[doc = "t_DTS = t_CK_INT"] - pub const DIV1: Self = Self(0); - #[doc = "t_DTS = 2 × t_CK_INT"] - pub const DIV2: Self = Self(0x01); - #[doc = "t_DTS = 4 × t_CK_INT"] - pub const DIV4: Self = Self(0x02); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Icf(pub u8); - impl Icf { - #[doc = "No filter, sampling is done at fDTS"] - pub const NOFILTER: Self = Self(0); - #[doc = "fSAMPLING=fCK_INT, N=2"] - pub const FCK_INT_N2: Self = Self(0x01); - #[doc = "fSAMPLING=fCK_INT, N=4"] - pub const FCK_INT_N4: Self = Self(0x02); - #[doc = "fSAMPLING=fCK_INT, N=8"] - pub const FCK_INT_N8: Self = Self(0x03); - #[doc = "fSAMPLING=fDTS/2, N=6"] - pub const FDTS_DIV2_N6: Self = Self(0x04); - #[doc = "fSAMPLING=fDTS/2, N=8"] - pub const FDTS_DIV2_N8: Self = Self(0x05); - #[doc = "fSAMPLING=fDTS/4, N=6"] - pub const FDTS_DIV4_N6: Self = Self(0x06); - #[doc = "fSAMPLING=fDTS/4, N=8"] - pub const FDTS_DIV4_N8: Self = Self(0x07); - #[doc = "fSAMPLING=fDTS/8, N=6"] - pub const FDTS_DIV8_N6: Self = Self(0x08); - #[doc = "fSAMPLING=fDTS/8, N=8"] - pub const FDTS_DIV8_N8: Self = Self(0x09); - #[doc = "fSAMPLING=fDTS/16, N=5"] - pub const FDTS_DIV16_N5: Self = Self(0x0a); - #[doc = "fSAMPLING=fDTS/16, N=6"] - pub const FDTS_DIV16_N6: Self = Self(0x0b); - #[doc = "fSAMPLING=fDTS/16, N=8"] - pub const FDTS_DIV16_N8: Self = Self(0x0c); - #[doc = "fSAMPLING=fDTS/32, N=5"] - pub const FDTS_DIV32_N5: Self = Self(0x0d); - #[doc = "fSAMPLING=fDTS/32, N=6"] - pub const FDTS_DIV32_N6: Self = Self(0x0e); - #[doc = "fSAMPLING=fDTS/32, N=8"] - pub const FDTS_DIV32_N8: Self = Self(0x0f); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Urs(pub u8); - impl Urs { - #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"] - pub const ANYEVENT: Self = Self(0); - #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"] - pub const COUNTERONLY: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ccds(pub u8); - impl Ccds { - #[doc = "CCx DMA request sent when CCx event occurs"] - pub const ONCOMPARE: Self = Self(0); - #[doc = "CCx DMA request sent when update event occurs"] - pub const ONUPDATE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct CcmrInputCcs(pub u8); - impl CcmrInputCcs { - #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"] - pub const TI4: Self = Self(0x01); - #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"] - pub const TI3: Self = Self(0x02); - #[doc = "CCx channel is configured as input, ICx is mapped on TRC"] - pub const TRC: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Opm(pub u8); - impl Opm { - #[doc = "Counter is not stopped at update event"] - pub const DISABLED: Self = Self(0); - #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct CcmrOutputCcs(pub u8); - impl CcmrOutputCcs { - #[doc = "CCx channel is configured as output"] - pub const OUTPUT: Self = Self(0); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ece(pub u8); - impl Ece { - #[doc = "External clock mode 2 disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Etp(pub u8); - impl Etp { - #[doc = "ETR is noninverted, active at high level or rising edge"] - pub const NOTINVERTED: Self = Self(0); - #[doc = "ETR is inverted, active at low level or falling edge"] - pub const INVERTED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Etf(pub u8); - impl Etf { - #[doc = "No filter, sampling is done at fDTS"] - pub const NOFILTER: Self = Self(0); - #[doc = "fSAMPLING=fCK_INT, N=2"] - pub const FCK_INT_N2: Self = Self(0x01); - #[doc = "fSAMPLING=fCK_INT, N=4"] - pub const FCK_INT_N4: Self = Self(0x02); - #[doc = "fSAMPLING=fCK_INT, N=8"] - pub const FCK_INT_N8: Self = Self(0x03); - #[doc = "fSAMPLING=fDTS/2, N=6"] - pub const FDTS_DIV2_N6: Self = Self(0x04); - #[doc = "fSAMPLING=fDTS/2, N=8"] - pub const FDTS_DIV2_N8: Self = Self(0x05); - #[doc = "fSAMPLING=fDTS/4, N=6"] - pub const FDTS_DIV4_N6: Self = Self(0x06); - #[doc = "fSAMPLING=fDTS/4, N=8"] - pub const FDTS_DIV4_N8: Self = Self(0x07); - #[doc = "fSAMPLING=fDTS/8, N=6"] - pub const FDTS_DIV8_N6: Self = Self(0x08); - #[doc = "fSAMPLING=fDTS/8, N=8"] - pub const FDTS_DIV8_N8: Self = Self(0x09); - #[doc = "fSAMPLING=fDTS/16, N=5"] - pub const FDTS_DIV16_N5: Self = Self(0x0a); - #[doc = "fSAMPLING=fDTS/16, N=6"] - pub const FDTS_DIV16_N6: Self = Self(0x0b); - #[doc = "fSAMPLING=fDTS/16, N=8"] - pub const FDTS_DIV16_N8: Self = Self(0x0c); - #[doc = "fSAMPLING=fDTS/32, N=5"] - pub const FDTS_DIV32_N5: Self = Self(0x0d); - #[doc = "fSAMPLING=fDTS/32, N=6"] - pub const FDTS_DIV32_N6: Self = Self(0x0e); - #[doc = "fSAMPLING=fDTS/32, N=8"] - pub const FDTS_DIV32_N8: Self = Self(0x0f); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ts(pub u8); - impl Ts { - #[doc = "Internal Trigger 0 (ITR0)"] - pub const ITR0: Self = Self(0); - #[doc = "Internal Trigger 1 (ITR1)"] - pub const ITR1: Self = Self(0x01); - #[doc = "Internal Trigger 2 (ITR2)"] - pub const ITR2: Self = Self(0x02); - #[doc = "TI1 Edge Detector (TI1F_ED)"] - pub const TI1F_ED: Self = Self(0x04); - #[doc = "Filtered Timer Input 1 (TI1FP1)"] - pub const TI1FP1: Self = Self(0x05); - #[doc = "Filtered Timer Input 2 (TI2FP2)"] - pub const TI2FP2: Self = Self(0x06); - #[doc = "External Trigger input (ETRF)"] - pub const ETRF: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ossr(pub u8); - impl Ossr { - #[doc = "When inactive, OC/OCN outputs are disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"] - pub const IDLELEVEL: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Etps(pub u8); - impl Etps { - #[doc = "Prescaler OFF"] - pub const DIV1: Self = Self(0); - #[doc = "ETRP frequency divided by 2"] - pub const DIV2: Self = Self(0x01); - #[doc = "ETRP frequency divided by 4"] - pub const DIV4: Self = Self(0x02); - #[doc = "ETRP frequency divided by 8"] - pub const DIV8: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ossi(pub u8); - impl Ossi { - #[doc = "When inactive, OC/OCN outputs are disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "When inactive, OC/OCN outputs are forced to idle level"] - pub const IDLELEVEL: Self = Self(0x01); - } } } diff --git a/embassy-stm32/src/pac/stm32f429zi.rs b/embassy-stm32/src/pac/stm32f429zi.rs index b76378e0..a1a3ab42 100644 --- a/embassy-stm32/src/pac/stm32f429zi.rs +++ b/embassy-stm32/src/pac/stm32f429zi.rs @@ -6,23 +6,23 @@ pub fn GPIO(n: usize) -> gpio::Gpio { gpio::Gpio((0x40020000 + 0x400 * n) as _) } pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); -impl_dma_channel!(DMA1_CH0, 1, 0); -impl_dma_channel!(DMA1_CH1, 1, 1); -impl_dma_channel!(DMA1_CH2, 1, 2); -impl_dma_channel!(DMA1_CH3, 1, 3); -impl_dma_channel!(DMA1_CH4, 1, 4); -impl_dma_channel!(DMA1_CH5, 1, 5); -impl_dma_channel!(DMA1_CH6, 1, 6); -impl_dma_channel!(DMA1_CH7, 1, 7); +impl_dma_channel!(DMA1_CH0, DMA1, 0); +impl_dma_channel!(DMA1_CH1, DMA1, 1); +impl_dma_channel!(DMA1_CH2, DMA1, 2); +impl_dma_channel!(DMA1_CH3, DMA1, 3); +impl_dma_channel!(DMA1_CH4, DMA1, 4); +impl_dma_channel!(DMA1_CH5, DMA1, 5); +impl_dma_channel!(DMA1_CH6, DMA1, 6); +impl_dma_channel!(DMA1_CH7, DMA1, 7); pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); -impl_dma_channel!(DMA2_CH0, 2, 0); -impl_dma_channel!(DMA2_CH1, 2, 1); -impl_dma_channel!(DMA2_CH2, 2, 2); -impl_dma_channel!(DMA2_CH3, 2, 3); -impl_dma_channel!(DMA2_CH4, 2, 4); -impl_dma_channel!(DMA2_CH5, 2, 5); -impl_dma_channel!(DMA2_CH6, 2, 6); -impl_dma_channel!(DMA2_CH7, 2, 7); +impl_dma_channel!(DMA2_CH0, DMA2, 0); +impl_dma_channel!(DMA2_CH1, DMA2, 1); +impl_dma_channel!(DMA2_CH2, DMA2, 2); +impl_dma_channel!(DMA2_CH3, DMA2, 3); +impl_dma_channel!(DMA2_CH4, DMA2, 4); +impl_dma_channel!(DMA2_CH5, DMA2, 5); +impl_dma_channel!(DMA2_CH6, DMA2, 6); +impl_dma_channel!(DMA2_CH7, DMA2, 7); pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); impl_gpio_pin!(PA0, 0, 0, EXTI0); diff --git a/embassy-stm32/src/pac/stm32l431cb.rs b/embassy-stm32/src/pac/stm32l431cb.rs index 4201a530..ea00d69f 100644 --- a/embassy-stm32/src/pac/stm32l431cb.rs +++ b/embassy-stm32/src/pac/stm32l431cb.rs @@ -130,10 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l431cc.rs b/embassy-stm32/src/pac/stm32l431cc.rs index 4201a530..ea00d69f 100644 --- a/embassy-stm32/src/pac/stm32l431cc.rs +++ b/embassy-stm32/src/pac/stm32l431cc.rs @@ -130,10 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l431kb.rs b/embassy-stm32/src/pac/stm32l431kb.rs index 088aa064..09ab12d6 100644 --- a/embassy-stm32/src/pac/stm32l431kb.rs +++ b/embassy-stm32/src/pac/stm32l431kb.rs @@ -130,8 +130,26 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l431kc.rs b/embassy-stm32/src/pac/stm32l431kc.rs index 088aa064..09ab12d6 100644 --- a/embassy-stm32/src/pac/stm32l431kc.rs +++ b/embassy-stm32/src/pac/stm32l431kc.rs @@ -130,8 +130,26 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l431rb.rs b/embassy-stm32/src/pac/stm32l431rb.rs index 4201a530..ea00d69f 100644 --- a/embassy-stm32/src/pac/stm32l431rb.rs +++ b/embassy-stm32/src/pac/stm32l431rb.rs @@ -130,10 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l431rc.rs b/embassy-stm32/src/pac/stm32l431rc.rs index 4201a530..ea00d69f 100644 --- a/embassy-stm32/src/pac/stm32l431rc.rs +++ b/embassy-stm32/src/pac/stm32l431rc.rs @@ -130,10 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l431vc.rs b/embassy-stm32/src/pac/stm32l431vc.rs index 4201a530..ea00d69f 100644 --- a/embassy-stm32/src/pac/stm32l431vc.rs +++ b/embassy-stm32/src/pac/stm32l431vc.rs @@ -130,10 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l432kb.rs b/embassy-stm32/src/pac/stm32l432kb.rs index a9dd16c9..ac3b809c 100644 --- a/embassy-stm32/src/pac/stm32l432kb.rs +++ b/embassy-stm32/src/pac/stm32l432kb.rs @@ -96,8 +96,23 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l432kc.rs b/embassy-stm32/src/pac/stm32l432kc.rs index a9dd16c9..ac3b809c 100644 --- a/embassy-stm32/src/pac/stm32l432kc.rs +++ b/embassy-stm32/src/pac/stm32l432kc.rs @@ -96,8 +96,23 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l433cb.rs b/embassy-stm32/src/pac/stm32l433cb.rs index 3d3c1e40..bcfd7f87 100644 --- a/embassy-stm32/src/pac/stm32l433cb.rs +++ b/embassy-stm32/src/pac/stm32l433cb.rs @@ -130,10 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l433cc.rs b/embassy-stm32/src/pac/stm32l433cc.rs index 3d3c1e40..bcfd7f87 100644 --- a/embassy-stm32/src/pac/stm32l433cc.rs +++ b/embassy-stm32/src/pac/stm32l433cc.rs @@ -130,10 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l433rb.rs b/embassy-stm32/src/pac/stm32l433rb.rs index 3d3c1e40..bcfd7f87 100644 --- a/embassy-stm32/src/pac/stm32l433rb.rs +++ b/embassy-stm32/src/pac/stm32l433rb.rs @@ -130,10 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l433rc.rs b/embassy-stm32/src/pac/stm32l433rc.rs index 3d3c1e40..bcfd7f87 100644 --- a/embassy-stm32/src/pac/stm32l433rc.rs +++ b/embassy-stm32/src/pac/stm32l433rc.rs @@ -130,10 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l433vc.rs b/embassy-stm32/src/pac/stm32l433vc.rs index 3d3c1e40..bcfd7f87 100644 --- a/embassy-stm32/src/pac/stm32l433vc.rs +++ b/embassy-stm32/src/pac/stm32l433vc.rs @@ -130,10 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l442kc.rs b/embassy-stm32/src/pac/stm32l442kc.rs index b193e51e..b54a36ae 100644 --- a/embassy-stm32/src/pac/stm32l442kc.rs +++ b/embassy-stm32/src/pac/stm32l442kc.rs @@ -96,8 +96,23 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l443cc.rs b/embassy-stm32/src/pac/stm32l443cc.rs index ed14584f..434050d6 100644 --- a/embassy-stm32/src/pac/stm32l443cc.rs +++ b/embassy-stm32/src/pac/stm32l443cc.rs @@ -130,10 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l443rc.rs b/embassy-stm32/src/pac/stm32l443rc.rs index ed14584f..434050d6 100644 --- a/embassy-stm32/src/pac/stm32l443rc.rs +++ b/embassy-stm32/src/pac/stm32l443rc.rs @@ -130,10 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l443vc.rs b/embassy-stm32/src/pac/stm32l443vc.rs index ed14584f..434050d6 100644 --- a/embassy-stm32/src/pac/stm32l443vc.rs +++ b/embassy-stm32/src/pac/stm32l443vc.rs @@ -130,10 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496ae.rs b/embassy-stm32/src/pac/stm32l496ae.rs index 3f97aeec..6e2a59f6 100644 --- a/embassy-stm32/src/pac/stm32l496ae.rs +++ b/embassy-stm32/src/pac/stm32l496ae.rs @@ -181,10 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496ag.rs b/embassy-stm32/src/pac/stm32l496ag.rs index 3f97aeec..6e2a59f6 100644 --- a/embassy-stm32/src/pac/stm32l496ag.rs +++ b/embassy-stm32/src/pac/stm32l496ag.rs @@ -181,10 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496qe.rs b/embassy-stm32/src/pac/stm32l496qe.rs index 3f97aeec..6e2a59f6 100644 --- a/embassy-stm32/src/pac/stm32l496qe.rs +++ b/embassy-stm32/src/pac/stm32l496qe.rs @@ -181,10 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496qg.rs b/embassy-stm32/src/pac/stm32l496qg.rs index 3f97aeec..6e2a59f6 100644 --- a/embassy-stm32/src/pac/stm32l496qg.rs +++ b/embassy-stm32/src/pac/stm32l496qg.rs @@ -181,10 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496re.rs b/embassy-stm32/src/pac/stm32l496re.rs index 3f97aeec..6e2a59f6 100644 --- a/embassy-stm32/src/pac/stm32l496re.rs +++ b/embassy-stm32/src/pac/stm32l496re.rs @@ -181,10 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496rg.rs b/embassy-stm32/src/pac/stm32l496rg.rs index 3f97aeec..6e2a59f6 100644 --- a/embassy-stm32/src/pac/stm32l496rg.rs +++ b/embassy-stm32/src/pac/stm32l496rg.rs @@ -181,10 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496ve.rs b/embassy-stm32/src/pac/stm32l496ve.rs index 3f97aeec..6e2a59f6 100644 --- a/embassy-stm32/src/pac/stm32l496ve.rs +++ b/embassy-stm32/src/pac/stm32l496ve.rs @@ -181,10 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496vg.rs b/embassy-stm32/src/pac/stm32l496vg.rs index 3f97aeec..6e2a59f6 100644 --- a/embassy-stm32/src/pac/stm32l496vg.rs +++ b/embassy-stm32/src/pac/stm32l496vg.rs @@ -181,10 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496wg.rs b/embassy-stm32/src/pac/stm32l496wg.rs index 3f97aeec..6e2a59f6 100644 --- a/embassy-stm32/src/pac/stm32l496wg.rs +++ b/embassy-stm32/src/pac/stm32l496wg.rs @@ -181,10 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496ze.rs b/embassy-stm32/src/pac/stm32l496ze.rs index 3f97aeec..6e2a59f6 100644 --- a/embassy-stm32/src/pac/stm32l496ze.rs +++ b/embassy-stm32/src/pac/stm32l496ze.rs @@ -181,10 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496zg.rs b/embassy-stm32/src/pac/stm32l496zg.rs index 3f97aeec..6e2a59f6 100644 --- a/embassy-stm32/src/pac/stm32l496zg.rs +++ b/embassy-stm32/src/pac/stm32l496zg.rs @@ -181,10 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l4a6ag.rs b/embassy-stm32/src/pac/stm32l4a6ag.rs index 2fc3593f..8ca5eca3 100644 --- a/embassy-stm32/src/pac/stm32l4a6ag.rs +++ b/embassy-stm32/src/pac/stm32l4a6ag.rs @@ -181,10 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l4a6qg.rs b/embassy-stm32/src/pac/stm32l4a6qg.rs index 2fc3593f..8ca5eca3 100644 --- a/embassy-stm32/src/pac/stm32l4a6qg.rs +++ b/embassy-stm32/src/pac/stm32l4a6qg.rs @@ -181,10 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l4a6rg.rs b/embassy-stm32/src/pac/stm32l4a6rg.rs index 2fc3593f..8ca5eca3 100644 --- a/embassy-stm32/src/pac/stm32l4a6rg.rs +++ b/embassy-stm32/src/pac/stm32l4a6rg.rs @@ -181,10 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l4a6vg.rs b/embassy-stm32/src/pac/stm32l4a6vg.rs index 2fc3593f..8ca5eca3 100644 --- a/embassy-stm32/src/pac/stm32l4a6vg.rs +++ b/embassy-stm32/src/pac/stm32l4a6vg.rs @@ -181,10 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l4a6zg.rs b/embassy-stm32/src/pac/stm32l4a6zg.rs index 2fc3593f..8ca5eca3 100644 --- a/embassy-stm32/src/pac/stm32l4a6zg.rs +++ b/embassy-stm32/src/pac/stm32l4a6zg.rs @@ -181,10 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l4p5ae.rs b/embassy-stm32/src/pac/stm32l4p5ae.rs index ae3342f4..c406d194 100644 --- a/embassy-stm32/src/pac/stm32l4p5ae.rs +++ b/embassy-stm32/src/pac/stm32l4p5ae.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5ag.rs b/embassy-stm32/src/pac/stm32l4p5ag.rs index ae3342f4..c406d194 100644 --- a/embassy-stm32/src/pac/stm32l4p5ag.rs +++ b/embassy-stm32/src/pac/stm32l4p5ag.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5ce.rs b/embassy-stm32/src/pac/stm32l4p5ce.rs index ae3342f4..c406d194 100644 --- a/embassy-stm32/src/pac/stm32l4p5ce.rs +++ b/embassy-stm32/src/pac/stm32l4p5ce.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5cg.rs b/embassy-stm32/src/pac/stm32l4p5cg.rs index ae3342f4..c406d194 100644 --- a/embassy-stm32/src/pac/stm32l4p5cg.rs +++ b/embassy-stm32/src/pac/stm32l4p5cg.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5qe.rs b/embassy-stm32/src/pac/stm32l4p5qe.rs index ae3342f4..c406d194 100644 --- a/embassy-stm32/src/pac/stm32l4p5qe.rs +++ b/embassy-stm32/src/pac/stm32l4p5qe.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5qg.rs b/embassy-stm32/src/pac/stm32l4p5qg.rs index ae3342f4..c406d194 100644 --- a/embassy-stm32/src/pac/stm32l4p5qg.rs +++ b/embassy-stm32/src/pac/stm32l4p5qg.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5re.rs b/embassy-stm32/src/pac/stm32l4p5re.rs index ae3342f4..c406d194 100644 --- a/embassy-stm32/src/pac/stm32l4p5re.rs +++ b/embassy-stm32/src/pac/stm32l4p5re.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5rg.rs b/embassy-stm32/src/pac/stm32l4p5rg.rs index ae3342f4..c406d194 100644 --- a/embassy-stm32/src/pac/stm32l4p5rg.rs +++ b/embassy-stm32/src/pac/stm32l4p5rg.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5ve.rs b/embassy-stm32/src/pac/stm32l4p5ve.rs index ae3342f4..c406d194 100644 --- a/embassy-stm32/src/pac/stm32l4p5ve.rs +++ b/embassy-stm32/src/pac/stm32l4p5ve.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5vg.rs b/embassy-stm32/src/pac/stm32l4p5vg.rs index ae3342f4..c406d194 100644 --- a/embassy-stm32/src/pac/stm32l4p5vg.rs +++ b/embassy-stm32/src/pac/stm32l4p5vg.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5ze.rs b/embassy-stm32/src/pac/stm32l4p5ze.rs index ae3342f4..c406d194 100644 --- a/embassy-stm32/src/pac/stm32l4p5ze.rs +++ b/embassy-stm32/src/pac/stm32l4p5ze.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5zg.rs b/embassy-stm32/src/pac/stm32l4p5zg.rs index ae3342f4..c406d194 100644 --- a/embassy-stm32/src/pac/stm32l4p5zg.rs +++ b/embassy-stm32/src/pac/stm32l4p5zg.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4q5ag.rs b/embassy-stm32/src/pac/stm32l4q5ag.rs index 2313edd8..d8552a71 100644 --- a/embassy-stm32/src/pac/stm32l4q5ag.rs +++ b/embassy-stm32/src/pac/stm32l4q5ag.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4q5cg.rs b/embassy-stm32/src/pac/stm32l4q5cg.rs index 2313edd8..d8552a71 100644 --- a/embassy-stm32/src/pac/stm32l4q5cg.rs +++ b/embassy-stm32/src/pac/stm32l4q5cg.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4q5qg.rs b/embassy-stm32/src/pac/stm32l4q5qg.rs index 2313edd8..d8552a71 100644 --- a/embassy-stm32/src/pac/stm32l4q5qg.rs +++ b/embassy-stm32/src/pac/stm32l4q5qg.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4q5rg.rs b/embassy-stm32/src/pac/stm32l4q5rg.rs index 2313edd8..d8552a71 100644 --- a/embassy-stm32/src/pac/stm32l4q5rg.rs +++ b/embassy-stm32/src/pac/stm32l4q5rg.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4q5vg.rs b/embassy-stm32/src/pac/stm32l4q5vg.rs index 2313edd8..d8552a71 100644 --- a/embassy-stm32/src/pac/stm32l4q5vg.rs +++ b/embassy-stm32/src/pac/stm32l4q5vg.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4q5zg.rs b/embassy-stm32/src/pac/stm32l4q5zg.rs index 2313edd8..d8552a71 100644 --- a/embassy-stm32/src/pac/stm32l4q5zg.rs +++ b/embassy-stm32/src/pac/stm32l4q5zg.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r5ag.rs b/embassy-stm32/src/pac/stm32l4r5ag.rs index c9741414..b739f4df 100644 --- a/embassy-stm32/src/pac/stm32l4r5ag.rs +++ b/embassy-stm32/src/pac/stm32l4r5ag.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r5ai.rs b/embassy-stm32/src/pac/stm32l4r5ai.rs index c9741414..b739f4df 100644 --- a/embassy-stm32/src/pac/stm32l4r5ai.rs +++ b/embassy-stm32/src/pac/stm32l4r5ai.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r5qg.rs b/embassy-stm32/src/pac/stm32l4r5qg.rs index c9741414..b739f4df 100644 --- a/embassy-stm32/src/pac/stm32l4r5qg.rs +++ b/embassy-stm32/src/pac/stm32l4r5qg.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r5qi.rs b/embassy-stm32/src/pac/stm32l4r5qi.rs index c9741414..b739f4df 100644 --- a/embassy-stm32/src/pac/stm32l4r5qi.rs +++ b/embassy-stm32/src/pac/stm32l4r5qi.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r5vg.rs b/embassy-stm32/src/pac/stm32l4r5vg.rs index c9741414..b739f4df 100644 --- a/embassy-stm32/src/pac/stm32l4r5vg.rs +++ b/embassy-stm32/src/pac/stm32l4r5vg.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r5vi.rs b/embassy-stm32/src/pac/stm32l4r5vi.rs index c9741414..b739f4df 100644 --- a/embassy-stm32/src/pac/stm32l4r5vi.rs +++ b/embassy-stm32/src/pac/stm32l4r5vi.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r5zg.rs b/embassy-stm32/src/pac/stm32l4r5zg.rs index c9741414..b739f4df 100644 --- a/embassy-stm32/src/pac/stm32l4r5zg.rs +++ b/embassy-stm32/src/pac/stm32l4r5zg.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r5zi.rs b/embassy-stm32/src/pac/stm32l4r5zi.rs index c9741414..b739f4df 100644 --- a/embassy-stm32/src/pac/stm32l4r5zi.rs +++ b/embassy-stm32/src/pac/stm32l4r5zi.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r7ai.rs b/embassy-stm32/src/pac/stm32l4r7ai.rs index 62ec3567..6aa7197f 100644 --- a/embassy-stm32/src/pac/stm32l4r7ai.rs +++ b/embassy-stm32/src/pac/stm32l4r7ai.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r7vi.rs b/embassy-stm32/src/pac/stm32l4r7vi.rs index 62ec3567..6aa7197f 100644 --- a/embassy-stm32/src/pac/stm32l4r7vi.rs +++ b/embassy-stm32/src/pac/stm32l4r7vi.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r7zi.rs b/embassy-stm32/src/pac/stm32l4r7zi.rs index 62ec3567..6aa7197f 100644 --- a/embassy-stm32/src/pac/stm32l4r7zi.rs +++ b/embassy-stm32/src/pac/stm32l4r7zi.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r9ag.rs b/embassy-stm32/src/pac/stm32l4r9ag.rs index dedc3788..cd85f5bf 100644 --- a/embassy-stm32/src/pac/stm32l4r9ag.rs +++ b/embassy-stm32/src/pac/stm32l4r9ag.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r9ai.rs b/embassy-stm32/src/pac/stm32l4r9ai.rs index dedc3788..cd85f5bf 100644 --- a/embassy-stm32/src/pac/stm32l4r9ai.rs +++ b/embassy-stm32/src/pac/stm32l4r9ai.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r9vg.rs b/embassy-stm32/src/pac/stm32l4r9vg.rs index dedc3788..cd85f5bf 100644 --- a/embassy-stm32/src/pac/stm32l4r9vg.rs +++ b/embassy-stm32/src/pac/stm32l4r9vg.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r9vi.rs b/embassy-stm32/src/pac/stm32l4r9vi.rs index dedc3788..cd85f5bf 100644 --- a/embassy-stm32/src/pac/stm32l4r9vi.rs +++ b/embassy-stm32/src/pac/stm32l4r9vi.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r9zg.rs b/embassy-stm32/src/pac/stm32l4r9zg.rs index dedc3788..cd85f5bf 100644 --- a/embassy-stm32/src/pac/stm32l4r9zg.rs +++ b/embassy-stm32/src/pac/stm32l4r9zg.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r9zi.rs b/embassy-stm32/src/pac/stm32l4r9zi.rs index dedc3788..cd85f5bf 100644 --- a/embassy-stm32/src/pac/stm32l4r9zi.rs +++ b/embassy-stm32/src/pac/stm32l4r9zi.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s5ai.rs b/embassy-stm32/src/pac/stm32l4s5ai.rs index 95c47ae1..c101f5c5 100644 --- a/embassy-stm32/src/pac/stm32l4s5ai.rs +++ b/embassy-stm32/src/pac/stm32l4s5ai.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s5qi.rs b/embassy-stm32/src/pac/stm32l4s5qi.rs index 95c47ae1..c101f5c5 100644 --- a/embassy-stm32/src/pac/stm32l4s5qi.rs +++ b/embassy-stm32/src/pac/stm32l4s5qi.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s5vi.rs b/embassy-stm32/src/pac/stm32l4s5vi.rs index 95c47ae1..c101f5c5 100644 --- a/embassy-stm32/src/pac/stm32l4s5vi.rs +++ b/embassy-stm32/src/pac/stm32l4s5vi.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s5zi.rs b/embassy-stm32/src/pac/stm32l4s5zi.rs index 95c47ae1..c101f5c5 100644 --- a/embassy-stm32/src/pac/stm32l4s5zi.rs +++ b/embassy-stm32/src/pac/stm32l4s5zi.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s7ai.rs b/embassy-stm32/src/pac/stm32l4s7ai.rs index 6ff9debf..c6cc8f7d 100644 --- a/embassy-stm32/src/pac/stm32l4s7ai.rs +++ b/embassy-stm32/src/pac/stm32l4s7ai.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s7vi.rs b/embassy-stm32/src/pac/stm32l4s7vi.rs index 6ff9debf..c6cc8f7d 100644 --- a/embassy-stm32/src/pac/stm32l4s7vi.rs +++ b/embassy-stm32/src/pac/stm32l4s7vi.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s7zi.rs b/embassy-stm32/src/pac/stm32l4s7zi.rs index 6ff9debf..c6cc8f7d 100644 --- a/embassy-stm32/src/pac/stm32l4s7zi.rs +++ b/embassy-stm32/src/pac/stm32l4s7zi.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s9ai.rs b/embassy-stm32/src/pac/stm32l4s9ai.rs index 7031b3ac..7b93516a 100644 --- a/embassy-stm32/src/pac/stm32l4s9ai.rs +++ b/embassy-stm32/src/pac/stm32l4s9ai.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s9vi.rs b/embassy-stm32/src/pac/stm32l4s9vi.rs index 7031b3ac..7b93516a 100644 --- a/embassy-stm32/src/pac/stm32l4s9vi.rs +++ b/embassy-stm32/src/pac/stm32l4s9vi.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s9zi.rs b/embassy-stm32/src/pac/stm32l4s9zi.rs index 7031b3ac..7b93516a 100644 --- a/embassy-stm32/src/pac/stm32l4s9zi.rs +++ b/embassy-stm32/src/pac/stm32l4s9zi.rs @@ -181,10 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1); +impl_spi_pin!(SPI1, Sck, PA1, 5); +impl_spi_pin!(SPI1, Miso, PA11, 5); +impl_spi_pin!(SPI1, Mosi, PA12, 5); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, Sck, PE13, 5); +impl_spi_pin!(SPI1, Miso, PE14, 5); +impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, Sck, PG2, 5); +impl_spi_pin!(SPI1, Miso, PG3, 5); +impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2); +impl_spi_pin!(SPI2, Sck, PA9, 3); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 3); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD1, 5); +impl_spi_pin!(SPI2, Sck, PD3, 3); +impl_spi_pin!(SPI2, Miso, PD3, 5); +impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, Miso, PG10, 6); +impl_spi_pin!(SPI3, Mosi, PG11, 6); +impl_spi_pin!(SPI3, Sck, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/spi.rs b/embassy-stm32/src/spi.rs index 3eec7742..c581f146 100644 --- a/embassy-stm32/src/spi.rs +++ b/embassy-stm32/src/spi.rs @@ -4,14 +4,56 @@ pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_ use core::marker::PhantomData; use embassy::interrupt::Interrupt; use embedded_hal::blocking::spi::{Write, Transfer}; +use embassy::util::Unborrow; +use embassy_extras::{impl_unborrow, unborrow}; +use crate::gpio::{Pin, AnyPin}; +use crate::pac::gpio::vals::Afr; +use crate::pac::gpio::Gpio; //use crate::pac::spi; pub struct Spi<'d, T: Instance> { peri: T, + sck: AnyPin, + mosi: AnyPin, + miso: AnyPin, //irq: T::Interrupt, phantom: PhantomData<&'d mut T>, } +impl<'d, T: Instance> Spi<'d, T> { + pub fn new(peri: impl Unborrow + 'd, + sck: impl Unborrow>, + mosi: impl Unborrow>, + miso: impl Unborrow>, + ) -> Self { + unborrow!(peri); + unborrow!(sck, mosi, miso); + + unsafe { + Self::configure_pin( sck.block(), sck.pin() as usize, sck.af() ); + Self::configure_pin( mosi.block(), mosi.pin() as usize, mosi.af() ); + Self::configure_pin( miso.block(), miso.pin() as usize, miso.af() ); + } + + let sck = sck.degrade(); + let mosi = mosi.degrade(); + let miso = miso.degrade(); + + Self { + peri, + sck, + mosi, + miso, + phantom: PhantomData, + } + } + + unsafe fn configure_pin(block: Gpio, pin: usize, af_num: u8) { + let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) }; + block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num))); + } +} + pub enum Error { Framing, Crc, @@ -111,12 +153,45 @@ pub(crate) mod sealed { fn regs() -> &'static crate::pac::spi::Spi; //fn state() -> &'static State; } + + pub trait Sck : Pin { + const AF: u8; + fn af(&self) -> u8 { + Self::AF + } + } + + pub trait Mosi : Pin { + const AF: u8; + fn af(&self) -> u8 { + Self::AF + } + } + + pub trait Miso : Pin { + const AF: u8; + fn af(&self) -> u8 { + Self::AF + } + } } pub trait Instance: sealed::Instance + 'static { //type Interrupt: Interrupt; } +pub trait Sck: sealed::Sck + 'static { + +} + +pub trait Mosi: sealed::Mosi + 'static { + +} + +pub trait Miso: sealed::Miso + 'static { + +} + macro_rules! impl_spi { ($inst:ident) => { impl crate::spi::sealed::Instance for peripherals::$inst { @@ -127,4 +202,15 @@ macro_rules! impl_spi { impl crate::spi::Instance for peripherals::$inst {} }; +} + +macro_rules! impl_spi_pin { + ($inst:ident, $pin_func:ident, $pin:ident, $af:expr) => { + impl crate::spi::$pin_func for peripherals::$pin { + } + + impl crate::spi::sealed::$pin_func for peripherals::$pin { + const AF: u8 = $af; + } + } } \ No newline at end of file diff --git a/embassy-stm32/stm32-data b/embassy-stm32/stm32-data index 10f86e02..2e550650 160000 --- a/embassy-stm32/stm32-data +++ b/embassy-stm32/stm32-data @@ -1 +1 @@ -Subproject commit 10f86e022b297069c0da9069814e7b811f19d2e1 +Subproject commit 2e55065013cda8b5836d74570530e7fdb75a76b3 From 36c16dbef8786a5323f722034936c5bd2482f681 Mon Sep 17 00:00:00 2001 From: Bob McWhirter Date: Wed, 12 May 2021 10:46:18 -0400 Subject: [PATCH 4/8] Continuing to update clocks (unused now) and SPI --- embassy-stm32/gen.py | 3 +- embassy-stm32/src/gpio.rs | 10 + embassy-stm32/src/lib.rs | 1 + embassy-stm32/src/pac/regs.rs | 13298 ++++++++++++------------- embassy-stm32/src/pac/stm32l431cb.rs | 6 +- embassy-stm32/src/pac/stm32l431cc.rs | 6 +- embassy-stm32/src/pac/stm32l431kb.rs | 4 +- embassy-stm32/src/pac/stm32l431kc.rs | 4 +- embassy-stm32/src/pac/stm32l431rb.rs | 6 +- embassy-stm32/src/pac/stm32l431rc.rs | 6 +- embassy-stm32/src/pac/stm32l431vc.rs | 6 +- embassy-stm32/src/pac/stm32l432kb.rs | 4 +- embassy-stm32/src/pac/stm32l432kc.rs | 4 +- embassy-stm32/src/pac/stm32l433cb.rs | 6 +- embassy-stm32/src/pac/stm32l433cc.rs | 6 +- embassy-stm32/src/pac/stm32l433rb.rs | 6 +- embassy-stm32/src/pac/stm32l433rc.rs | 6 +- embassy-stm32/src/pac/stm32l433vc.rs | 6 +- embassy-stm32/src/pac/stm32l442kc.rs | 4 +- embassy-stm32/src/pac/stm32l443cc.rs | 6 +- embassy-stm32/src/pac/stm32l443rc.rs | 6 +- embassy-stm32/src/pac/stm32l443vc.rs | 6 +- embassy-stm32/src/pac/stm32l496ae.rs | 6 +- embassy-stm32/src/pac/stm32l496ag.rs | 6 +- embassy-stm32/src/pac/stm32l496qe.rs | 6 +- embassy-stm32/src/pac/stm32l496qg.rs | 6 +- embassy-stm32/src/pac/stm32l496re.rs | 6 +- embassy-stm32/src/pac/stm32l496rg.rs | 6 +- embassy-stm32/src/pac/stm32l496ve.rs | 6 +- embassy-stm32/src/pac/stm32l496vg.rs | 6 +- embassy-stm32/src/pac/stm32l496wg.rs | 6 +- embassy-stm32/src/pac/stm32l496ze.rs | 6 +- embassy-stm32/src/pac/stm32l496zg.rs | 6 +- embassy-stm32/src/pac/stm32l4a6ag.rs | 6 +- embassy-stm32/src/pac/stm32l4a6qg.rs | 6 +- embassy-stm32/src/pac/stm32l4a6rg.rs | 6 +- embassy-stm32/src/pac/stm32l4a6vg.rs | 6 +- embassy-stm32/src/pac/stm32l4a6zg.rs | 6 +- embassy-stm32/src/pac/stm32l4p5ae.rs | 6 +- embassy-stm32/src/pac/stm32l4p5ag.rs | 6 +- embassy-stm32/src/pac/stm32l4p5ce.rs | 6 +- embassy-stm32/src/pac/stm32l4p5cg.rs | 6 +- embassy-stm32/src/pac/stm32l4p5qe.rs | 6 +- embassy-stm32/src/pac/stm32l4p5qg.rs | 6 +- embassy-stm32/src/pac/stm32l4p5re.rs | 6 +- embassy-stm32/src/pac/stm32l4p5rg.rs | 6 +- embassy-stm32/src/pac/stm32l4p5ve.rs | 6 +- embassy-stm32/src/pac/stm32l4p5vg.rs | 6 +- embassy-stm32/src/pac/stm32l4p5ze.rs | 6 +- embassy-stm32/src/pac/stm32l4p5zg.rs | 6 +- embassy-stm32/src/pac/stm32l4q5ag.rs | 6 +- embassy-stm32/src/pac/stm32l4q5cg.rs | 6 +- embassy-stm32/src/pac/stm32l4q5qg.rs | 6 +- embassy-stm32/src/pac/stm32l4q5rg.rs | 6 +- embassy-stm32/src/pac/stm32l4q5vg.rs | 6 +- embassy-stm32/src/pac/stm32l4q5zg.rs | 6 +- embassy-stm32/src/pac/stm32l4r5ag.rs | 6 +- embassy-stm32/src/pac/stm32l4r5ai.rs | 6 +- embassy-stm32/src/pac/stm32l4r5qg.rs | 6 +- embassy-stm32/src/pac/stm32l4r5qi.rs | 6 +- embassy-stm32/src/pac/stm32l4r5vg.rs | 6 +- embassy-stm32/src/pac/stm32l4r5vi.rs | 6 +- embassy-stm32/src/pac/stm32l4r5zg.rs | 6 +- embassy-stm32/src/pac/stm32l4r5zi.rs | 6 +- embassy-stm32/src/pac/stm32l4r7ai.rs | 6 +- embassy-stm32/src/pac/stm32l4r7vi.rs | 6 +- embassy-stm32/src/pac/stm32l4r7zi.rs | 6 +- embassy-stm32/src/pac/stm32l4r9ag.rs | 6 +- embassy-stm32/src/pac/stm32l4r9ai.rs | 6 +- embassy-stm32/src/pac/stm32l4r9vg.rs | 6 +- embassy-stm32/src/pac/stm32l4r9vi.rs | 6 +- embassy-stm32/src/pac/stm32l4r9zg.rs | 6 +- embassy-stm32/src/pac/stm32l4r9zi.rs | 6 +- embassy-stm32/src/pac/stm32l4s5ai.rs | 6 +- embassy-stm32/src/pac/stm32l4s5qi.rs | 6 +- embassy-stm32/src/pac/stm32l4s5vi.rs | 6 +- embassy-stm32/src/pac/stm32l4s5zi.rs | 6 +- embassy-stm32/src/pac/stm32l4s7ai.rs | 6 +- embassy-stm32/src/pac/stm32l4s7vi.rs | 6 +- embassy-stm32/src/pac/stm32l4s7zi.rs | 6 +- embassy-stm32/src/pac/stm32l4s9ai.rs | 6 +- embassy-stm32/src/pac/stm32l4s9vi.rs | 6 +- embassy-stm32/src/pac/stm32l4s9zi.rs | 6 +- embassy-stm32/src/spi.rs | 132 +- embassy-stm32/src/time.rs | 127 + embassy-stm32/stm32-data | 2 +- 86 files changed, 7131 insertions(+), 6906 deletions(-) create mode 100644 embassy-stm32/src/time.rs diff --git a/embassy-stm32/gen.py b/embassy-stm32/gen.py index ec6b99b1..3f3fe569 100644 --- a/embassy-stm32/gen.py +++ b/embassy-stm32/gen.py @@ -116,7 +116,8 @@ for chip in chips.values(): f.write(f'impl_rng!({name});') if block_mod == 'spi': - f.write(f'impl_spi!({name});') + clock = peri['clock'] + f.write(f'impl_spi!({name}, {clock});') for pin, funcs in af.items(): if pin in pins: if func := funcs.get(f'{name}_SCK'): diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs index 85c573a8..350918e8 100644 --- a/embassy-stm32/src/gpio.rs +++ b/embassy-stm32/src/gpio.rs @@ -228,6 +228,16 @@ impl AnyPin { pub unsafe fn steal(pin_port: u8) -> Self { Self { pin_port } } + + #[inline] + fn _port(&self) -> u8 { + self.pin_port / 16 + } + + #[inline] + pub fn block(&self) -> gpio::Gpio { + pac::GPIO(self._port() as _) + } } impl_unborrow!(AnyPin); diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs index 6f300263..b54bc4a4 100644 --- a/embassy-stm32/src/lib.rs +++ b/embassy-stm32/src/lib.rs @@ -23,6 +23,7 @@ pub mod usart; // This must go LAST so that it sees the `impl_foo!` macros mod pac; +mod time; pub use embassy_macros::interrupt; pub use pac::{interrupt, peripherals, Peripherals}; diff --git a/embassy-stm32/src/pac/regs.rs b/embassy-stm32/src/pac/regs.rs index 9e4efa70..fa31704d 100644 --- a/embassy-stm32/src/pac/regs.rs +++ b/embassy-stm32/src/pac/regs.rs @@ -1,716 +1,5 @@ #![no_std] #![doc = "Peripheral access API (generated using svd2rust v0.17.0 (22741fa 2021-04-20))"] -pub mod syscfg_l4 { - use crate::generic::*; - #[doc = "System configuration controller"] - #[derive(Copy, Clone)] - pub struct Syscfg(pub *mut u8); - unsafe impl Send for Syscfg {} - unsafe impl Sync for Syscfg {} - impl Syscfg { - #[doc = "memory remap register"] - pub fn memrmp(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "configuration register 1"] - pub fn cfgr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "external interrupt configuration register 1"] - pub fn exticr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } - } - #[doc = "SCSR"] - pub fn scsr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } - } - #[doc = "CFGR2"] - pub fn cfgr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(28usize)) } - } - #[doc = "SWPR"] - pub fn swpr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(32usize)) } - } - #[doc = "SKR"] - pub fn skr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "SKR"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Skr(pub u32); - impl Skr { - #[doc = "SRAM2 write protection key for software erase"] - pub const fn key(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "SRAM2 write protection key for software erase"] - pub fn set_key(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - } - impl Default for Skr { - fn default() -> Skr { - Skr(0) - } - } - #[doc = "external interrupt configuration register 4"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Exticr(pub u32); - impl Exticr { - #[doc = "EXTI12 configuration bits"] - pub fn exti(&self, n: usize) -> u8 { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x0f; - val as u8 - } - #[doc = "EXTI12 configuration bits"] - pub fn set_exti(&mut self, n: usize, val: u8) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); - } - } - impl Default for Exticr { - fn default() -> Exticr { - Exticr(0) - } - } - #[doc = "SCSR"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Scsr(pub u32); - impl Scsr { - #[doc = "SRAM2 Erase"] - pub const fn sram2er(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "SRAM2 Erase"] - pub fn set_sram2er(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "SRAM2 busy by erase operation"] - pub const fn sram2bsy(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "SRAM2 busy by erase operation"] - pub fn set_sram2bsy(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - } - impl Default for Scsr { - fn default() -> Scsr { - Scsr(0) - } - } - #[doc = "SWPR"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Swpr(pub u32); - impl Swpr { - #[doc = "SRAWM2 write protection."] - pub fn pwp(&self, n: usize) -> bool { - assert!(n < 32usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "SRAWM2 write protection."] - pub fn set_pwp(&mut self, n: usize, val: bool) { - assert!(n < 32usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Swpr { - fn default() -> Swpr { - Swpr(0) - } - } - #[doc = "configuration register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cfgr1(pub u32); - impl Cfgr1 { - #[doc = "Firewall disable"] - pub const fn fwdis(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Firewall disable"] - pub fn set_fwdis(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "I/O analog switch voltage booster enable"] - pub const fn boosten(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "I/O analog switch voltage booster enable"] - pub fn set_boosten(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"] - pub const fn i2c_pb6_fmp(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"] - pub fn set_i2c_pb6_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"] - pub const fn i2c_pb7_fmp(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"] - pub fn set_i2c_pb7_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"] - pub const fn i2c_pb8_fmp(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"] - pub fn set_i2c_pb8_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"] - pub const fn i2c_pb9_fmp(&self) -> bool { - let val = (self.0 >> 19usize) & 0x01; - val != 0 - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"] - pub fn set_i2c_pb9_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); - } - #[doc = "I2C1 Fast-mode Plus driving capability activation"] - pub const fn i2c1_fmp(&self) -> bool { - let val = (self.0 >> 20usize) & 0x01; - val != 0 - } - #[doc = "I2C1 Fast-mode Plus driving capability activation"] - pub fn set_i2c1_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); - } - #[doc = "I2C2 Fast-mode Plus driving capability activation"] - pub const fn i2c2_fmp(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[doc = "I2C2 Fast-mode Plus driving capability activation"] - pub fn set_i2c2_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[doc = "I2C3 Fast-mode Plus driving capability activation"] - pub const fn i2c3_fmp(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[doc = "I2C3 Fast-mode Plus driving capability activation"] - pub fn set_i2c3_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[doc = "Floating Point Unit interrupts enable bits"] - pub const fn fpu_ie(&self) -> u8 { - let val = (self.0 >> 26usize) & 0x3f; - val as u8 - } - #[doc = "Floating Point Unit interrupts enable bits"] - pub fn set_fpu_ie(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 26usize)) | (((val as u32) & 0x3f) << 26usize); - } - } - impl Default for Cfgr1 { - fn default() -> Cfgr1 { - Cfgr1(0) - } - } - #[doc = "memory remap register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Memrmp(pub u32); - impl Memrmp { - #[doc = "Memory mapping selection"] - pub const fn mem_mode(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Memory mapping selection"] - pub fn set_mem_mode(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "QUADSPI memory mapping swap"] - pub const fn qfs(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "QUADSPI memory mapping swap"] - pub fn set_qfs(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Flash Bank mode selection"] - pub const fn fb_mode(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Flash Bank mode selection"] - pub fn set_fb_mode(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for Memrmp { - fn default() -> Memrmp { - Memrmp(0) - } - } - #[doc = "CFGR2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cfgr2(pub u32); - impl Cfgr2 { - #[doc = "Cortex LOCKUP (Hardfault) output enable bit"] - pub const fn cll(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Cortex LOCKUP (Hardfault) output enable bit"] - pub fn set_cll(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "SRAM2 parity lock bit"] - pub const fn spl(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "SRAM2 parity lock bit"] - pub fn set_spl(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "PVD lock enable bit"] - pub const fn pvdl(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "PVD lock enable bit"] - pub fn set_pvdl(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "ECC Lock"] - pub const fn eccl(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "ECC Lock"] - pub fn set_eccl(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "SRAM2 parity error flag"] - pub const fn spf(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "SRAM2 parity error flag"] - pub fn set_spf(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for Cfgr2 { - fn default() -> Cfgr2 { - Cfgr2(0) - } - } - } -} -pub mod dma_v1 { - use crate::generic::*; - #[doc = "DMA controller"] - #[derive(Copy, Clone)] - pub struct Dma(pub *mut u8); - unsafe impl Send for Dma {} - unsafe impl Sync for Dma {} - impl Dma { - #[doc = "DMA interrupt status register (DMA_ISR)"] - pub fn isr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] - pub fn ifcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] - pub fn ch(self, n: usize) -> Ch { - assert!(n < 7usize); - unsafe { Ch(self.0.add(8usize + n * 20usize)) } - } - } - #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] - #[derive(Copy, Clone)] - pub struct Ch(pub *mut u8); - unsafe impl Send for Ch {} - unsafe impl Sync for Ch {} - impl Ch { - #[doc = "DMA channel configuration register (DMA_CCR)"] - pub fn cr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "DMA channel 1 number of data register"] - pub fn ndtr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "DMA channel 1 peripheral address register"] - pub fn par(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "DMA channel 1 memory address register"] - pub fn mar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "DMA interrupt status register (DMA_ISR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Isr(pub u32); - impl Isr { - #[doc = "Channel 1 Global interrupt flag"] - pub fn gif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Global interrupt flag"] - pub fn set_gif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Transfer Complete flag"] - pub fn tcif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 1usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Transfer Complete flag"] - pub fn set_tcif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 1usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Half Transfer Complete flag"] - pub fn htif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 2usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Half Transfer Complete flag"] - pub fn set_htif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 2usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Transfer Error flag"] - pub fn teif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 3usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Transfer Error flag"] - pub fn set_teif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 3usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Isr { - fn default() -> Isr { - Isr(0) - } - } - #[doc = "DMA channel 1 number of data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ndtr(pub u32); - impl Ndtr { - #[doc = "Number of data to transfer"] - pub const fn ndt(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Number of data to transfer"] - pub fn set_ndt(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Ndtr { - fn default() -> Ndtr { - Ndtr(0) - } - } - #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ifcr(pub u32); - impl Ifcr { - #[doc = "Channel 1 Global interrupt clear"] - pub fn cgif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Global interrupt clear"] - pub fn set_cgif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Transfer Complete clear"] - pub fn ctcif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 1usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Transfer Complete clear"] - pub fn set_ctcif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 1usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Half Transfer clear"] - pub fn chtif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 2usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Half Transfer clear"] - pub fn set_chtif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 2usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Transfer Error clear"] - pub fn cteif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 3usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Transfer Error clear"] - pub fn set_cteif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 3usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Ifcr { - fn default() -> Ifcr { - Ifcr(0) - } - } - #[doc = "DMA channel configuration register (DMA_CCR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr(pub u32); - impl Cr { - #[doc = "Channel enable"] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Channel enable"] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Transfer complete interrupt enable"] - pub const fn tcie(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Transfer complete interrupt enable"] - pub fn set_tcie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Half Transfer interrupt enable"] - pub const fn htie(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Half Transfer interrupt enable"] - pub fn set_htie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Transfer error interrupt enable"] - pub const fn teie(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Transfer error interrupt enable"] - pub fn set_teie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Data transfer direction"] - pub const fn dir(&self) -> super::vals::Dir { - let val = (self.0 >> 4usize) & 0x01; - super::vals::Dir(val as u8) - } - #[doc = "Data transfer direction"] - pub fn set_dir(&mut self, val: super::vals::Dir) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); - } - #[doc = "Circular mode"] - pub const fn circ(&self) -> super::vals::Circ { - let val = (self.0 >> 5usize) & 0x01; - super::vals::Circ(val as u8) - } - #[doc = "Circular mode"] - pub fn set_circ(&mut self, val: super::vals::Circ) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); - } - #[doc = "Peripheral increment mode"] - pub const fn pinc(&self) -> super::vals::Inc { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Inc(val as u8) - } - #[doc = "Peripheral increment mode"] - pub fn set_pinc(&mut self, val: super::vals::Inc) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize); - } - #[doc = "Memory increment mode"] - pub const fn minc(&self) -> super::vals::Inc { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Inc(val as u8) - } - #[doc = "Memory increment mode"] - pub fn set_minc(&mut self, val: super::vals::Inc) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Peripheral size"] - pub const fn psize(&self) -> super::vals::Size { - let val = (self.0 >> 8usize) & 0x03; - super::vals::Size(val as u8) - } - #[doc = "Peripheral size"] - pub fn set_psize(&mut self, val: super::vals::Size) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); - } - #[doc = "Memory size"] - pub const fn msize(&self) -> super::vals::Size { - let val = (self.0 >> 10usize) & 0x03; - super::vals::Size(val as u8) - } - #[doc = "Memory size"] - pub fn set_msize(&mut self, val: super::vals::Size) { - self.0 = (self.0 & !(0x03 << 10usize)) | (((val.0 as u32) & 0x03) << 10usize); - } - #[doc = "Channel Priority level"] - pub const fn pl(&self) -> super::vals::Pl { - let val = (self.0 >> 12usize) & 0x03; - super::vals::Pl(val as u8) - } - #[doc = "Channel Priority level"] - pub fn set_pl(&mut self, val: super::vals::Pl) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); - } - #[doc = "Memory to memory mode"] - pub const fn mem2mem(&self) -> super::vals::Memmem { - let val = (self.0 >> 14usize) & 0x01; - super::vals::Memmem(val as u8) - } - #[doc = "Memory to memory mode"] - pub fn set_mem2mem(&mut self, val: super::vals::Memmem) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); - } - } - impl Default for Cr { - fn default() -> Cr { - Cr(0) - } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Circ(pub u8); - impl Circ { - #[doc = "Circular buffer disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Circular buffer enabled"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Memmem(pub u8); - impl Memmem { - #[doc = "Memory to memory mode disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Memory to memory mode enabled"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dir(pub u8); - impl Dir { - #[doc = "Read from peripheral"] - pub const FROMPERIPHERAL: Self = Self(0); - #[doc = "Read from memory"] - pub const FROMMEMORY: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Size(pub u8); - impl Size { - #[doc = "8-bit size"] - pub const BITS8: Self = Self(0); - #[doc = "16-bit size"] - pub const BITS16: Self = Self(0x01); - #[doc = "32-bit size"] - pub const BITS32: Self = Self(0x02); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pl(pub u8); - impl Pl { - #[doc = "Low priority"] - pub const LOW: Self = Self(0); - #[doc = "Medium priority"] - pub const MEDIUM: Self = Self(0x01); - #[doc = "High priority"] - pub const HIGH: Self = Self(0x02); - #[doc = "Very high priority"] - pub const VERYHIGH: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Inc(pub u8); - impl Inc { - #[doc = "Increment mode disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Increment mode enabled"] - pub const ENABLED: Self = Self(0x01); - } - } -} pub mod generic { use core::marker::PhantomData; #[derive(Copy, Clone)] @@ -781,544 +70,866 @@ pub mod generic { } } } -pub mod spi_v1 { +pub mod syscfg_h7 { use crate::generic::*; - #[doc = "Serial peripheral interface"] + #[doc = "System configuration controller"] #[derive(Copy, Clone)] - pub struct Spi(pub *mut u8); - unsafe impl Send for Spi {} - unsafe impl Sync for Spi {} - impl Spi { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { + pub struct Syscfg(pub *mut u8); + unsafe impl Send for Syscfg {} + unsafe impl Sync for Syscfg {} + impl Syscfg { + #[doc = "peripheral mode configuration register"] + pub fn pmcr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(4usize)) } } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } + #[doc = "external interrupt configuration register 1"] + pub fn exticr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } } - #[doc = "data register"] - pub fn dr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } + #[doc = "compensation cell control/status register"] + pub fn cccsr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } } - #[doc = "CRC polynomial register"] - pub fn crcpr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } + #[doc = "SYSCFG compensation cell value register"] + pub fn ccvr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } } - #[doc = "RX CRC register"] - pub fn rxcrcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } + #[doc = "SYSCFG compensation cell code register"] + pub fn cccr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } } - #[doc = "TX CRC register"] - pub fn txcrcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } + #[doc = "SYSCFG power control register"] + pub fn pwrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Crcnext(pub u8); - impl Crcnext { - #[doc = "Next transmit value is from Tx buffer"] - pub const TXBUFFER: Self = Self(0); - #[doc = "Next transmit value is from Tx CRC register"] - pub const CRC: Self = Self(0x01); + #[doc = "SYSCFG package register"] + pub fn pkgr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(292usize)) } } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Br(pub u8); - impl Br { - #[doc = "f_PCLK / 2"] - pub const DIV2: Self = Self(0); - #[doc = "f_PCLK / 4"] - pub const DIV4: Self = Self(0x01); - #[doc = "f_PCLK / 8"] - pub const DIV8: Self = Self(0x02); - #[doc = "f_PCLK / 16"] - pub const DIV16: Self = Self(0x03); - #[doc = "f_PCLK / 32"] - pub const DIV32: Self = Self(0x04); - #[doc = "f_PCLK / 64"] - pub const DIV64: Self = Self(0x05); - #[doc = "f_PCLK / 128"] - pub const DIV128: Self = Self(0x06); - #[doc = "f_PCLK / 256"] - pub const DIV256: Self = Self(0x07); + #[doc = "SYSCFG user register 0"] + pub fn ur0(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(768usize)) } } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpol(pub u8); - impl Cpol { - #[doc = "CK to 0 when idle"] - pub const IDLELOW: Self = Self(0); - #[doc = "CK to 1 when idle"] - pub const IDLEHIGH: Self = Self(0x01); + #[doc = "SYSCFG user register 2"] + pub fn ur2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(776usize)) } } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mstr(pub u8); - impl Mstr { - #[doc = "Slave configuration"] - pub const SLAVE: Self = Self(0); - #[doc = "Master configuration"] - pub const MASTER: Self = Self(0x01); + #[doc = "SYSCFG user register 3"] + pub fn ur3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(780usize)) } } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dff(pub u8); - impl Dff { - #[doc = "8-bit data frame format is selected for transmission/reception"] - pub const EIGHTBIT: Self = Self(0); - #[doc = "16-bit data frame format is selected for transmission/reception"] - pub const SIXTEENBIT: Self = Self(0x01); + #[doc = "SYSCFG user register 4"] + pub fn ur4(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(784usize)) } } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpha(pub u8); - impl Cpha { - #[doc = "The first clock transition is the first data capture edge"] - pub const FIRSTEDGE: Self = Self(0); - #[doc = "The second clock transition is the first data capture edge"] - pub const SECONDEDGE: Self = Self(0x01); + #[doc = "SYSCFG user register 5"] + pub fn ur5(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(788usize)) } } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frer(pub u8); - impl Frer { - #[doc = "No frame format error"] - pub const NOERROR: Self = Self(0); - #[doc = "A frame format error occurred"] - pub const ERROR: Self = Self(0x01); + #[doc = "SYSCFG user register 6"] + pub fn ur6(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(792usize)) } } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bidioe(pub u8); - impl Bidioe { - #[doc = "Output disabled (receive-only mode)"] - pub const OUTPUTDISABLED: Self = Self(0); - #[doc = "Output enabled (transmit-only mode)"] - pub const OUTPUTENABLED: Self = Self(0x01); + #[doc = "SYSCFG user register 7"] + pub fn ur7(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(796usize)) } } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Rxonly(pub u8); - impl Rxonly { - #[doc = "Full duplex (Transmit and receive)"] - pub const FULLDUPLEX: Self = Self(0); - #[doc = "Output disabled (Receive-only mode)"] - pub const OUTPUTDISABLED: Self = Self(0x01); + #[doc = "SYSCFG user register 8"] + pub fn ur8(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(800usize)) } } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Iscfg(pub u8); - impl Iscfg { - #[doc = "Slave - transmit"] - pub const SLAVETX: Self = Self(0); - #[doc = "Slave - receive"] - pub const SLAVERX: Self = Self(0x01); - #[doc = "Master - transmit"] - pub const MASTERTX: Self = Self(0x02); - #[doc = "Master - receive"] - pub const MASTERRX: Self = Self(0x03); + #[doc = "SYSCFG user register 9"] + pub fn ur9(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(804usize)) } } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lsbfirst(pub u8); - impl Lsbfirst { - #[doc = "Data is transmitted/received with the MSB first"] - pub const MSBFIRST: Self = Self(0); - #[doc = "Data is transmitted/received with the LSB first"] - pub const LSBFIRST: Self = Self(0x01); + #[doc = "SYSCFG user register 10"] + pub fn ur10(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(808usize)) } } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frf(pub u8); - impl Frf { - #[doc = "SPI Motorola mode"] - pub const MOTOROLA: Self = Self(0); - #[doc = "SPI TI mode"] - pub const TI: Self = Self(0x01); + #[doc = "SYSCFG user register 11"] + pub fn ur11(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(812usize)) } } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bidimode(pub u8); - impl Bidimode { - #[doc = "2-line unidirectional data mode selected"] - pub const UNIDIRECTIONAL: Self = Self(0); - #[doc = "1-line bidirectional data mode selected"] - pub const BIDIRECTIONAL: Self = Self(0x01); + #[doc = "SYSCFG user register 12"] + pub fn ur12(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(816usize)) } + } + #[doc = "SYSCFG user register 13"] + pub fn ur13(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(820usize)) } + } + #[doc = "SYSCFG user register 14"] + pub fn ur14(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(824usize)) } + } + #[doc = "SYSCFG user register 15"] + pub fn ur15(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(828usize)) } + } + #[doc = "SYSCFG user register 16"] + pub fn ur16(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(832usize)) } + } + #[doc = "SYSCFG user register 17"] + pub fn ur17(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(836usize)) } } } pub mod regs { use crate::generic::*; - #[doc = "status register"] + #[doc = "SYSCFG power control register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Sr(pub u32); - impl Sr { - #[doc = "Receive buffer not empty"] - pub const fn rxne(&self) -> bool { + pub struct Pwrcr(pub u32); + impl Pwrcr { + #[doc = "Overdrive enable"] + pub const fn oden(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Overdrive enable"] + pub fn set_oden(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + } + impl Default for Pwrcr { + fn default() -> Pwrcr { + Pwrcr(0) + } + } + #[doc = "SYSCFG user register 0"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur0(pub u32); + impl Ur0 { + #[doc = "Bank Swap"] + pub const fn bks(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Receive buffer not empty"] - pub fn set_rxne(&mut self, val: bool) { + #[doc = "Bank Swap"] + pub fn set_bks(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Transmit buffer empty"] - pub const fn txe(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 + #[doc = "Readout protection"] + pub const fn rdp(&self) -> u8 { + let val = (self.0 >> 16usize) & 0xff; + val as u8 } - #[doc = "Transmit buffer empty"] - pub fn set_txe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "CRC error flag"] - pub const fn crcerr(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "CRC error flag"] - pub fn set_crcerr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Mode fault"] - pub const fn modf(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Mode fault"] - pub fn set_modf(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Overrun flag"] - pub const fn ovr(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Overrun flag"] - pub fn set_ovr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Busy flag"] - pub const fn bsy(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Busy flag"] - pub fn set_bsy(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "TI frame format error"] - pub const fn fre(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "TI frame format error"] - pub fn set_fre(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + #[doc = "Readout protection"] + pub fn set_rdp(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); } } - impl Default for Sr { - fn default() -> Sr { - Sr(0) + impl Default for Ur0 { + fn default() -> Ur0 { + Ur0(0) } } - #[doc = "TX CRC register"] + #[doc = "SYSCFG user register 14"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Txcrcr(pub u32); - impl Txcrcr { - #[doc = "Tx CRC register"] - pub const fn tx_crc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Tx CRC register"] - pub fn set_tx_crc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Txcrcr { - fn default() -> Txcrcr { - Txcrcr(0) - } - } - #[doc = "RX CRC register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Rxcrcr(pub u32); - impl Rxcrcr { - #[doc = "Rx CRC register"] - pub const fn rx_crc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Rx CRC register"] - pub fn set_rx_crc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Rxcrcr { - fn default() -> Rxcrcr { - Rxcrcr(0) - } - } - #[doc = "CRC polynomial register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Crcpr(pub u32); - impl Crcpr { - #[doc = "CRC polynomial register"] - pub const fn crcpoly(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "CRC polynomial register"] - pub fn set_crcpoly(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Crcpr { - fn default() -> Crcpr { - Crcpr(0) - } - } - #[doc = "control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2(pub u32); - impl Cr2 { - #[doc = "Rx buffer DMA enable"] - pub const fn rxdmaen(&self) -> bool { + pub struct Ur14(pub u32); + impl Ur14 { + #[doc = "D1 Stop Reset"] + pub const fn d1stprst(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Rx buffer DMA enable"] - pub fn set_rxdmaen(&mut self, val: bool) { + #[doc = "D1 Stop Reset"] + pub fn set_d1stprst(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Tx buffer DMA enable"] - pub const fn txdmaen(&self) -> bool { + } + impl Default for Ur14 { + fn default() -> Ur14 { + Ur14(0) + } + } + #[doc = "SYSCFG user register 5"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur5(pub u32); + impl Ur5 { + #[doc = "Mass erase secured area disabled for bank 1"] + pub const fn mesad_1(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Mass erase secured area disabled for bank 1"] + pub fn set_mesad_1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Write protection for flash bank 1"] + pub const fn wrpn_1(&self) -> u8 { + let val = (self.0 >> 16usize) & 0xff; + val as u8 + } + #[doc = "Write protection for flash bank 1"] + pub fn set_wrpn_1(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); + } + } + impl Default for Ur5 { + fn default() -> Ur5 { + Ur5(0) + } + } + #[doc = "SYSCFG user register 8"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur8(pub u32); + impl Ur8 { + #[doc = "Mass erase protected area disabled for bank 2"] + pub const fn mepad_2(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Mass erase protected area disabled for bank 2"] + pub fn set_mepad_2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Mass erase secured area disabled for bank 2"] + pub const fn mesad_2(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Mass erase secured area disabled for bank 2"] + pub fn set_mesad_2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur8 { + fn default() -> Ur8 { + Ur8(0) + } + } + #[doc = "peripheral mode configuration register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pmcr(pub u32); + impl Pmcr { + #[doc = "I2C1 Fm+"] + pub const fn i2c1fmp(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "I2C1 Fm+"] + pub fn set_i2c1fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "I2C2 Fm+"] + pub const fn i2c2fmp(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Tx buffer DMA enable"] - pub fn set_txdmaen(&mut self, val: bool) { + #[doc = "I2C2 Fm+"] + pub fn set_i2c2fmp(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "SS output enable"] - pub const fn ssoe(&self) -> bool { + #[doc = "I2C3 Fm+"] + pub const fn i2c3fmp(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "SS output enable"] - pub fn set_ssoe(&mut self, val: bool) { + #[doc = "I2C3 Fm+"] + pub fn set_i2c3fmp(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Frame format"] - pub const fn frf(&self) -> super::vals::Frf { + #[doc = "I2C4 Fm+"] + pub const fn i2c4fmp(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "I2C4 Fm+"] + pub fn set_i2c4fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "PB(6) Fm+"] + pub const fn pb6fmp(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; - super::vals::Frf(val as u8) + val != 0 } - #[doc = "Frame format"] - pub fn set_frf(&mut self, val: super::vals::Frf) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + #[doc = "PB(6) Fm+"] + pub fn set_pb6fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Error interrupt enable"] - pub const fn errie(&self) -> bool { + #[doc = "PB(7) Fast Mode Plus"] + pub const fn pb7fmp(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Error interrupt enable"] - pub fn set_errie(&mut self, val: bool) { + #[doc = "PB(7) Fast Mode Plus"] + pub fn set_pb7fmp(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "RX buffer not empty interrupt enable"] - pub const fn rxneie(&self) -> bool { + #[doc = "PB(8) Fast Mode Plus"] + pub const fn pb8fmp(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "RX buffer not empty interrupt enable"] - pub fn set_rxneie(&mut self, val: bool) { + #[doc = "PB(8) Fast Mode Plus"] + pub fn set_pb8fmp(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "Tx buffer empty interrupt enable"] - pub const fn txeie(&self) -> bool { + #[doc = "PB(9) Fm+"] + pub const fn pb9fmp(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Tx buffer empty interrupt enable"] - pub fn set_txeie(&mut self, val: bool) { + #[doc = "PB(9) Fm+"] + pub fn set_pb9fmp(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - } - impl Default for Cr2 { - fn default() -> Cr2 { - Cr2(0) - } - } - #[doc = "control register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1(pub u32); - impl Cr1 { - #[doc = "Clock phase"] - pub const fn cpha(&self) -> super::vals::Cpha { - let val = (self.0 >> 0usize) & 0x01; - super::vals::Cpha(val as u8) - } - #[doc = "Clock phase"] - pub fn set_cpha(&mut self, val: super::vals::Cpha) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); - } - #[doc = "Clock polarity"] - pub const fn cpol(&self) -> super::vals::Cpol { - let val = (self.0 >> 1usize) & 0x01; - super::vals::Cpol(val as u8) - } - #[doc = "Clock polarity"] - pub fn set_cpol(&mut self, val: super::vals::Cpol) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); - } - #[doc = "Master selection"] - pub const fn mstr(&self) -> super::vals::Mstr { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Mstr(val as u8) - } - #[doc = "Master selection"] - pub fn set_mstr(&mut self, val: super::vals::Mstr) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "Baud rate control"] - pub const fn br(&self) -> super::vals::Br { - let val = (self.0 >> 3usize) & 0x07; - super::vals::Br(val as u8) - } - #[doc = "Baud rate control"] - pub fn set_br(&mut self, val: super::vals::Br) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); - } - #[doc = "SPI enable"] - pub const fn spe(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "SPI enable"] - pub fn set_spe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Frame format"] - pub const fn lsbfirst(&self) -> super::vals::Lsbfirst { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Lsbfirst(val as u8) - } - #[doc = "Frame format"] - pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Internal slave select"] - pub const fn ssi(&self) -> bool { + #[doc = "Booster Enable"] + pub const fn booste(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "Internal slave select"] - pub fn set_ssi(&mut self, val: bool) { + #[doc = "Booster Enable"] + pub fn set_booste(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } - #[doc = "Software slave management"] - pub const fn ssm(&self) -> bool { + #[doc = "Analog switch supply voltage selection"] + pub const fn boostvddsel(&self) -> bool { let val = (self.0 >> 9usize) & 0x01; val != 0 } - #[doc = "Software slave management"] - pub fn set_ssm(&mut self, val: bool) { + #[doc = "Analog switch supply voltage selection"] + pub fn set_boostvddsel(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); } - #[doc = "Receive only"] - pub const fn rxonly(&self) -> super::vals::Rxonly { - let val = (self.0 >> 10usize) & 0x01; - super::vals::Rxonly(val as u8) + #[doc = "Ethernet PHY Interface Selection"] + pub const fn epis(&self) -> u8 { + let val = (self.0 >> 21usize) & 0x07; + val as u8 } - #[doc = "Receive only"] - pub fn set_rxonly(&mut self, val: super::vals::Rxonly) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + #[doc = "Ethernet PHY Interface Selection"] + pub fn set_epis(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 21usize)) | (((val as u32) & 0x07) << 21usize); } - #[doc = "Data frame format"] - pub const fn dff(&self) -> super::vals::Dff { - let val = (self.0 >> 11usize) & 0x01; - super::vals::Dff(val as u8) - } - #[doc = "Data frame format"] - pub fn set_dff(&mut self, val: super::vals::Dff) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); - } - #[doc = "CRC transfer next"] - pub const fn crcnext(&self) -> super::vals::Crcnext { - let val = (self.0 >> 12usize) & 0x01; - super::vals::Crcnext(val as u8) - } - #[doc = "CRC transfer next"] - pub fn set_crcnext(&mut self, val: super::vals::Crcnext) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); - } - #[doc = "Hardware CRC calculation enable"] - pub const fn crcen(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; + #[doc = "PA0 Switch Open"] + pub const fn pa0so(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; val != 0 } - #[doc = "Hardware CRC calculation enable"] - pub fn set_crcen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + #[doc = "PA0 Switch Open"] + pub fn set_pa0so(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); } - #[doc = "Output enable in bidirectional mode"] - pub const fn bidioe(&self) -> super::vals::Bidioe { - let val = (self.0 >> 14usize) & 0x01; - super::vals::Bidioe(val as u8) + #[doc = "PA1 Switch Open"] + pub const fn pa1so(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 } - #[doc = "Output enable in bidirectional mode"] - pub fn set_bidioe(&mut self, val: super::vals::Bidioe) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + #[doc = "PA1 Switch Open"] + pub fn set_pa1so(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); } - #[doc = "Bidirectional data mode enable"] - pub const fn bidimode(&self) -> super::vals::Bidimode { - let val = (self.0 >> 15usize) & 0x01; - super::vals::Bidimode(val as u8) + #[doc = "PC2 Switch Open"] + pub const fn pc2so(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 } - #[doc = "Bidirectional data mode enable"] - pub fn set_bidimode(&mut self, val: super::vals::Bidimode) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + #[doc = "PC2 Switch Open"] + pub fn set_pc2so(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "PC3 Switch Open"] + pub const fn pc3so(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "PC3 Switch Open"] + pub fn set_pc3so(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); } } - impl Default for Cr1 { - fn default() -> Cr1 { - Cr1(0) + impl Default for Pmcr { + fn default() -> Pmcr { + Pmcr(0) } } - #[doc = "data register"] + #[doc = "SYSCFG user register 12"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dr(pub u32); - impl Dr { - #[doc = "Data register"] - pub const fn dr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 + pub struct Ur12(pub u32); + impl Ur12 { + #[doc = "Secure mode"] + pub const fn secure(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 } - #[doc = "Data register"] - pub fn set_dr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + #[doc = "Secure mode"] + pub fn set_secure(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } } - impl Default for Dr { - fn default() -> Dr { - Dr(0) + impl Default for Ur12 { + fn default() -> Ur12 { + Ur12(0) + } + } + #[doc = "SYSCFG user register 4"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur4(pub u32); + impl Ur4 { + #[doc = "Mass Erase Protected Area Disabled for bank 1"] + pub const fn mepad_1(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Mass Erase Protected Area Disabled for bank 1"] + pub fn set_mepad_1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur4 { + fn default() -> Ur4 { + Ur4(0) + } + } + #[doc = "SYSCFG compensation cell value register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccvr(pub u32); + impl Ccvr { + #[doc = "NMOS compensation value"] + pub const fn ncv(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "NMOS compensation value"] + pub fn set_ncv(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "PMOS compensation value"] + pub const fn pcv(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "PMOS compensation value"] + pub fn set_pcv(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + } + impl Default for Ccvr { + fn default() -> Ccvr { + Ccvr(0) + } + } + #[doc = "SYSCFG user register 13"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur13(pub u32); + impl Ur13 { + #[doc = "Secured DTCM RAM Size"] + pub const fn sdrs(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x03; + val as u8 + } + #[doc = "Secured DTCM RAM Size"] + pub fn set_sdrs(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); + } + #[doc = "D1 Standby reset"] + pub const fn d1sbrst(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "D1 Standby reset"] + pub fn set_d1sbrst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur13 { + fn default() -> Ur13 { + Ur13(0) + } + } + #[doc = "compensation cell control/status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cccsr(pub u32); + impl Cccsr { + #[doc = "enable"] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "enable"] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Code selection"] + pub const fn cs(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Code selection"] + pub fn set_cs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Compensation cell ready flag"] + pub const fn ready(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Compensation cell ready flag"] + pub fn set_ready(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "High-speed at low-voltage"] + pub const fn hslv(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "High-speed at low-voltage"] + pub fn set_hslv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Cccsr { + fn default() -> Cccsr { + Cccsr(0) + } + } + #[doc = "SYSCFG user register 6"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur6(pub u32); + impl Ur6 { + #[doc = "Protected area start address for bank 1"] + pub const fn pa_beg_1(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area start address for bank 1"] + pub fn set_pa_beg_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Protected area end address for bank 1"] + pub const fn pa_end_1(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area end address for bank 1"] + pub fn set_pa_end_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur6 { + fn default() -> Ur6 { + Ur6(0) + } + } + #[doc = "SYSCFG package register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pkgr(pub u32); + impl Pkgr { + #[doc = "Package"] + pub const fn pkg(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Package"] + pub fn set_pkg(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + } + impl Default for Pkgr { + fn default() -> Pkgr { + Pkgr(0) + } + } + #[doc = "SYSCFG user register 10"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur10(pub u32); + impl Ur10 { + #[doc = "Protected area end address for bank 2"] + pub const fn pa_end_2(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area end address for bank 2"] + pub fn set_pa_end_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Secured area start address for bank 2"] + pub const fn sa_beg_2(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area start address for bank 2"] + pub fn set_sa_beg_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur10 { + fn default() -> Ur10 { + Ur10(0) + } + } + #[doc = "external interrupt configuration register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Exticr(pub u32); + impl Exticr { + #[doc = "EXTI x configuration (x = 4 to 7)"] + pub fn exti(&self, n: usize) -> u8 { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + val as u8 + } + #[doc = "EXTI x configuration (x = 4 to 7)"] + pub fn set_exti(&mut self, n: usize, val: u8) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); + } + } + impl Default for Exticr { + fn default() -> Exticr { + Exticr(0) + } + } + #[doc = "SYSCFG user register 15"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur15(pub u32); + impl Ur15 { + #[doc = "Freeze independent watchdog in Standby mode"] + pub const fn fziwdgstb(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Freeze independent watchdog in Standby mode"] + pub fn set_fziwdgstb(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur15 { + fn default() -> Ur15 { + Ur15(0) + } + } + #[doc = "SYSCFG user register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur3(pub u32); + impl Ur3 { + #[doc = "Boot Address 1"] + pub const fn boot_add1(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "Boot Address 1"] + pub fn set_boot_add1(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + } + } + impl Default for Ur3 { + fn default() -> Ur3 { + Ur3(0) + } + } + #[doc = "SYSCFG user register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur2(pub u32); + impl Ur2 { + #[doc = "BOR_LVL Brownout Reset Threshold Level"] + pub const fn borh(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x03; + val as u8 + } + #[doc = "BOR_LVL Brownout Reset Threshold Level"] + pub fn set_borh(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); + } + #[doc = "Boot Address 0"] + pub const fn boot_add0(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "Boot Address 0"] + pub fn set_boot_add0(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + } + } + impl Default for Ur2 { + fn default() -> Ur2 { + Ur2(0) + } + } + #[doc = "SYSCFG user register 17"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur17(pub u32); + impl Ur17 { + #[doc = "I/O high speed / low voltage"] + pub const fn io_hslv(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "I/O high speed / low voltage"] + pub fn set_io_hslv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for Ur17 { + fn default() -> Ur17 { + Ur17(0) + } + } + #[doc = "SYSCFG user register 9"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur9(pub u32); + impl Ur9 { + #[doc = "Write protection for flash bank 2"] + pub const fn wrpn_2(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Write protection for flash bank 2"] + pub fn set_wrpn_2(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Protected area start address for bank 2"] + pub const fn pa_beg_2(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area start address for bank 2"] + pub fn set_pa_beg_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur9 { + fn default() -> Ur9 { + Ur9(0) + } + } + #[doc = "SYSCFG compensation cell code register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cccr(pub u32); + impl Cccr { + #[doc = "NMOS compensation code"] + pub const fn ncc(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "NMOS compensation code"] + pub fn set_ncc(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "PMOS compensation code"] + pub const fn pcc(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "PMOS compensation code"] + pub fn set_pcc(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + } + impl Default for Cccr { + fn default() -> Cccr { + Cccr(0) + } + } + #[doc = "SYSCFG user register 11"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur11(pub u32); + impl Ur11 { + #[doc = "Secured area end address for bank 2"] + pub const fn sa_end_2(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area end address for bank 2"] + pub fn set_sa_end_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Independent Watchdog 1 mode"] + pub const fn iwdg1m(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Independent Watchdog 1 mode"] + pub fn set_iwdg1m(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur11 { + fn default() -> Ur11 { + Ur11(0) + } + } + #[doc = "SYSCFG user register 16"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur16(pub u32); + impl Ur16 { + #[doc = "Freeze independent watchdog in Stop mode"] + pub const fn fziwdgstp(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Freeze independent watchdog in Stop mode"] + pub fn set_fziwdgstp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Private key programmed"] + pub const fn pkp(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Private key programmed"] + pub fn set_pkp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur16 { + fn default() -> Ur16 { + Ur16(0) + } + } + #[doc = "SYSCFG user register 7"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur7(pub u32); + impl Ur7 { + #[doc = "Secured area start address for bank 1"] + pub const fn sa_beg_1(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area start address for bank 1"] + pub fn set_sa_beg_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Secured area end address for bank 1"] + pub const fn sa_end_1(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area end address for bank 1"] + pub fn set_sa_end_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur7 { + fn default() -> Ur7 { + Ur7(0) } } } @@ -1356,76 +967,8 @@ pub mod exti_v1 { unsafe { Reg::from_ptr(self.0.add(20usize)) } } } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Prr(pub u8); - impl Prr { - #[doc = "No trigger request occurred"] - pub const NOTPENDING: Self = Self(0); - #[doc = "Selected trigger request occurred"] - pub const PENDING: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Prw(pub u8); - impl Prw { - #[doc = "Clears pending bit"] - pub const CLEAR: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Swierw(pub u8); - impl Swierw { - #[doc = "Generates an interrupt request"] - pub const PEND: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mr(pub u8); - impl Mr { - #[doc = "Interrupt request line is masked"] - pub const MASKED: Self = Self(0); - #[doc = "Interrupt request line is unmasked"] - pub const UNMASKED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Tr(pub u8); - impl Tr { - #[doc = "Falling edge trigger is disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Falling edge trigger is enabled"] - pub const ENABLED: Self = Self(0x01); - } - } pub mod regs { use crate::generic::*; - #[doc = "Rising Trigger selection register (EXTI_RTSR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Rtsr(pub u32); - impl Rtsr { - #[doc = "Rising trigger event configuration of line 0"] - pub fn tr(&self, n: usize) -> super::vals::Tr { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Tr(val as u8) - } - #[doc = "Rising trigger event configuration of line 0"] - pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Rtsr { - fn default() -> Rtsr { - Rtsr(0) - } - } #[doc = "Falling Trigger selection register (EXTI_FTSR)"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1450,28 +993,28 @@ pub mod exti_v1 { Ftsr(0) } } - #[doc = "Interrupt mask register (EXTI_IMR)"] + #[doc = "Event mask register (EXTI_EMR)"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Imr(pub u32); - impl Imr { - #[doc = "Interrupt Mask on line 0"] + pub struct Emr(pub u32); + impl Emr { + #[doc = "Event Mask on line 0"] pub fn mr(&self, n: usize) -> super::vals::Mr { assert!(n < 23usize); let offs = 0usize + n * 1usize; let val = (self.0 >> offs) & 0x01; super::vals::Mr(val as u8) } - #[doc = "Interrupt Mask on line 0"] + #[doc = "Event Mask on line 0"] pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { assert!(n < 23usize); let offs = 0usize + n * 1usize; self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); } } - impl Default for Imr { - fn default() -> Imr { - Imr(0) + impl Default for Emr { + fn default() -> Emr { + Emr(0) } } #[doc = "Pending register (EXTI_PR)"] @@ -1522,316 +1065,52 @@ pub mod exti_v1 { Swier(0) } } - #[doc = "Event mask register (EXTI_EMR)"] + #[doc = "Interrupt mask register (EXTI_IMR)"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Emr(pub u32); - impl Emr { - #[doc = "Event Mask on line 0"] + pub struct Imr(pub u32); + impl Imr { + #[doc = "Interrupt Mask on line 0"] pub fn mr(&self, n: usize) -> super::vals::Mr { assert!(n < 23usize); let offs = 0usize + n * 1usize; let val = (self.0 >> offs) & 0x01; super::vals::Mr(val as u8) } - #[doc = "Event Mask on line 0"] + #[doc = "Interrupt Mask on line 0"] pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { assert!(n < 23usize); let offs = 0usize + n * 1usize; self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); } } - impl Default for Emr { - fn default() -> Emr { - Emr(0) + impl Default for Imr { + fn default() -> Imr { + Imr(0) } } - } -} -pub mod gpio_v2 { - use crate::generic::*; - #[doc = "General-purpose I/Os"] - #[derive(Copy, Clone)] - pub struct Gpio(pub *mut u8); - unsafe impl Send for Gpio {} - unsafe impl Sync for Gpio {} - impl Gpio { - #[doc = "GPIO port mode register"] - pub fn moder(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "GPIO port output type register"] - pub fn otyper(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "GPIO port output speed register"] - pub fn ospeedr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "GPIO port pull-up/pull-down register"] - pub fn pupdr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "GPIO port input data register"] - pub fn idr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "GPIO port output data register"] - pub fn odr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "GPIO port bit set/reset register"] - pub fn bsrr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } - } - #[doc = "GPIO port configuration lock register"] - pub fn lckr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(28usize)) } - } - #[doc = "GPIO alternate function register (low, high)"] - pub fn afr(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(32usize + n * 4usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "GPIO port pull-up/pull-down register"] + #[doc = "Rising Trigger selection register (EXTI_RTSR)"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pupdr(pub u32); - impl Pupdr { - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn pupdr(&self, n: usize) -> super::vals::Pupdr { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Pupdr(val as u8) - } - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn set_pupdr(&mut self, n: usize, val: super::vals::Pupdr) { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - } - impl Default for Pupdr { - fn default() -> Pupdr { - Pupdr(0) - } - } - #[doc = "GPIO port input data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idr(pub u32); - impl Idr { - #[doc = "Port input data (y = 0..15)"] - pub fn idr(&self, n: usize) -> super::vals::Idr { - assert!(n < 16usize); + pub struct Rtsr(pub u32); + impl Rtsr { + #[doc = "Rising trigger event configuration of line 0"] + pub fn tr(&self, n: usize) -> super::vals::Tr { + assert!(n < 23usize); let offs = 0usize + n * 1usize; let val = (self.0 >> offs) & 0x01; - super::vals::Idr(val as u8) + super::vals::Tr(val as u8) } - #[doc = "Port input data (y = 0..15)"] - pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { - assert!(n < 16usize); + #[doc = "Rising trigger event configuration of line 0"] + pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) { + assert!(n < 23usize); let offs = 0usize + n * 1usize; self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); } } - impl Default for Idr { - fn default() -> Idr { - Idr(0) - } - } - #[doc = "GPIO port bit set/reset register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Bsrr(pub u32); - impl Bsrr { - #[doc = "Port x set bit y (y= 0..15)"] - pub fn bs(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Port x set bit y (y= 0..15)"] - pub fn set_bs(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Port x set bit y (y= 0..15)"] - pub fn br(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 16usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Port x set bit y (y= 0..15)"] - pub fn set_br(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 16usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Bsrr { - fn default() -> Bsrr { - Bsrr(0) - } - } - #[doc = "GPIO port output type register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Otyper(pub u32); - impl Otyper { - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn ot(&self, n: usize) -> super::vals::Ot { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Ot(val as u8) - } - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn set_ot(&mut self, n: usize, val: super::vals::Ot) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Otyper { - fn default() -> Otyper { - Otyper(0) - } - } - #[doc = "GPIO port output speed register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ospeedr(pub u32); - impl Ospeedr { - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Ospeedr(val as u8) - } - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - } - impl Default for Ospeedr { - fn default() -> Ospeedr { - Ospeedr(0) - } - } - #[doc = "GPIO port output data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Odr(pub u32); - impl Odr { - #[doc = "Port output data (y = 0..15)"] - pub fn odr(&self, n: usize) -> super::vals::Odr { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Odr(val as u8) - } - #[doc = "Port output data (y = 0..15)"] - pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Odr { - fn default() -> Odr { - Odr(0) - } - } - #[doc = "GPIO alternate function register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Afr(pub u32); - impl Afr { - #[doc = "Alternate function selection for port x bit y (y = 0..15)"] - pub fn afr(&self, n: usize) -> super::vals::Afr { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x0f; - super::vals::Afr(val as u8) - } - #[doc = "Alternate function selection for port x bit y (y = 0..15)"] - pub fn set_afr(&mut self, n: usize, val: super::vals::Afr) { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); - } - } - impl Default for Afr { - fn default() -> Afr { - Afr(0) - } - } - #[doc = "GPIO port configuration lock register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Lckr(pub u32); - impl Lckr { - #[doc = "Port x lock bit y (y= 0..15)"] - pub fn lck(&self, n: usize) -> super::vals::Lck { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Lck(val as u8) - } - #[doc = "Port x lock bit y (y= 0..15)"] - pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - #[doc = "Port x lock bit y (y= 0..15)"] - pub const fn lckk(&self) -> super::vals::Lckk { - let val = (self.0 >> 16usize) & 0x01; - super::vals::Lckk(val as u8) - } - #[doc = "Port x lock bit y (y= 0..15)"] - pub fn set_lckk(&mut self, val: super::vals::Lckk) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); - } - } - impl Default for Lckr { - fn default() -> Lckr { - Lckr(0) - } - } - #[doc = "GPIO port mode register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Moder(pub u32); - impl Moder { - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn moder(&self, n: usize) -> super::vals::Moder { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Moder(val as u8) - } - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - } - impl Default for Moder { - fn default() -> Moder { - Moder(0) + impl Default for Rtsr { + fn default() -> Rtsr { + Rtsr(0) } } } @@ -1839,136 +1118,44 @@ pub mod gpio_v2 { use crate::generic::*; #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Brw(pub u8); - impl Brw { - #[doc = "Resets the corresponding ODRx bit"] - pub const RESET: Self = Self(0x01); + pub struct Prr(pub u8); + impl Prr { + #[doc = "No trigger request occurred"] + pub const NOTPENDING: Self = Self(0); + #[doc = "Selected trigger request occurred"] + pub const PENDING: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Moder(pub u8); - impl Moder { - #[doc = "Input mode (reset state)"] - pub const INPUT: Self = Self(0); - #[doc = "General purpose output mode"] - pub const OUTPUT: Self = Self(0x01); - #[doc = "Alternate function mode"] - pub const ALTERNATE: Self = Self(0x02); - #[doc = "Analog mode"] - pub const ANALOG: Self = Self(0x03); + pub struct Swierw(pub u8); + impl Swierw { + #[doc = "Generates an interrupt request"] + pub const PEND: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pupdr(pub u8); - impl Pupdr { - #[doc = "No pull-up, pull-down"] - pub const FLOATING: Self = Self(0); - #[doc = "Pull-up"] - pub const PULLUP: Self = Self(0x01); - #[doc = "Pull-down"] - pub const PULLDOWN: Self = Self(0x02); + pub struct Tr(pub u8); + impl Tr { + #[doc = "Falling edge trigger is disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Falling edge trigger is enabled"] + pub const ENABLED: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lckk(pub u8); - impl Lckk { - #[doc = "Port configuration lock key not active"] - pub const NOTACTIVE: Self = Self(0); - #[doc = "Port configuration lock key active"] - pub const ACTIVE: Self = Self(0x01); + pub struct Mr(pub u8); + impl Mr { + #[doc = "Interrupt request line is masked"] + pub const MASKED: Self = Self(0); + #[doc = "Interrupt request line is unmasked"] + pub const UNMASKED: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ot(pub u8); - impl Ot { - #[doc = "Output push-pull (reset state)"] - pub const PUSHPULL: Self = Self(0); - #[doc = "Output open-drain"] - pub const OPENDRAIN: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ospeedr(pub u8); - impl Ospeedr { - #[doc = "Low speed"] - pub const LOWSPEED: Self = Self(0); - #[doc = "Medium speed"] - pub const MEDIUMSPEED: Self = Self(0x01); - #[doc = "High speed"] - pub const HIGHSPEED: Self = Self(0x02); - #[doc = "Very high speed"] - pub const VERYHIGHSPEED: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Afr(pub u8); - impl Afr { - #[doc = "AF0"] - pub const AF0: Self = Self(0); - #[doc = "AF1"] - pub const AF1: Self = Self(0x01); - #[doc = "AF2"] - pub const AF2: Self = Self(0x02); - #[doc = "AF3"] - pub const AF3: Self = Self(0x03); - #[doc = "AF4"] - pub const AF4: Self = Self(0x04); - #[doc = "AF5"] - pub const AF5: Self = Self(0x05); - #[doc = "AF6"] - pub const AF6: Self = Self(0x06); - #[doc = "AF7"] - pub const AF7: Self = Self(0x07); - #[doc = "AF8"] - pub const AF8: Self = Self(0x08); - #[doc = "AF9"] - pub const AF9: Self = Self(0x09); - #[doc = "AF10"] - pub const AF10: Self = Self(0x0a); - #[doc = "AF11"] - pub const AF11: Self = Self(0x0b); - #[doc = "AF12"] - pub const AF12: Self = Self(0x0c); - #[doc = "AF13"] - pub const AF13: Self = Self(0x0d); - #[doc = "AF14"] - pub const AF14: Self = Self(0x0e); - #[doc = "AF15"] - pub const AF15: Self = Self(0x0f); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Idr(pub u8); - impl Idr { - #[doc = "Input is logic low"] - pub const LOW: Self = Self(0); - #[doc = "Input is logic high"] - pub const HIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lck(pub u8); - impl Lck { - #[doc = "Port configuration not locked"] - pub const UNLOCKED: Self = Self(0); - #[doc = "Port configuration locked"] - pub const LOCKED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Odr(pub u8); - impl Odr { - #[doc = "Set output to logic low"] - pub const LOW: Self = Self(0); - #[doc = "Set output to logic high"] - pub const HIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bsw(pub u8); - impl Bsw { - #[doc = "Sets the corresponding ODRx bit"] - pub const SET: Self = Self(0x01); + pub struct Prw(pub u8); + impl Prw { + #[doc = "Clears pending bit"] + pub const CLEAR: Self = Self(0x01); } } } @@ -2027,150 +1214,6 @@ pub mod dma_v2 { unsafe { Reg::from_ptr(self.0.add(20usize)) } } } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Fth(pub u8); - impl Fth { - #[doc = "1/4 full FIFO"] - pub const QUARTER: Self = Self(0); - #[doc = "1/2 full FIFO"] - pub const HALF: Self = Self(0x01); - #[doc = "3/4 full FIFO"] - pub const THREEQUARTERS: Self = Self(0x02); - #[doc = "Full FIFO"] - pub const FULL: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pincos(pub u8); - impl Pincos { - #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] - pub const PSIZE: Self = Self(0); - #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] - pub const FIXED4: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Size(pub u8); - impl Size { - #[doc = "Byte (8-bit)"] - pub const BITS8: Self = Self(0); - #[doc = "Half-word (16-bit)"] - pub const BITS16: Self = Self(0x01); - #[doc = "Word (32-bit)"] - pub const BITS32: Self = Self(0x02); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dbm(pub u8); - impl Dbm { - #[doc = "No buffer switching at the end of transfer"] - pub const DISABLED: Self = Self(0); - #[doc = "Memory target switched at the end of the DMA transfer"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pl(pub u8); - impl Pl { - #[doc = "Low"] - pub const LOW: Self = Self(0); - #[doc = "Medium"] - pub const MEDIUM: Self = Self(0x01); - #[doc = "High"] - pub const HIGH: Self = Self(0x02); - #[doc = "Very high"] - pub const VERYHIGH: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dmdis(pub u8); - impl Dmdis { - #[doc = "Direct mode is enabled"] - pub const ENABLED: Self = Self(0); - #[doc = "Direct mode is disabled"] - pub const DISABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Burst(pub u8); - impl Burst { - #[doc = "Single transfer"] - pub const SINGLE: Self = Self(0); - #[doc = "Incremental burst of 4 beats"] - pub const INCR4: Self = Self(0x01); - #[doc = "Incremental burst of 8 beats"] - pub const INCR8: Self = Self(0x02); - #[doc = "Incremental burst of 16 beats"] - pub const INCR16: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dir(pub u8); - impl Dir { - #[doc = "Peripheral-to-memory"] - pub const PERIPHERALTOMEMORY: Self = Self(0); - #[doc = "Memory-to-peripheral"] - pub const MEMORYTOPERIPHERAL: Self = Self(0x01); - #[doc = "Memory-to-memory"] - pub const MEMORYTOMEMORY: Self = Self(0x02); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Circ(pub u8); - impl Circ { - #[doc = "Circular mode disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Circular mode enabled"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ct(pub u8); - impl Ct { - #[doc = "The current target memory is Memory 0"] - pub const MEMORY0: Self = Self(0); - #[doc = "The current target memory is Memory 1"] - pub const MEMORY1: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Inc(pub u8); - impl Inc { - #[doc = "Address pointer is fixed"] - pub const FIXED: Self = Self(0); - #[doc = "Address pointer is incremented after each data transfer"] - pub const INCREMENTED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Fs(pub u8); - impl Fs { - #[doc = "0 < fifo_level < 1/4"] - pub const QUARTER1: Self = Self(0); - #[doc = "1/4 <= fifo_level < 1/2"] - pub const QUARTER2: Self = Self(0x01); - #[doc = "1/2 <= fifo_level < 3/4"] - pub const QUARTER3: Self = Self(0x02); - #[doc = "3/4 <= fifo_level < full"] - pub const QUARTER4: Self = Self(0x03); - #[doc = "FIFO is empty"] - pub const EMPTY: Self = Self(0x04); - #[doc = "FIFO is full"] - pub const FULL: Self = Self(0x05); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pfctrl(pub u8); - impl Pfctrl { - #[doc = "The DMA is the flow controller"] - pub const DMA: Self = Self(0); - #[doc = "The peripheral is the flow controller"] - pub const PERIPHERAL: Self = Self(0x01); - } - } pub mod regs { use crate::generic::*; #[doc = "stream x number of data register"] @@ -2193,6 +1236,53 @@ pub mod dma_v2 { Ndtr(0) } } + #[doc = "stream x FIFO control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Fcr(pub u32); + impl Fcr { + #[doc = "FIFO threshold selection"] + pub const fn fth(&self) -> super::vals::Fth { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Fth(val as u8) + } + #[doc = "FIFO threshold selection"] + pub fn set_fth(&mut self, val: super::vals::Fth) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize); + } + #[doc = "Direct mode disable"] + pub const fn dmdis(&self) -> super::vals::Dmdis { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Dmdis(val as u8) + } + #[doc = "Direct mode disable"] + pub fn set_dmdis(&mut self, val: super::vals::Dmdis) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "FIFO status"] + pub const fn fs(&self) -> super::vals::Fs { + let val = (self.0 >> 3usize) & 0x07; + super::vals::Fs(val as u8) + } + #[doc = "FIFO status"] + pub fn set_fs(&mut self, val: super::vals::Fs) { + self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); + } + #[doc = "FIFO error interrupt enable"] + pub const fn feie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "FIFO error interrupt enable"] + pub fn set_feie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for Fcr { + fn default() -> Fcr { + Fcr(0) + } + } #[doc = "low interrupt flag clear register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -2269,129 +1359,6 @@ pub mod dma_v2 { Ifcr(0) } } - #[doc = "stream x FIFO control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Fcr(pub u32); - impl Fcr { - #[doc = "FIFO threshold selection"] - pub const fn fth(&self) -> super::vals::Fth { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Fth(val as u8) - } - #[doc = "FIFO threshold selection"] - pub fn set_fth(&mut self, val: super::vals::Fth) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize); - } - #[doc = "Direct mode disable"] - pub const fn dmdis(&self) -> super::vals::Dmdis { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Dmdis(val as u8) - } - #[doc = "Direct mode disable"] - pub fn set_dmdis(&mut self, val: super::vals::Dmdis) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "FIFO status"] - pub const fn fs(&self) -> super::vals::Fs { - let val = (self.0 >> 3usize) & 0x07; - super::vals::Fs(val as u8) - } - #[doc = "FIFO status"] - pub fn set_fs(&mut self, val: super::vals::Fs) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); - } - #[doc = "FIFO error interrupt enable"] - pub const fn feie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "FIFO error interrupt enable"] - pub fn set_feie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - } - impl Default for Fcr { - fn default() -> Fcr { - Fcr(0) - } - } - #[doc = "low interrupt status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Isr(pub u32); - impl Isr { - #[doc = "Stream x FIFO error interrupt flag (x=3..0)"] - pub fn feif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x FIFO error interrupt flag (x=3..0)"] - pub fn set_feif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x direct mode error interrupt flag (x=3..0)"] - pub fn dmeif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x direct mode error interrupt flag (x=3..0)"] - pub fn set_dmeif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x transfer error interrupt flag (x=3..0)"] - pub fn teif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x transfer error interrupt flag (x=3..0)"] - pub fn set_teif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x half transfer interrupt flag (x=3..0)"] - pub fn htif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x half transfer interrupt flag (x=3..0)"] - pub fn set_htif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"] - pub fn tcif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"] - pub fn set_tcif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Isr { - fn default() -> Isr { - Isr(0) - } - } #[doc = "stream x configuration register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -2574,322 +1541,242 @@ pub mod dma_v2 { Cr(0) } } - } -} -pub mod gpio_v1 { - use crate::generic::*; - #[doc = "General purpose I/O"] - #[derive(Copy, Clone)] - pub struct Gpio(pub *mut u8); - unsafe impl Send for Gpio {} - unsafe impl Sync for Gpio {} - impl Gpio { - #[doc = "Port configuration register low (GPIOn_CRL)"] - pub fn cr(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) } + #[doc = "low interrupt status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Isr(pub u32); + impl Isr { + #[doc = "Stream x FIFO error interrupt flag (x=3..0)"] + pub fn feif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x FIFO error interrupt flag (x=3..0)"] + pub fn set_feif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x direct mode error interrupt flag (x=3..0)"] + pub fn dmeif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x direct mode error interrupt flag (x=3..0)"] + pub fn set_dmeif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x transfer error interrupt flag (x=3..0)"] + pub fn teif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x transfer error interrupt flag (x=3..0)"] + pub fn set_teif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x half transfer interrupt flag (x=3..0)"] + pub fn htif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x half transfer interrupt flag (x=3..0)"] + pub fn set_htif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"] + pub fn tcif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"] + pub fn set_tcif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } } - #[doc = "Port input data register (GPIOn_IDR)"] - pub fn idr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "Port output data register (GPIOn_ODR)"] - pub fn odr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "Port bit set/reset register (GPIOn_BSRR)"] - pub fn bsrr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "Port bit reset register (GPIOn_BRR)"] - pub fn brr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "Port configuration lock register"] - pub fn lckr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } + impl Default for Isr { + fn default() -> Isr { + Isr(0) + } } } pub mod vals { use crate::generic::*; #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Brw(pub u8); - impl Brw { - #[doc = "No action on the corresponding ODx bit"] - pub const NOACTION: Self = Self(0); - #[doc = "Reset the ODx bit"] - pub const RESET: Self = Self(0x01); + pub struct Burst(pub u8); + impl Burst { + #[doc = "Single transfer"] + pub const SINGLE: Self = Self(0); + #[doc = "Incremental burst of 4 beats"] + pub const INCR4: Self = Self(0x01); + #[doc = "Incremental burst of 8 beats"] + pub const INCR8: Self = Self(0x02); + #[doc = "Incremental burst of 16 beats"] + pub const INCR16: Self = Self(0x03); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bsw(pub u8); - impl Bsw { - #[doc = "No action on the corresponding ODx bit"] - pub const NOACTION: Self = Self(0); - #[doc = "Sets the corresponding ODRx bit"] - pub const SET: Self = Self(0x01); + pub struct Pincos(pub u8); + impl Pincos { + #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] + pub const PSIZE: Self = Self(0); + #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] + pub const FIXED4: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mode(pub u8); - impl Mode { - #[doc = "Input mode (reset state)"] - pub const INPUT: Self = Self(0); - #[doc = "Output mode 10 MHz"] - pub const OUTPUT: Self = Self(0x01); - #[doc = "Output mode 2 MHz"] - pub const OUTPUT2: Self = Self(0x02); - #[doc = "Output mode 50 MHz"] - pub const OUTPUT50: Self = Self(0x03); + pub struct Size(pub u8); + impl Size { + #[doc = "Byte (8-bit)"] + pub const BITS8: Self = Self(0); + #[doc = "Half-word (16-bit)"] + pub const BITS16: Self = Self(0x01); + #[doc = "Word (32-bit)"] + pub const BITS32: Self = Self(0x02); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cnf(pub u8); - impl Cnf { - #[doc = "Analog mode / Push-Pull mode"] - pub const PUSHPULL: Self = Self(0); - #[doc = "Floating input (reset state) / Open Drain-Mode"] - pub const OPENDRAIN: Self = Self(0x01); - #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"] - pub const ALTPUSHPULL: Self = Self(0x02); - #[doc = "Alternate Function Open-Drain Mode"] - pub const ALTOPENDRAIN: Self = Self(0x03); + pub struct Dmdis(pub u8); + impl Dmdis { + #[doc = "Direct mode is enabled"] + pub const ENABLED: Self = Self(0); + #[doc = "Direct mode is disabled"] + pub const DISABLED: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lckk(pub u8); - impl Lckk { - #[doc = "Port configuration lock key not active"] - pub const NOTACTIVE: Self = Self(0); - #[doc = "Port configuration lock key active"] - pub const ACTIVE: Self = Self(0x01); + pub struct Fth(pub u8); + impl Fth { + #[doc = "1/4 full FIFO"] + pub const QUARTER: Self = Self(0); + #[doc = "1/2 full FIFO"] + pub const HALF: Self = Self(0x01); + #[doc = "3/4 full FIFO"] + pub const THREEQUARTERS: Self = Self(0x02); + #[doc = "Full FIFO"] + pub const FULL: Self = Self(0x03); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Odr(pub u8); - impl Odr { - #[doc = "Set output to logic low"] + pub struct Inc(pub u8); + impl Inc { + #[doc = "Address pointer is fixed"] + pub const FIXED: Self = Self(0); + #[doc = "Address pointer is incremented after each data transfer"] + pub const INCREMENTED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Peripheral-to-memory"] + pub const PERIPHERALTOMEMORY: Self = Self(0); + #[doc = "Memory-to-peripheral"] + pub const MEMORYTOPERIPHERAL: Self = Self(0x01); + #[doc = "Memory-to-memory"] + pub const MEMORYTOMEMORY: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dbm(pub u8); + impl Dbm { + #[doc = "No buffer switching at the end of transfer"] + pub const DISABLED: Self = Self(0); + #[doc = "Memory target switched at the end of the DMA transfer"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pfctrl(pub u8); + impl Pfctrl { + #[doc = "The DMA is the flow controller"] + pub const DMA: Self = Self(0); + #[doc = "The peripheral is the flow controller"] + pub const PERIPHERAL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Circ(pub u8); + impl Circ { + #[doc = "Circular mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Circular mode enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Fs(pub u8); + impl Fs { + #[doc = "0 < fifo_level < 1/4"] + pub const QUARTER1: Self = Self(0); + #[doc = "1/4 <= fifo_level < 1/2"] + pub const QUARTER2: Self = Self(0x01); + #[doc = "1/2 <= fifo_level < 3/4"] + pub const QUARTER3: Self = Self(0x02); + #[doc = "3/4 <= fifo_level < full"] + pub const QUARTER4: Self = Self(0x03); + #[doc = "FIFO is empty"] + pub const EMPTY: Self = Self(0x04); + #[doc = "FIFO is full"] + pub const FULL: Self = Self(0x05); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pl(pub u8); + impl Pl { + #[doc = "Low"] pub const LOW: Self = Self(0); - #[doc = "Set output to logic high"] - pub const HIGH: Self = Self(0x01); + #[doc = "Medium"] + pub const MEDIUM: Self = Self(0x01); + #[doc = "High"] + pub const HIGH: Self = Self(0x02); + #[doc = "Very high"] + pub const VERYHIGH: Self = Self(0x03); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Idr(pub u8); - impl Idr { - #[doc = "Input is logic low"] - pub const LOW: Self = Self(0); - #[doc = "Input is logic high"] - pub const HIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lck(pub u8); - impl Lck { - #[doc = "Port configuration not locked"] - pub const UNLOCKED: Self = Self(0); - #[doc = "Port configuration locked"] - pub const LOCKED: Self = Self(0x01); - } - } - pub mod regs { - use crate::generic::*; - #[doc = "Port input data register (GPIOn_IDR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idr(pub u32); - impl Idr { - #[doc = "Port input data"] - pub fn idr(&self, n: usize) -> super::vals::Idr { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Idr(val as u8) - } - #[doc = "Port input data"] - pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Idr { - fn default() -> Idr { - Idr(0) - } - } - #[doc = "Port bit reset register (GPIOn_BRR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Brr(pub u32); - impl Brr { - #[doc = "Reset bit"] - pub fn br(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Reset bit"] - pub fn set_br(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Brr { - fn default() -> Brr { - Brr(0) - } - } - #[doc = "Port bit set/reset register (GPIOn_BSRR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Bsrr(pub u32); - impl Bsrr { - #[doc = "Set bit"] - pub fn bs(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Set bit"] - pub fn set_bs(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Reset bit"] - pub fn br(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 16usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Reset bit"] - pub fn set_br(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 16usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Bsrr { - fn default() -> Bsrr { - Bsrr(0) - } - } - #[doc = "Port configuration register (GPIOn_CRx)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr(pub u32); - impl Cr { - #[doc = "Port n mode bits"] - pub fn mode(&self, n: usize) -> super::vals::Mode { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Mode(val as u8) - } - #[doc = "Port n mode bits"] - pub fn set_mode(&mut self, n: usize, val: super::vals::Mode) { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - #[doc = "Port n configuration bits"] - pub fn cnf(&self, n: usize) -> super::vals::Cnf { - assert!(n < 8usize); - let offs = 2usize + n * 4usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Cnf(val as u8) - } - #[doc = "Port n configuration bits"] - pub fn set_cnf(&mut self, n: usize, val: super::vals::Cnf) { - assert!(n < 8usize); - let offs = 2usize + n * 4usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - } - impl Default for Cr { - fn default() -> Cr { - Cr(0) - } - } - #[doc = "Port configuration lock register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Lckr(pub u32); - impl Lckr { - #[doc = "Port A Lock bit"] - pub fn lck(&self, n: usize) -> super::vals::Lck { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Lck(val as u8) - } - #[doc = "Port A Lock bit"] - pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - #[doc = "Lock key"] - pub const fn lckk(&self) -> super::vals::Lckk { - let val = (self.0 >> 16usize) & 0x01; - super::vals::Lckk(val as u8) - } - #[doc = "Lock key"] - pub fn set_lckk(&mut self, val: super::vals::Lckk) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); - } - } - impl Default for Lckr { - fn default() -> Lckr { - Lckr(0) - } - } - #[doc = "Port output data register (GPIOn_ODR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Odr(pub u32); - impl Odr { - #[doc = "Port output data"] - pub fn odr(&self, n: usize) -> super::vals::Odr { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Odr(val as u8) - } - #[doc = "Port output data"] - pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Odr { - fn default() -> Odr { - Odr(0) - } + pub struct Ct(pub u8); + impl Ct { + #[doc = "The current target memory is Memory 0"] + pub const MEMORY0: Self = Self(0); + #[doc = "The current target memory is Memory 1"] + pub const MEMORY1: Self = Self(0x01); } } } pub mod timer_v1 { use crate::generic::*; - #[doc = "General purpose 16-bit timer"] + #[doc = "Advanced-timers"] #[derive(Copy, Clone)] - pub struct TimGp16(pub *mut u8); - unsafe impl Send for TimGp16 {} - unsafe impl Sync for TimGp16 {} - impl TimGp16 { + pub struct TimAdv(pub *mut u8); + unsafe impl Send for TimAdv {} + unsafe impl Sync for TimAdv {} + impl TimAdv { #[doc = "control register 1"] pub fn cr1(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(0usize)) } } #[doc = "control register 2"] - pub fn cr2(self) -> Reg { + pub fn cr2(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(4usize)) } } #[doc = "slave mode control register"] @@ -2897,15 +1784,15 @@ pub mod timer_v1 { unsafe { Reg::from_ptr(self.0.add(8usize)) } } #[doc = "DMA/Interrupt enable register"] - pub fn dier(self) -> Reg { + pub fn dier(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(12usize)) } } #[doc = "status register"] - pub fn sr(self) -> Reg { + pub fn sr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(16usize)) } } #[doc = "event generation register"] - pub fn egr(self) -> Reg { + pub fn egr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(20usize)) } } #[doc = "capture/compare mode register 1 (input mode)"] @@ -2919,7 +1806,7 @@ pub mod timer_v1 { unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } } #[doc = "capture/compare enable register"] - pub fn ccer(self) -> Reg { + pub fn ccer(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(32usize)) } } #[doc = "counter"] @@ -2934,11 +1821,19 @@ pub mod timer_v1 { pub fn arr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(44usize)) } } + #[doc = "repetition counter register"] + pub fn rcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(48usize)) } + } #[doc = "capture/compare register"] pub fn ccr(self, n: usize) -> Reg { assert!(n < 4usize); unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } } + #[doc = "break and dead-time register"] + pub fn bdtr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(68usize)) } + } #[doc = "DMA control register"] pub fn dcr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(72usize)) } @@ -3018,18 +1913,18 @@ pub mod timer_v1 { unsafe { Reg::from_ptr(self.0.add(76usize)) } } } - #[doc = "Advanced-timers"] + #[doc = "General purpose 16-bit timer"] #[derive(Copy, Clone)] - pub struct TimAdv(pub *mut u8); - unsafe impl Send for TimAdv {} - unsafe impl Sync for TimAdv {} - impl TimAdv { + pub struct TimGp16(pub *mut u8); + unsafe impl Send for TimGp16 {} + unsafe impl Sync for TimGp16 {} + impl TimGp16 { #[doc = "control register 1"] pub fn cr1(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(0usize)) } } #[doc = "control register 2"] - pub fn cr2(self) -> Reg { + pub fn cr2(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(4usize)) } } #[doc = "slave mode control register"] @@ -3037,15 +1932,15 @@ pub mod timer_v1 { unsafe { Reg::from_ptr(self.0.add(8usize)) } } #[doc = "DMA/Interrupt enable register"] - pub fn dier(self) -> Reg { + pub fn dier(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(12usize)) } } #[doc = "status register"] - pub fn sr(self) -> Reg { + pub fn sr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(16usize)) } } #[doc = "event generation register"] - pub fn egr(self) -> Reg { + pub fn egr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(20usize)) } } #[doc = "capture/compare mode register 1 (input mode)"] @@ -3059,7 +1954,7 @@ pub mod timer_v1 { unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } } #[doc = "capture/compare enable register"] - pub fn ccer(self) -> Reg { + pub fn ccer(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(32usize)) } } #[doc = "counter"] @@ -3074,19 +1969,11 @@ pub mod timer_v1 { pub fn arr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(44usize)) } } - #[doc = "repetition counter register"] - pub fn rcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(48usize)) } - } #[doc = "capture/compare register"] pub fn ccr(self, n: usize) -> Reg { assert!(n < 4usize); unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } } - #[doc = "break and dead-time register"] - pub fn bdtr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(68usize)) } - } #[doc = "DMA control register"] pub fn dcr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(72usize)) } @@ -3135,349 +2022,26 @@ pub mod timer_v1 { unsafe { Reg::from_ptr(self.0.add(44usize)) } } } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ts(pub u8); - impl Ts { - #[doc = "Internal Trigger 0 (ITR0)"] - pub const ITR0: Self = Self(0); - #[doc = "Internal Trigger 1 (ITR1)"] - pub const ITR1: Self = Self(0x01); - #[doc = "Internal Trigger 2 (ITR2)"] - pub const ITR2: Self = Self(0x02); - #[doc = "TI1 Edge Detector (TI1F_ED)"] - pub const TI1F_ED: Self = Self(0x04); - #[doc = "Filtered Timer Input 1 (TI1FP1)"] - pub const TI1FP1: Self = Self(0x05); - #[doc = "Filtered Timer Input 2 (TI2FP2)"] - pub const TI2FP2: Self = Self(0x06); - #[doc = "External Trigger input (ETRF)"] - pub const ETRF: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Sms(pub u8); - impl Sms { - #[doc = "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] - pub const DISABLED: Self = Self(0); - #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."] - pub const ENCODER_MODE_1: Self = Self(0x01); - #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."] - pub const ENCODER_MODE_2: Self = Self(0x02); - #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."] - pub const ENCODER_MODE_3: Self = Self(0x03); - #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."] - pub const RESET_MODE: Self = Self(0x04); - #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."] - pub const GATED_MODE: Self = Self(0x05); - #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."] - pub const TRIGGER_MODE: Self = Self(0x06); - #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."] - pub const EXT_CLOCK_MODE: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Icf(pub u8); - impl Icf { - #[doc = "No filter, sampling is done at fDTS"] - pub const NOFILTER: Self = Self(0); - #[doc = "fSAMPLING=fCK_INT, N=2"] - pub const FCK_INT_N2: Self = Self(0x01); - #[doc = "fSAMPLING=fCK_INT, N=4"] - pub const FCK_INT_N4: Self = Self(0x02); - #[doc = "fSAMPLING=fCK_INT, N=8"] - pub const FCK_INT_N8: Self = Self(0x03); - #[doc = "fSAMPLING=fDTS/2, N=6"] - pub const FDTS_DIV2_N6: Self = Self(0x04); - #[doc = "fSAMPLING=fDTS/2, N=8"] - pub const FDTS_DIV2_N8: Self = Self(0x05); - #[doc = "fSAMPLING=fDTS/4, N=6"] - pub const FDTS_DIV4_N6: Self = Self(0x06); - #[doc = "fSAMPLING=fDTS/4, N=8"] - pub const FDTS_DIV4_N8: Self = Self(0x07); - #[doc = "fSAMPLING=fDTS/8, N=6"] - pub const FDTS_DIV8_N6: Self = Self(0x08); - #[doc = "fSAMPLING=fDTS/8, N=8"] - pub const FDTS_DIV8_N8: Self = Self(0x09); - #[doc = "fSAMPLING=fDTS/16, N=5"] - pub const FDTS_DIV16_N5: Self = Self(0x0a); - #[doc = "fSAMPLING=fDTS/16, N=6"] - pub const FDTS_DIV16_N6: Self = Self(0x0b); - #[doc = "fSAMPLING=fDTS/16, N=8"] - pub const FDTS_DIV16_N8: Self = Self(0x0c); - #[doc = "fSAMPLING=fDTS/32, N=5"] - pub const FDTS_DIV32_N5: Self = Self(0x0d); - #[doc = "fSAMPLING=fDTS/32, N=6"] - pub const FDTS_DIV32_N6: Self = Self(0x0e); - #[doc = "fSAMPLING=fDTS/32, N=8"] - pub const FDTS_DIV32_N8: Self = Self(0x0f); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Opm(pub u8); - impl Opm { - #[doc = "Counter is not stopped at update event"] - pub const DISABLED: Self = Self(0); - #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ocm(pub u8); - impl Ocm { - #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] - pub const FROZEN: Self = Self(0); - #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] - pub const ACTIVEONMATCH: Self = Self(0x01); - #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] - pub const INACTIVEONMATCH: Self = Self(0x02); - #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] - pub const TOGGLE: Self = Self(0x03); - #[doc = "OCyREF is forced low"] - pub const FORCEINACTIVE: Self = Self(0x04); - #[doc = "OCyREF is forced high"] - pub const FORCEACTIVE: Self = Self(0x05); - #[doc = "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active"] - pub const PWMMODE1: Self = Self(0x06); - #[doc = "Inversely to PwmMode1"] - pub const PWMMODE2: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ossi(pub u8); - impl Ossi { - #[doc = "When inactive, OC/OCN outputs are disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "When inactive, OC/OCN outputs are forced to idle level"] - pub const IDLELEVEL: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dir(pub u8); - impl Dir { - #[doc = "Counter used as upcounter"] - pub const UP: Self = Self(0); - #[doc = "Counter used as downcounter"] - pub const DOWN: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ossr(pub u8); - impl Ossr { - #[doc = "When inactive, OC/OCN outputs are disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"] - pub const IDLELEVEL: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Msm(pub u8); - impl Msm { - #[doc = "No action"] - pub const NOSYNC: Self = Self(0); - #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."] - pub const SYNC: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Arpe(pub u8); - impl Arpe { - #[doc = "TIMx_APRR register is not buffered"] - pub const DISABLED: Self = Self(0); - #[doc = "TIMx_APRR register is buffered"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct CcmrOutputCcs(pub u8); - impl CcmrOutputCcs { - #[doc = "CCx channel is configured as output"] - pub const OUTPUT: Self = Self(0); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ccds(pub u8); - impl Ccds { - #[doc = "CCx DMA request sent when CCx event occurs"] - pub const ONCOMPARE: Self = Self(0); - #[doc = "CCx DMA request sent when update event occurs"] - pub const ONUPDATE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Tis(pub u8); - impl Tis { - #[doc = "The TIMx_CH1 pin is connected to TI1 input"] - pub const NORMAL: Self = Self(0); - #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"] - pub const XOR: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct CcmrInputCcs(pub u8); - impl CcmrInputCcs { - #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"] - pub const TI4: Self = Self(0x01); - #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"] - pub const TI3: Self = Self(0x02); - #[doc = "CCx channel is configured as input, ICx is mapped on TRC"] - pub const TRC: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Etf(pub u8); - impl Etf { - #[doc = "No filter, sampling is done at fDTS"] - pub const NOFILTER: Self = Self(0); - #[doc = "fSAMPLING=fCK_INT, N=2"] - pub const FCK_INT_N2: Self = Self(0x01); - #[doc = "fSAMPLING=fCK_INT, N=4"] - pub const FCK_INT_N4: Self = Self(0x02); - #[doc = "fSAMPLING=fCK_INT, N=8"] - pub const FCK_INT_N8: Self = Self(0x03); - #[doc = "fSAMPLING=fDTS/2, N=6"] - pub const FDTS_DIV2_N6: Self = Self(0x04); - #[doc = "fSAMPLING=fDTS/2, N=8"] - pub const FDTS_DIV2_N8: Self = Self(0x05); - #[doc = "fSAMPLING=fDTS/4, N=6"] - pub const FDTS_DIV4_N6: Self = Self(0x06); - #[doc = "fSAMPLING=fDTS/4, N=8"] - pub const FDTS_DIV4_N8: Self = Self(0x07); - #[doc = "fSAMPLING=fDTS/8, N=6"] - pub const FDTS_DIV8_N6: Self = Self(0x08); - #[doc = "fSAMPLING=fDTS/8, N=8"] - pub const FDTS_DIV8_N8: Self = Self(0x09); - #[doc = "fSAMPLING=fDTS/16, N=5"] - pub const FDTS_DIV16_N5: Self = Self(0x0a); - #[doc = "fSAMPLING=fDTS/16, N=6"] - pub const FDTS_DIV16_N6: Self = Self(0x0b); - #[doc = "fSAMPLING=fDTS/16, N=8"] - pub const FDTS_DIV16_N8: Self = Self(0x0c); - #[doc = "fSAMPLING=fDTS/32, N=5"] - pub const FDTS_DIV32_N5: Self = Self(0x0d); - #[doc = "fSAMPLING=fDTS/32, N=6"] - pub const FDTS_DIV32_N6: Self = Self(0x0e); - #[doc = "fSAMPLING=fDTS/32, N=8"] - pub const FDTS_DIV32_N8: Self = Self(0x0f); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cms(pub u8); - impl Cms { - #[doc = "The counter counts up or down depending on the direction bit"] - pub const EDGEALIGNED: Self = Self(0); - #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] - pub const CENTERALIGNED1: Self = Self(0x01); - #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] - pub const CENTERALIGNED2: Self = Self(0x02); - #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] - pub const CENTERALIGNED3: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ckd(pub u8); - impl Ckd { - #[doc = "t_DTS = t_CK_INT"] - pub const DIV1: Self = Self(0); - #[doc = "t_DTS = 2 × t_CK_INT"] - pub const DIV2: Self = Self(0x01); - #[doc = "t_DTS = 4 × t_CK_INT"] - pub const DIV4: Self = Self(0x02); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Etp(pub u8); - impl Etp { - #[doc = "ETR is noninverted, active at high level or rising edge"] - pub const NOTINVERTED: Self = Self(0); - #[doc = "ETR is inverted, active at low level or falling edge"] - pub const INVERTED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Etps(pub u8); - impl Etps { - #[doc = "Prescaler OFF"] - pub const DIV1: Self = Self(0); - #[doc = "ETRP frequency divided by 2"] - pub const DIV2: Self = Self(0x01); - #[doc = "ETRP frequency divided by 4"] - pub const DIV4: Self = Self(0x02); - #[doc = "ETRP frequency divided by 8"] - pub const DIV8: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Urs(pub u8); - impl Urs { - #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"] - pub const ANYEVENT: Self = Self(0); - #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"] - pub const COUNTERONLY: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ocpe(pub u8); - impl Ocpe { - #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"] - pub const DISABLED: Self = Self(0); - #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ece(pub u8); - impl Ece { - #[doc = "External clock mode 2 disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mms(pub u8); - impl Mms { - #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"] - pub const RESET: Self = Self(0); - #[doc = "The counter enable signal, CNT_EN, is used as trigger output"] - pub const ENABLE: Self = Self(0x01); - #[doc = "The update event is selected as trigger output"] - pub const UPDATE: Self = Self(0x02); - #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"] - pub const COMPAREPULSE: Self = Self(0x03); - #[doc = "OC1REF signal is used as trigger output"] - pub const COMPAREOC1: Self = Self(0x04); - #[doc = "OC2REF signal is used as trigger output"] - pub const COMPAREOC2: Self = Self(0x05); - #[doc = "OC3REF signal is used as trigger output"] - pub const COMPAREOC3: Self = Self(0x06); - #[doc = "OC4REF signal is used as trigger output"] - pub const COMPAREOC4: Self = Self(0x07); - } - } pub mod regs { use crate::generic::*; - #[doc = "counter"] + #[doc = "event generation register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cnt32(pub u32); - impl Cnt32 { - #[doc = "counter value"] - pub const fn cnt(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 + pub struct EgrBasic(pub u32); + impl EgrBasic { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 } - #[doc = "counter value"] - pub fn set_cnt(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } } - impl Default for Cnt32 { - fn default() -> Cnt32 { - Cnt32(0) + impl Default for EgrBasic { + fn default() -> EgrBasic { + EgrBasic(0) } } #[doc = "DMA address for full transfer"] @@ -3500,119 +2064,6 @@ pub mod timer_v1 { Dmar(0) } } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct SrGp(pub u32); - impl SrGp { - #[doc = "Update interrupt flag"] - pub const fn uif(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt flag"] - pub fn set_uif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare 1 interrupt flag"] - pub fn ccif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/compare 1 interrupt flag"] - pub fn set_ccif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "COM interrupt flag"] - pub const fn comif(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "COM interrupt flag"] - pub fn set_comif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger interrupt flag"] - pub const fn tif(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger interrupt flag"] - pub fn set_tif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break interrupt flag"] - pub const fn bif(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break interrupt flag"] - pub fn set_bif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Capture/Compare 1 overcapture flag"] - pub fn ccof(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 overcapture flag"] - pub fn set_ccof(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for SrGp { - fn default() -> SrGp { - SrGp(0) - } - } - #[doc = "prescaler"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Psc(pub u32); - impl Psc { - #[doc = "Prescaler value"] - pub const fn psc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Prescaler value"] - pub fn set_psc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Psc { - fn default() -> Psc { - Psc(0) - } - } - #[doc = "capture/compare register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ccr16(pub u32); - impl Ccr16 { - #[doc = "Capture/Compare 1 value"] - pub const fn ccr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Capture/Compare 1 value"] - pub fn set_ccr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Ccr16 { - fn default() -> Ccr16 { - Ccr16(0) - } - } #[doc = "event generation register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -3673,1080 +2124,6 @@ pub mod timer_v1 { EgrGp(0) } } - #[doc = "DMA/Interrupt enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct DierAdv(pub u32); - impl DierAdv { - #[doc = "Update interrupt enable"] - pub const fn uie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt enable"] - pub fn set_uie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/Compare 1 interrupt enable"] - pub fn ccie(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 interrupt enable"] - pub fn set_ccie(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "COM interrupt enable"] - pub const fn comie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "COM interrupt enable"] - pub fn set_comie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger interrupt enable"] - pub const fn tie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger interrupt enable"] - pub fn set_tie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break interrupt enable"] - pub const fn bie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break interrupt enable"] - pub fn set_bie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Update DMA request enable"] - pub const fn ude(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Update DMA request enable"] - pub fn set_ude(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Capture/Compare 1 DMA request enable"] - pub fn ccde(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 DMA request enable"] - pub fn set_ccde(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "COM DMA request enable"] - pub const fn comde(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "COM DMA request enable"] - pub fn set_comde(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[doc = "Trigger DMA request enable"] - pub const fn tde(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Trigger DMA request enable"] - pub fn set_tde(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - } - impl Default for DierAdv { - fn default() -> DierAdv { - DierAdv(0) - } - } - #[doc = "repetition counter register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Rcr(pub u32); - impl Rcr { - #[doc = "Repetition counter value"] - pub const fn rep(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Repetition counter value"] - pub fn set_rep(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - } - impl Default for Rcr { - fn default() -> Rcr { - Rcr(0) - } - } - #[doc = "event generation register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct EgrAdv(pub u32); - impl EgrAdv { - #[doc = "Update generation"] - pub const fn ug(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update generation"] - pub fn set_ug(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare 1 generation"] - pub fn ccg(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/compare 1 generation"] - pub fn set_ccg(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare control update generation"] - pub const fn comg(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Capture/Compare control update generation"] - pub fn set_comg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger generation"] - pub const fn tg(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger generation"] - pub fn set_tg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break generation"] - pub const fn bg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break generation"] - pub fn set_bg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - } - impl Default for EgrAdv { - fn default() -> EgrAdv { - EgrAdv(0) - } - } - #[doc = "control register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1Gp(pub u32); - impl Cr1Gp { - #[doc = "Counter enable"] - pub const fn cen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Counter enable"] - pub fn set_cen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Update disable"] - pub const fn udis(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Update disable"] - pub fn set_udis(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Update request source"] - pub const fn urs(&self) -> super::vals::Urs { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Urs(val as u8) - } - #[doc = "Update request source"] - pub fn set_urs(&mut self, val: super::vals::Urs) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "One-pulse mode"] - pub const fn opm(&self) -> super::vals::Opm { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Opm(val as u8) - } - #[doc = "One-pulse mode"] - pub fn set_opm(&mut self, val: super::vals::Opm) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Direction"] - pub const fn dir(&self) -> super::vals::Dir { - let val = (self.0 >> 4usize) & 0x01; - super::vals::Dir(val as u8) - } - #[doc = "Direction"] - pub fn set_dir(&mut self, val: super::vals::Dir) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); - } - #[doc = "Center-aligned mode selection"] - pub const fn cms(&self) -> super::vals::Cms { - let val = (self.0 >> 5usize) & 0x03; - super::vals::Cms(val as u8) - } - #[doc = "Center-aligned mode selection"] - pub fn set_cms(&mut self, val: super::vals::Cms) { - self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize); - } - #[doc = "Auto-reload preload enable"] - pub const fn arpe(&self) -> super::vals::Arpe { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Arpe(val as u8) - } - #[doc = "Auto-reload preload enable"] - pub fn set_arpe(&mut self, val: super::vals::Arpe) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Clock division"] - pub const fn ckd(&self) -> super::vals::Ckd { - let val = (self.0 >> 8usize) & 0x03; - super::vals::Ckd(val as u8) - } - #[doc = "Clock division"] - pub fn set_ckd(&mut self, val: super::vals::Ckd) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); - } - } - impl Default for Cr1Gp { - fn default() -> Cr1Gp { - Cr1Gp(0) - } - } - #[doc = "capture/compare register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ccr32(pub u32); - impl Ccr32 { - #[doc = "Capture/Compare 1 value"] - pub const fn ccr(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Capture/Compare 1 value"] - pub fn set_ccr(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Ccr32 { - fn default() -> Ccr32 { - Ccr32(0) - } - } - #[doc = "capture/compare mode register 1 (input mode)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcmrInput(pub u32); - impl CcmrInput { - #[doc = "Capture/Compare 1 selection"] - pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs { - assert!(n < 2usize); - let offs = 0usize + n * 8usize; - let val = (self.0 >> offs) & 0x03; - super::vals::CcmrInputCcs(val as u8) - } - #[doc = "Capture/Compare 1 selection"] - pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) { - assert!(n < 2usize); - let offs = 0usize + n * 8usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - #[doc = "Input capture 1 prescaler"] - pub fn icpsc(&self, n: usize) -> u8 { - assert!(n < 2usize); - let offs = 2usize + n * 8usize; - let val = (self.0 >> offs) & 0x03; - val as u8 - } - #[doc = "Input capture 1 prescaler"] - pub fn set_icpsc(&mut self, n: usize, val: u8) { - assert!(n < 2usize); - let offs = 2usize + n * 8usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs); - } - #[doc = "Input capture 1 filter"] - pub fn icf(&self, n: usize) -> super::vals::Icf { - assert!(n < 2usize); - let offs = 4usize + n * 8usize; - let val = (self.0 >> offs) & 0x0f; - super::vals::Icf(val as u8) - } - #[doc = "Input capture 1 filter"] - pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) { - assert!(n < 2usize); - let offs = 4usize + n * 8usize; - self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); - } - } - impl Default for CcmrInput { - fn default() -> CcmrInput { - CcmrInput(0) - } - } - #[doc = "auto-reload register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Arr32(pub u32); - impl Arr32 { - #[doc = "Auto-reload value"] - pub const fn arr(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Auto-reload value"] - pub fn set_arr(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Arr32 { - fn default() -> Arr32 { - Arr32(0) - } - } - #[doc = "slave mode control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Smcr(pub u32); - impl Smcr { - #[doc = "Slave mode selection"] - pub const fn sms(&self) -> super::vals::Sms { - let val = (self.0 >> 0usize) & 0x07; - super::vals::Sms(val as u8) - } - #[doc = "Slave mode selection"] - pub fn set_sms(&mut self, val: super::vals::Sms) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize); - } - #[doc = "Trigger selection"] - pub const fn ts(&self) -> super::vals::Ts { - let val = (self.0 >> 4usize) & 0x07; - super::vals::Ts(val as u8) - } - #[doc = "Trigger selection"] - pub fn set_ts(&mut self, val: super::vals::Ts) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); - } - #[doc = "Master/Slave mode"] - pub const fn msm(&self) -> super::vals::Msm { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Msm(val as u8) - } - #[doc = "Master/Slave mode"] - pub fn set_msm(&mut self, val: super::vals::Msm) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "External trigger filter"] - pub const fn etf(&self) -> super::vals::Etf { - let val = (self.0 >> 8usize) & 0x0f; - super::vals::Etf(val as u8) - } - #[doc = "External trigger filter"] - pub fn set_etf(&mut self, val: super::vals::Etf) { - self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); - } - #[doc = "External trigger prescaler"] - pub const fn etps(&self) -> super::vals::Etps { - let val = (self.0 >> 12usize) & 0x03; - super::vals::Etps(val as u8) - } - #[doc = "External trigger prescaler"] - pub fn set_etps(&mut self, val: super::vals::Etps) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); - } - #[doc = "External clock enable"] - pub const fn ece(&self) -> super::vals::Ece { - let val = (self.0 >> 14usize) & 0x01; - super::vals::Ece(val as u8) - } - #[doc = "External clock enable"] - pub fn set_ece(&mut self, val: super::vals::Ece) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); - } - #[doc = "External trigger polarity"] - pub const fn etp(&self) -> super::vals::Etp { - let val = (self.0 >> 15usize) & 0x01; - super::vals::Etp(val as u8) - } - #[doc = "External trigger polarity"] - pub fn set_etp(&mut self, val: super::vals::Etp) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); - } - } - impl Default for Smcr { - fn default() -> Smcr { - Smcr(0) - } - } - #[doc = "control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2Basic(pub u32); - impl Cr2Basic { - #[doc = "Master mode selection"] - pub const fn mms(&self) -> super::vals::Mms { - let val = (self.0 >> 4usize) & 0x07; - super::vals::Mms(val as u8) - } - #[doc = "Master mode selection"] - pub fn set_mms(&mut self, val: super::vals::Mms) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); - } - } - impl Default for Cr2Basic { - fn default() -> Cr2Basic { - Cr2Basic(0) - } - } - #[doc = "capture/compare enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcerAdv(pub u32); - impl CcerAdv { - #[doc = "Capture/Compare 1 output enable"] - pub fn cce(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output enable"] - pub fn set_cce(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn ccp(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn set_ccp(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 complementary output enable"] - pub fn ccne(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 2usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 complementary output enable"] - pub fn set_ccne(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 2usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn ccnp(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 3usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn set_ccnp(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 3usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for CcerAdv { - fn default() -> CcerAdv { - CcerAdv(0) - } - } - #[doc = "DMA/Interrupt enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct DierGp(pub u32); - impl DierGp { - #[doc = "Update interrupt enable"] - pub const fn uie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt enable"] - pub fn set_uie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/Compare 1 interrupt enable"] - pub fn ccie(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 interrupt enable"] - pub fn set_ccie(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Trigger interrupt enable"] - pub const fn tie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger interrupt enable"] - pub fn set_tie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Update DMA request enable"] - pub const fn ude(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Update DMA request enable"] - pub fn set_ude(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Capture/Compare 1 DMA request enable"] - pub fn ccde(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 DMA request enable"] - pub fn set_ccde(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Trigger DMA request enable"] - pub const fn tde(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Trigger DMA request enable"] - pub fn set_tde(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - } - impl Default for DierGp { - fn default() -> DierGp { - DierGp(0) - } - } - #[doc = "auto-reload register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Arr16(pub u32); - impl Arr16 { - #[doc = "Auto-reload value"] - pub const fn arr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Auto-reload value"] - pub fn set_arr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Arr16 { - fn default() -> Arr16 { - Arr16(0) - } - } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct SrBasic(pub u32); - impl SrBasic { - #[doc = "Update interrupt flag"] - pub const fn uif(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt flag"] - pub fn set_uif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for SrBasic { - fn default() -> SrBasic { - SrBasic(0) - } - } - #[doc = "DMA control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dcr(pub u32); - impl Dcr { - #[doc = "DMA base address"] - pub const fn dba(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x1f; - val as u8 - } - #[doc = "DMA base address"] - pub fn set_dba(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); - } - #[doc = "DMA burst length"] - pub const fn dbl(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x1f; - val as u8 - } - #[doc = "DMA burst length"] - pub fn set_dbl(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); - } - } - impl Default for Dcr { - fn default() -> Dcr { - Dcr(0) - } - } - #[doc = "control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2Adv(pub u32); - impl Cr2Adv { - #[doc = "Capture/compare preloaded control"] - pub const fn ccpc(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Capture/compare preloaded control"] - pub fn set_ccpc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare control update selection"] - pub const fn ccus(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Capture/compare control update selection"] - pub fn set_ccus(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Capture/compare DMA selection"] - pub const fn ccds(&self) -> super::vals::Ccds { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Ccds(val as u8) - } - #[doc = "Capture/compare DMA selection"] - pub fn set_ccds(&mut self, val: super::vals::Ccds) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Master mode selection"] - pub const fn mms(&self) -> super::vals::Mms { - let val = (self.0 >> 4usize) & 0x07; - super::vals::Mms(val as u8) - } - #[doc = "Master mode selection"] - pub fn set_mms(&mut self, val: super::vals::Mms) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); - } - #[doc = "TI1 selection"] - pub const fn ti1s(&self) -> super::vals::Tis { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Tis(val as u8) - } - #[doc = "TI1 selection"] - pub fn set_ti1s(&mut self, val: super::vals::Tis) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Output Idle state 1"] - pub fn ois(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 8usize + n * 2usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Output Idle state 1"] - pub fn set_ois(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 8usize + n * 2usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Output Idle state 1"] - pub const fn ois1n(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Output Idle state 1"] - pub fn set_ois1n(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Output Idle state 2"] - pub const fn ois2n(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "Output Idle state 2"] - pub fn set_ois2n(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "Output Idle state 3"] - pub const fn ois3n(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "Output Idle state 3"] - pub fn set_ois3n(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - } - impl Default for Cr2Adv { - fn default() -> Cr2Adv { - Cr2Adv(0) - } - } - #[doc = "event generation register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct EgrBasic(pub u32); - impl EgrBasic { - #[doc = "Update generation"] - pub const fn ug(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update generation"] - pub fn set_ug(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for EgrBasic { - fn default() -> EgrBasic { - EgrBasic(0) - } - } - #[doc = "control register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1Basic(pub u32); - impl Cr1Basic { - #[doc = "Counter enable"] - pub const fn cen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Counter enable"] - pub fn set_cen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Update disable"] - pub const fn udis(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Update disable"] - pub fn set_udis(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Update request source"] - pub const fn urs(&self) -> super::vals::Urs { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Urs(val as u8) - } - #[doc = "Update request source"] - pub fn set_urs(&mut self, val: super::vals::Urs) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "One-pulse mode"] - pub const fn opm(&self) -> super::vals::Opm { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Opm(val as u8) - } - #[doc = "One-pulse mode"] - pub fn set_opm(&mut self, val: super::vals::Opm) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Auto-reload preload enable"] - pub const fn arpe(&self) -> super::vals::Arpe { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Arpe(val as u8) - } - #[doc = "Auto-reload preload enable"] - pub fn set_arpe(&mut self, val: super::vals::Arpe) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - } - impl Default for Cr1Basic { - fn default() -> Cr1Basic { - Cr1Basic(0) - } - } - #[doc = "capture/compare enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcerGp(pub u32); - impl CcerGp { - #[doc = "Capture/Compare 1 output enable"] - pub fn cce(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output enable"] - pub fn set_cce(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn ccp(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn set_ccp(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn ccnp(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 3usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn set_ccnp(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 3usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for CcerGp { - fn default() -> CcerGp { - CcerGp(0) - } - } - #[doc = "capture/compare mode register 2 (output mode)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcmrOutput(pub u32); - impl CcmrOutput { - #[doc = "Capture/Compare 3 selection"] - pub fn ccs(&self, n: usize) -> super::vals::CcmrOutputCcs { - assert!(n < 2usize); - let offs = 0usize + n * 8usize; - let val = (self.0 >> offs) & 0x03; - super::vals::CcmrOutputCcs(val as u8) - } - #[doc = "Capture/Compare 3 selection"] - pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrOutputCcs) { - assert!(n < 2usize); - let offs = 0usize + n * 8usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - #[doc = "Output compare 3 fast enable"] - pub fn ocfe(&self, n: usize) -> bool { - assert!(n < 2usize); - let offs = 2usize + n * 8usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Output compare 3 fast enable"] - pub fn set_ocfe(&mut self, n: usize, val: bool) { - assert!(n < 2usize); - let offs = 2usize + n * 8usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Output compare 3 preload enable"] - pub fn ocpe(&self, n: usize) -> super::vals::Ocpe { - assert!(n < 2usize); - let offs = 3usize + n * 8usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Ocpe(val as u8) - } - #[doc = "Output compare 3 preload enable"] - pub fn set_ocpe(&mut self, n: usize, val: super::vals::Ocpe) { - assert!(n < 2usize); - let offs = 3usize + n * 8usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - #[doc = "Output compare 3 mode"] - pub fn ocm(&self, n: usize) -> super::vals::Ocm { - assert!(n < 2usize); - let offs = 4usize + n * 8usize; - let val = (self.0 >> offs) & 0x07; - super::vals::Ocm(val as u8) - } - #[doc = "Output compare 3 mode"] - pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) { - assert!(n < 2usize); - let offs = 4usize + n * 8usize; - self.0 = (self.0 & !(0x07 << offs)) | (((val.0 as u32) & 0x07) << offs); - } - #[doc = "Output compare 3 clear enable"] - pub fn occe(&self, n: usize) -> bool { - assert!(n < 2usize); - let offs = 7usize + n * 8usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Output compare 3 clear enable"] - pub fn set_occe(&mut self, n: usize, val: bool) { - assert!(n < 2usize); - let offs = 7usize + n * 8usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for CcmrOutput { - fn default() -> CcmrOutput { - CcmrOutput(0) - } - } - #[doc = "counter"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cnt16(pub u32); - impl Cnt16 { - #[doc = "counter value"] - pub const fn cnt(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "counter value"] - pub fn set_cnt(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Cnt16 { - fn default() -> Cnt16 { - Cnt16(0) - } - } - #[doc = "DMA/Interrupt enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct DierBasic(pub u32); - impl DierBasic { - #[doc = "Update interrupt enable"] - pub const fn uie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt enable"] - pub fn set_uie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Update DMA request enable"] - pub const fn ude(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Update DMA request enable"] - pub fn set_ude(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for DierBasic { - fn default() -> DierBasic { - DierBasic(0) - } - } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct SrAdv(pub u32); - impl SrAdv { - #[doc = "Update interrupt flag"] - pub const fn uif(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt flag"] - pub fn set_uif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare 1 interrupt flag"] - pub fn ccif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/compare 1 interrupt flag"] - pub fn set_ccif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "COM interrupt flag"] - pub const fn comif(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "COM interrupt flag"] - pub fn set_comif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger interrupt flag"] - pub const fn tif(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger interrupt flag"] - pub fn set_tif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break interrupt flag"] - pub const fn bif(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break interrupt flag"] - pub fn set_bif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Capture/Compare 1 overcapture flag"] - pub fn ccof(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 overcapture flag"] - pub fn set_ccof(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for SrAdv { - fn default() -> SrAdv { - SrAdv(0) - } - } #[doc = "control register 2"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -4868,922 +2245,2078 @@ pub mod timer_v1 { Bdtr(0) } } - } -} -pub mod syscfg_h7 { - use crate::generic::*; - #[doc = "System configuration controller"] - #[derive(Copy, Clone)] - pub struct Syscfg(pub *mut u8); - unsafe impl Send for Syscfg {} - unsafe impl Sync for Syscfg {} - impl Syscfg { - #[doc = "peripheral mode configuration register"] - pub fn pmcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "external interrupt configuration register 1"] - pub fn exticr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } - } - #[doc = "compensation cell control/status register"] - pub fn cccsr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(32usize)) } - } - #[doc = "SYSCFG compensation cell value register"] - pub fn ccvr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - #[doc = "SYSCFG compensation cell code register"] - pub fn cccr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(40usize)) } - } - #[doc = "SYSCFG power control register"] - pub fn pwrcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(44usize)) } - } - #[doc = "SYSCFG package register"] - pub fn pkgr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(292usize)) } - } - #[doc = "SYSCFG user register 0"] - pub fn ur0(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(768usize)) } - } - #[doc = "SYSCFG user register 2"] - pub fn ur2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(776usize)) } - } - #[doc = "SYSCFG user register 3"] - pub fn ur3(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(780usize)) } - } - #[doc = "SYSCFG user register 4"] - pub fn ur4(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(784usize)) } - } - #[doc = "SYSCFG user register 5"] - pub fn ur5(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(788usize)) } - } - #[doc = "SYSCFG user register 6"] - pub fn ur6(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(792usize)) } - } - #[doc = "SYSCFG user register 7"] - pub fn ur7(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(796usize)) } - } - #[doc = "SYSCFG user register 8"] - pub fn ur8(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(800usize)) } - } - #[doc = "SYSCFG user register 9"] - pub fn ur9(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(804usize)) } - } - #[doc = "SYSCFG user register 10"] - pub fn ur10(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(808usize)) } - } - #[doc = "SYSCFG user register 11"] - pub fn ur11(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(812usize)) } - } - #[doc = "SYSCFG user register 12"] - pub fn ur12(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(816usize)) } - } - #[doc = "SYSCFG user register 13"] - pub fn ur13(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(820usize)) } - } - #[doc = "SYSCFG user register 14"] - pub fn ur14(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(824usize)) } - } - #[doc = "SYSCFG user register 15"] - pub fn ur15(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(828usize)) } - } - #[doc = "SYSCFG user register 16"] - pub fn ur16(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(832usize)) } - } - #[doc = "SYSCFG user register 17"] - pub fn ur17(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(836usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "SYSCFG user register 7"] + #[doc = "repetition counter register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur7(pub u32); - impl Ur7 { - #[doc = "Secured area start address for bank 1"] - pub const fn sa_beg_1(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Secured area start address for bank 1"] - pub fn set_sa_beg_1(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Secured area end address for bank 1"] - pub const fn sa_end_1(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x0fff; - val as u16 - } - #[doc = "Secured area end address for bank 1"] - pub fn set_sa_end_1(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); - } - } - impl Default for Ur7 { - fn default() -> Ur7 { - Ur7(0) - } - } - #[doc = "SYSCFG package register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pkgr(pub u32); - impl Pkgr { - #[doc = "Package"] - pub const fn pkg(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Package"] - pub fn set_pkg(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - } - impl Default for Pkgr { - fn default() -> Pkgr { - Pkgr(0) - } - } - #[doc = "SYSCFG user register 15"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur15(pub u32); - impl Ur15 { - #[doc = "Freeze independent watchdog in Standby mode"] - pub const fn fziwdgstb(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Freeze independent watchdog in Standby mode"] - pub fn set_fziwdgstb(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur15 { - fn default() -> Ur15 { - Ur15(0) - } - } - #[doc = "SYSCFG user register 4"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur4(pub u32); - impl Ur4 { - #[doc = "Mass Erase Protected Area Disabled for bank 1"] - pub const fn mepad_1(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Mass Erase Protected Area Disabled for bank 1"] - pub fn set_mepad_1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur4 { - fn default() -> Ur4 { - Ur4(0) - } - } - #[doc = "SYSCFG user register 3"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur3(pub u32); - impl Ur3 { - #[doc = "Boot Address 1"] - pub const fn boot_add1(&self) -> u16 { - let val = (self.0 >> 16usize) & 0xffff; - val as u16 - } - #[doc = "Boot Address 1"] - pub fn set_boot_add1(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); - } - } - impl Default for Ur3 { - fn default() -> Ur3 { - Ur3(0) - } - } - #[doc = "SYSCFG user register 13"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur13(pub u32); - impl Ur13 { - #[doc = "Secured DTCM RAM Size"] - pub const fn sdrs(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x03; - val as u8 - } - #[doc = "Secured DTCM RAM Size"] - pub fn set_sdrs(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); - } - #[doc = "D1 Standby reset"] - pub const fn d1sbrst(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "D1 Standby reset"] - pub fn set_d1sbrst(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur13 { - fn default() -> Ur13 { - Ur13(0) - } - } - #[doc = "peripheral mode configuration register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pmcr(pub u32); - impl Pmcr { - #[doc = "I2C1 Fm+"] - pub const fn i2c1fmp(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "I2C1 Fm+"] - pub fn set_i2c1fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "I2C2 Fm+"] - pub const fn i2c2fmp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "I2C2 Fm+"] - pub fn set_i2c2fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "I2C3 Fm+"] - pub const fn i2c3fmp(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "I2C3 Fm+"] - pub fn set_i2c3fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "I2C4 Fm+"] - pub const fn i2c4fmp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "I2C4 Fm+"] - pub fn set_i2c4fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "PB(6) Fm+"] - pub const fn pb6fmp(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "PB(6) Fm+"] - pub fn set_pb6fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "PB(7) Fast Mode Plus"] - pub const fn pb7fmp(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "PB(7) Fast Mode Plus"] - pub fn set_pb7fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "PB(8) Fast Mode Plus"] - pub const fn pb8fmp(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "PB(8) Fast Mode Plus"] - pub fn set_pb8fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "PB(9) Fm+"] - pub const fn pb9fmp(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "PB(9) Fm+"] - pub fn set_pb9fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Booster Enable"] - pub const fn booste(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Booster Enable"] - pub fn set_booste(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Analog switch supply voltage selection"] - pub const fn boostvddsel(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Analog switch supply voltage selection"] - pub fn set_boostvddsel(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Ethernet PHY Interface Selection"] - pub const fn epis(&self) -> u8 { - let val = (self.0 >> 21usize) & 0x07; - val as u8 - } - #[doc = "Ethernet PHY Interface Selection"] - pub fn set_epis(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 21usize)) | (((val as u32) & 0x07) << 21usize); - } - #[doc = "PA0 Switch Open"] - pub const fn pa0so(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[doc = "PA0 Switch Open"] - pub fn set_pa0so(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[doc = "PA1 Switch Open"] - pub const fn pa1so(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[doc = "PA1 Switch Open"] - pub fn set_pa1so(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[doc = "PC2 Switch Open"] - pub const fn pc2so(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[doc = "PC2 Switch Open"] - pub fn set_pc2so(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[doc = "PC3 Switch Open"] - pub const fn pc3so(&self) -> bool { - let val = (self.0 >> 27usize) & 0x01; - val != 0 - } - #[doc = "PC3 Switch Open"] - pub fn set_pc3so(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); - } - } - impl Default for Pmcr { - fn default() -> Pmcr { - Pmcr(0) - } - } - #[doc = "SYSCFG user register 8"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur8(pub u32); - impl Ur8 { - #[doc = "Mass erase protected area disabled for bank 2"] - pub const fn mepad_2(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Mass erase protected area disabled for bank 2"] - pub fn set_mepad_2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Mass erase secured area disabled for bank 2"] - pub const fn mesad_2(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Mass erase secured area disabled for bank 2"] - pub fn set_mesad_2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur8 { - fn default() -> Ur8 { - Ur8(0) - } - } - #[doc = "SYSCFG compensation cell code register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cccr(pub u32); - impl Cccr { - #[doc = "NMOS compensation code"] - pub const fn ncc(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "NMOS compensation code"] - pub fn set_ncc(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "PMOS compensation code"] - pub const fn pcc(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 - } - #[doc = "PMOS compensation code"] - pub fn set_pcc(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); - } - } - impl Default for Cccr { - fn default() -> Cccr { - Cccr(0) - } - } - #[doc = "SYSCFG user register 12"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur12(pub u32); - impl Ur12 { - #[doc = "Secure mode"] - pub const fn secure(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Secure mode"] - pub fn set_secure(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur12 { - fn default() -> Ur12 { - Ur12(0) - } - } - #[doc = "SYSCFG user register 17"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur17(pub u32); - impl Ur17 { - #[doc = "I/O high speed / low voltage"] - pub const fn io_hslv(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "I/O high speed / low voltage"] - pub fn set_io_hslv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for Ur17 { - fn default() -> Ur17 { - Ur17(0) - } - } - #[doc = "SYSCFG user register 14"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur14(pub u32); - impl Ur14 { - #[doc = "D1 Stop Reset"] - pub const fn d1stprst(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "D1 Stop Reset"] - pub fn set_d1stprst(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for Ur14 { - fn default() -> Ur14 { - Ur14(0) - } - } - #[doc = "SYSCFG user register 5"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur5(pub u32); - impl Ur5 { - #[doc = "Mass erase secured area disabled for bank 1"] - pub const fn mesad_1(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Mass erase secured area disabled for bank 1"] - pub fn set_mesad_1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Write protection for flash bank 1"] - pub const fn wrpn_1(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Write protection for flash bank 1"] - pub fn set_wrpn_1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } - } - impl Default for Ur5 { - fn default() -> Ur5 { - Ur5(0) - } - } - #[doc = "external interrupt configuration register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Exticr(pub u32); - impl Exticr { - #[doc = "EXTI x configuration (x = 4 to 7)"] - pub fn exti(&self, n: usize) -> u8 { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x0f; - val as u8 - } - #[doc = "EXTI x configuration (x = 4 to 7)"] - pub fn set_exti(&mut self, n: usize, val: u8) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); - } - } - impl Default for Exticr { - fn default() -> Exticr { - Exticr(0) - } - } - #[doc = "SYSCFG user register 10"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur10(pub u32); - impl Ur10 { - #[doc = "Protected area end address for bank 2"] - pub const fn pa_end_2(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Protected area end address for bank 2"] - pub fn set_pa_end_2(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Secured area start address for bank 2"] - pub const fn sa_beg_2(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x0fff; - val as u16 - } - #[doc = "Secured area start address for bank 2"] - pub fn set_sa_beg_2(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); - } - } - impl Default for Ur10 { - fn default() -> Ur10 { - Ur10(0) - } - } - #[doc = "SYSCFG power control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pwrcr(pub u32); - impl Pwrcr { - #[doc = "Overdrive enable"] - pub const fn oden(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Overdrive enable"] - pub fn set_oden(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - } - impl Default for Pwrcr { - fn default() -> Pwrcr { - Pwrcr(0) - } - } - #[doc = "compensation cell control/status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cccsr(pub u32); - impl Cccsr { - #[doc = "enable"] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "enable"] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Code selection"] - pub const fn cs(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Code selection"] - pub fn set_cs(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Compensation cell ready flag"] - pub const fn ready(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Compensation cell ready flag"] - pub fn set_ready(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "High-speed at low-voltage"] - pub const fn hslv(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "High-speed at low-voltage"] - pub fn set_hslv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Cccsr { - fn default() -> Cccsr { - Cccsr(0) - } - } - #[doc = "SYSCFG user register 6"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur6(pub u32); - impl Ur6 { - #[doc = "Protected area start address for bank 1"] - pub const fn pa_beg_1(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Protected area start address for bank 1"] - pub fn set_pa_beg_1(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Protected area end address for bank 1"] - pub const fn pa_end_1(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x0fff; - val as u16 - } - #[doc = "Protected area end address for bank 1"] - pub fn set_pa_end_1(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); - } - } - impl Default for Ur6 { - fn default() -> Ur6 { - Ur6(0) - } - } - #[doc = "SYSCFG user register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur2(pub u32); - impl Ur2 { - #[doc = "BOR_LVL Brownout Reset Threshold Level"] - pub const fn borh(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x03; - val as u8 - } - #[doc = "BOR_LVL Brownout Reset Threshold Level"] - pub fn set_borh(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); - } - #[doc = "Boot Address 0"] - pub const fn boot_add0(&self) -> u16 { - let val = (self.0 >> 16usize) & 0xffff; - val as u16 - } - #[doc = "Boot Address 0"] - pub fn set_boot_add0(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); - } - } - impl Default for Ur2 { - fn default() -> Ur2 { - Ur2(0) - } - } - #[doc = "SYSCFG user register 9"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur9(pub u32); - impl Ur9 { - #[doc = "Write protection for flash bank 2"] - pub const fn wrpn_2(&self) -> u8 { + pub struct Rcr(pub u32); + impl Rcr { + #[doc = "Repetition counter value"] + pub const fn rep(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "Write protection for flash bank 2"] - pub fn set_wrpn_2(&mut self, val: u8) { + #[doc = "Repetition counter value"] + pub fn set_rep(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); } - #[doc = "Protected area start address for bank 2"] - pub const fn pa_beg_2(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x0fff; - val as u16 - } - #[doc = "Protected area start address for bank 2"] - pub fn set_pa_beg_2(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + impl Default for Rcr { + fn default() -> Rcr { + Rcr(0) } } - impl Default for Ur9 { - fn default() -> Ur9 { - Ur9(0) - } - } - #[doc = "SYSCFG user register 11"] + #[doc = "DMA/Interrupt enable register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur11(pub u32); - impl Ur11 { - #[doc = "Secured area end address for bank 2"] - pub const fn sa_end_2(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Secured area end address for bank 2"] - pub fn set_sa_end_2(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Independent Watchdog 1 mode"] - pub const fn iwdg1m(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Independent Watchdog 1 mode"] - pub fn set_iwdg1m(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur11 { - fn default() -> Ur11 { - Ur11(0) - } - } - #[doc = "SYSCFG compensation cell value register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ccvr(pub u32); - impl Ccvr { - #[doc = "NMOS compensation value"] - pub const fn ncv(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "NMOS compensation value"] - pub fn set_ncv(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "PMOS compensation value"] - pub const fn pcv(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 - } - #[doc = "PMOS compensation value"] - pub fn set_pcv(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); - } - } - impl Default for Ccvr { - fn default() -> Ccvr { - Ccvr(0) - } - } - #[doc = "SYSCFG user register 0"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur0(pub u32); - impl Ur0 { - #[doc = "Bank Swap"] - pub const fn bks(&self) -> bool { + pub struct DierAdv(pub u32); + impl DierAdv { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Bank Swap"] - pub fn set_bks(&mut self, val: bool) { + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Readout protection"] - pub const fn rdp(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn ccie(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 } - #[doc = "Readout protection"] - pub fn set_rdp(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn set_ccie(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt enable"] + pub const fn comie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt enable"] + pub fn set_comie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt enable"] + pub const fn tie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt enable"] + pub fn set_tie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt enable"] + pub const fn bie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break interrupt enable"] + pub fn set_bie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn ccde(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn set_ccde(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM DMA request enable"] + pub const fn comde(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "COM DMA request enable"] + pub fn set_comde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Trigger DMA request enable"] + pub const fn tde(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Trigger DMA request enable"] + pub fn set_tde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); } } - impl Default for Ur0 { - fn default() -> Ur0 { - Ur0(0) + impl Default for DierAdv { + fn default() -> DierAdv { + DierAdv(0) } } - #[doc = "SYSCFG user register 16"] + #[doc = "slave mode control register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur16(pub u32); - impl Ur16 { - #[doc = "Freeze independent watchdog in Stop mode"] - pub const fn fziwdgstp(&self) -> bool { + pub struct Smcr(pub u32); + impl Smcr { + #[doc = "Slave mode selection"] + pub const fn sms(&self) -> super::vals::Sms { + let val = (self.0 >> 0usize) & 0x07; + super::vals::Sms(val as u8) + } + #[doc = "Slave mode selection"] + pub fn set_sms(&mut self, val: super::vals::Sms) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize); + } + #[doc = "Trigger selection"] + pub const fn ts(&self) -> super::vals::Ts { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Ts(val as u8) + } + #[doc = "Trigger selection"] + pub fn set_ts(&mut self, val: super::vals::Ts) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "Master/Slave mode"] + pub const fn msm(&self) -> super::vals::Msm { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Msm(val as u8) + } + #[doc = "Master/Slave mode"] + pub fn set_msm(&mut self, val: super::vals::Msm) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "External trigger filter"] + pub const fn etf(&self) -> super::vals::Etf { + let val = (self.0 >> 8usize) & 0x0f; + super::vals::Etf(val as u8) + } + #[doc = "External trigger filter"] + pub fn set_etf(&mut self, val: super::vals::Etf) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); + } + #[doc = "External trigger prescaler"] + pub const fn etps(&self) -> super::vals::Etps { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Etps(val as u8) + } + #[doc = "External trigger prescaler"] + pub fn set_etps(&mut self, val: super::vals::Etps) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "External clock enable"] + pub const fn ece(&self) -> super::vals::Ece { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Ece(val as u8) + } + #[doc = "External clock enable"] + pub fn set_ece(&mut self, val: super::vals::Ece) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + #[doc = "External trigger polarity"] + pub const fn etp(&self) -> super::vals::Etp { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Etp(val as u8) + } + #[doc = "External trigger polarity"] + pub fn set_etp(&mut self, val: super::vals::Etp) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + } + impl Default for Smcr { + fn default() -> Smcr { + Smcr(0) + } + } + #[doc = "capture/compare register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccr32(pub u32); + impl Ccr32 { + #[doc = "Capture/Compare 1 value"] + pub const fn ccr(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Capture/Compare 1 value"] + pub fn set_ccr(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Ccr32 { + fn default() -> Ccr32 { + Ccr32(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Basic(pub u32); + impl Cr2Basic { + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + } + impl Default for Cr2Basic { + fn default() -> Cr2Basic { + Cr2Basic(0) + } + } + #[doc = "counter"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cnt32(pub u32); + impl Cnt32 { + #[doc = "counter value"] + pub const fn cnt(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "counter value"] + pub fn set_cnt(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Cnt32 { + fn default() -> Cnt32 { + Cnt32(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrGp(pub u32); + impl SrGp { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Freeze independent watchdog in Stop mode"] - pub fn set_fziwdgstp(&mut self, val: bool) { + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Private key programmed"] - pub const fn pkp(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; + #[doc = "Capture/compare 1 interrupt flag"] + pub fn ccif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; val != 0 } - #[doc = "Private key programmed"] - pub fn set_pkp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + #[doc = "Capture/compare 1 interrupt flag"] + pub fn set_ccif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt flag"] + pub const fn comif(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt flag"] + pub fn set_comif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt flag"] + pub const fn tif(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt flag"] + pub fn set_tif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt flag"] + pub const fn bif(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break interrupt flag"] + pub fn set_bif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn ccof(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn set_ccof(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } } - impl Default for Ur16 { - fn default() -> Ur16 { - Ur16(0) + impl Default for SrGp { + fn default() -> SrGp { + SrGp(0) + } + } + #[doc = "prescaler"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Psc(pub u32); + impl Psc { + #[doc = "Prescaler value"] + pub const fn psc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Prescaler value"] + pub fn set_psc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Psc { + fn default() -> Psc { + Psc(0) + } + } + #[doc = "DMA control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dcr(pub u32); + impl Dcr { + #[doc = "DMA base address"] + pub const fn dba(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 + } + #[doc = "DMA base address"] + pub fn set_dba(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); + } + #[doc = "DMA burst length"] + pub const fn dbl(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x1f; + val as u8 + } + #[doc = "DMA burst length"] + pub fn set_dbl(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); + } + } + impl Default for Dcr { + fn default() -> Dcr { + Dcr(0) + } + } + #[doc = "capture/compare enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcerGp(pub u32); + impl CcerGp { + #[doc = "Capture/Compare 1 output enable"] + pub fn cce(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output enable"] + pub fn set_cce(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccnp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccnp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcerGp { + fn default() -> CcerGp { + CcerGp(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrAdv(pub u32); + impl SrAdv { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn ccif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn set_ccif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt flag"] + pub const fn comif(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt flag"] + pub fn set_comif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt flag"] + pub const fn tif(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt flag"] + pub fn set_tif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt flag"] + pub const fn bif(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break interrupt flag"] + pub fn set_bif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn ccof(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn set_ccof(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for SrAdv { + fn default() -> SrAdv { + SrAdv(0) + } + } + #[doc = "capture/compare register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccr16(pub u32); + impl Ccr16 { + #[doc = "Capture/Compare 1 value"] + pub const fn ccr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Capture/Compare 1 value"] + pub fn set_ccr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Ccr16 { + fn default() -> Ccr16 { + Ccr16(0) + } + } + #[doc = "event generation register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct EgrAdv(pub u32); + impl EgrAdv { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 generation"] + pub fn ccg(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 generation"] + pub fn set_ccg(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare control update generation"] + pub const fn comg(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Capture/Compare control update generation"] + pub fn set_comg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger generation"] + pub const fn tg(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger generation"] + pub fn set_tg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break generation"] + pub const fn bg(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break generation"] + pub fn set_bg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for EgrAdv { + fn default() -> EgrAdv { + EgrAdv(0) + } + } + #[doc = "auto-reload register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Arr32(pub u32); + impl Arr32 { + #[doc = "Auto-reload value"] + pub const fn arr(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Auto-reload value"] + pub fn set_arr(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Arr32 { + fn default() -> Arr32 { + Arr32(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Adv(pub u32); + impl Cr2Adv { + #[doc = "Capture/compare preloaded control"] + pub const fn ccpc(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Capture/compare preloaded control"] + pub fn set_ccpc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare control update selection"] + pub const fn ccus(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Capture/compare control update selection"] + pub fn set_ccus(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Capture/compare DMA selection"] + pub const fn ccds(&self) -> super::vals::Ccds { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Ccds(val as u8) + } + #[doc = "Capture/compare DMA selection"] + pub fn set_ccds(&mut self, val: super::vals::Ccds) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "TI1 selection"] + pub const fn ti1s(&self) -> super::vals::Tis { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Tis(val as u8) + } + #[doc = "TI1 selection"] + pub fn set_ti1s(&mut self, val: super::vals::Tis) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Output Idle state 1"] + pub fn ois(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 8usize + n * 2usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output Idle state 1"] + pub fn set_ois(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 8usize + n * 2usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Output Idle state 1"] + pub const fn ois1n(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 1"] + pub fn set_ois1n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Output Idle state 2"] + pub const fn ois2n(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 2"] + pub fn set_ois2n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Output Idle state 3"] + pub const fn ois3n(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 3"] + pub fn set_ois3n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + } + impl Default for Cr2Adv { + fn default() -> Cr2Adv { + Cr2Adv(0) + } + } + #[doc = "capture/compare mode register 2 (output mode)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcmrOutput(pub u32); + impl CcmrOutput { + #[doc = "Capture/Compare 3 selection"] + pub fn ccs(&self, n: usize) -> super::vals::CcmrOutputCcs { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + super::vals::CcmrOutputCcs(val as u8) + } + #[doc = "Capture/Compare 3 selection"] + pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrOutputCcs) { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Output compare 3 fast enable"] + pub fn ocfe(&self, n: usize) -> bool { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output compare 3 fast enable"] + pub fn set_ocfe(&mut self, n: usize, val: bool) { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Output compare 3 preload enable"] + pub fn ocpe(&self, n: usize) -> super::vals::Ocpe { + assert!(n < 2usize); + let offs = 3usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Ocpe(val as u8) + } + #[doc = "Output compare 3 preload enable"] + pub fn set_ocpe(&mut self, n: usize, val: super::vals::Ocpe) { + assert!(n < 2usize); + let offs = 3usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Output compare 3 mode"] + pub fn ocm(&self, n: usize) -> super::vals::Ocm { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + let val = (self.0 >> offs) & 0x07; + super::vals::Ocm(val as u8) + } + #[doc = "Output compare 3 mode"] + pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + self.0 = (self.0 & !(0x07 << offs)) | (((val.0 as u32) & 0x07) << offs); + } + #[doc = "Output compare 3 clear enable"] + pub fn occe(&self, n: usize) -> bool { + assert!(n < 2usize); + let offs = 7usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output compare 3 clear enable"] + pub fn set_occe(&mut self, n: usize, val: bool) { + assert!(n < 2usize); + let offs = 7usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcmrOutput { + fn default() -> CcmrOutput { + CcmrOutput(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1Basic(pub u32); + impl Cr1Basic { + #[doc = "Counter enable"] + pub const fn cen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Counter enable"] + pub fn set_cen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update disable"] + pub const fn udis(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Update disable"] + pub fn set_udis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Update request source"] + pub const fn urs(&self) -> super::vals::Urs { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Urs(val as u8) + } + #[doc = "Update request source"] + pub fn set_urs(&mut self, val: super::vals::Urs) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "One-pulse mode"] + pub const fn opm(&self) -> super::vals::Opm { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Opm(val as u8) + } + #[doc = "One-pulse mode"] + pub fn set_opm(&mut self, val: super::vals::Opm) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Auto-reload preload enable"] + pub const fn arpe(&self) -> super::vals::Arpe { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Arpe(val as u8) + } + #[doc = "Auto-reload preload enable"] + pub fn set_arpe(&mut self, val: super::vals::Arpe) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + } + impl Default for Cr1Basic { + fn default() -> Cr1Basic { + Cr1Basic(0) + } + } + #[doc = "auto-reload register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Arr16(pub u32); + impl Arr16 { + #[doc = "Auto-reload value"] + pub const fn arr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Auto-reload value"] + pub fn set_arr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Arr16 { + fn default() -> Arr16 { + Arr16(0) + } + } + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierGp(pub u32); + impl DierGp { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn ccie(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn set_ccie(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Trigger interrupt enable"] + pub const fn tie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt enable"] + pub fn set_tie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn ccde(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn set_ccde(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Trigger DMA request enable"] + pub const fn tde(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Trigger DMA request enable"] + pub fn set_tde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for DierGp { + fn default() -> DierGp { + DierGp(0) + } + } + #[doc = "capture/compare mode register 1 (input mode)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcmrInput(pub u32); + impl CcmrInput { + #[doc = "Capture/Compare 1 selection"] + pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + super::vals::CcmrInputCcs(val as u8) + } + #[doc = "Capture/Compare 1 selection"] + pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Input capture 1 prescaler"] + pub fn icpsc(&self, n: usize) -> u8 { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + val as u8 + } + #[doc = "Input capture 1 prescaler"] + pub fn set_icpsc(&mut self, n: usize, val: u8) { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs); + } + #[doc = "Input capture 1 filter"] + pub fn icf(&self, n: usize) -> super::vals::Icf { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + let val = (self.0 >> offs) & 0x0f; + super::vals::Icf(val as u8) + } + #[doc = "Input capture 1 filter"] + pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); + } + } + impl Default for CcmrInput { + fn default() -> CcmrInput { + CcmrInput(0) + } + } + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierBasic(pub u32); + impl DierBasic { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for DierBasic { + fn default() -> DierBasic { + DierBasic(0) + } + } + #[doc = "capture/compare enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcerAdv(pub u32); + impl CcerAdv { + #[doc = "Capture/Compare 1 output enable"] + pub fn cce(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output enable"] + pub fn set_cce(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 complementary output enable"] + pub fn ccne(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 complementary output enable"] + pub fn set_ccne(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccnp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccnp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcerAdv { + fn default() -> CcerAdv { + CcerAdv(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrBasic(pub u32); + impl SrBasic { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for SrBasic { + fn default() -> SrBasic { + SrBasic(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1Gp(pub u32); + impl Cr1Gp { + #[doc = "Counter enable"] + pub const fn cen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Counter enable"] + pub fn set_cen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update disable"] + pub const fn udis(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Update disable"] + pub fn set_udis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Update request source"] + pub const fn urs(&self) -> super::vals::Urs { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Urs(val as u8) + } + #[doc = "Update request source"] + pub fn set_urs(&mut self, val: super::vals::Urs) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "One-pulse mode"] + pub const fn opm(&self) -> super::vals::Opm { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Opm(val as u8) + } + #[doc = "One-pulse mode"] + pub fn set_opm(&mut self, val: super::vals::Opm) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Direction"] + pub const fn dir(&self) -> super::vals::Dir { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Dir(val as u8) + } + #[doc = "Direction"] + pub fn set_dir(&mut self, val: super::vals::Dir) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Center-aligned mode selection"] + pub const fn cms(&self) -> super::vals::Cms { + let val = (self.0 >> 5usize) & 0x03; + super::vals::Cms(val as u8) + } + #[doc = "Center-aligned mode selection"] + pub fn set_cms(&mut self, val: super::vals::Cms) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize); + } + #[doc = "Auto-reload preload enable"] + pub const fn arpe(&self) -> super::vals::Arpe { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Arpe(val as u8) + } + #[doc = "Auto-reload preload enable"] + pub fn set_arpe(&mut self, val: super::vals::Arpe) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Clock division"] + pub const fn ckd(&self) -> super::vals::Ckd { + let val = (self.0 >> 8usize) & 0x03; + super::vals::Ckd(val as u8) + } + #[doc = "Clock division"] + pub fn set_ckd(&mut self, val: super::vals::Ckd) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); + } + } + impl Default for Cr1Gp { + fn default() -> Cr1Gp { + Cr1Gp(0) + } + } + #[doc = "counter"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cnt16(pub u32); + impl Cnt16 { + #[doc = "counter value"] + pub const fn cnt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "counter value"] + pub fn set_cnt(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Cnt16 { + fn default() -> Cnt16 { + Cnt16(0) } } } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etp(pub u8); + impl Etp { + #[doc = "ETR is noninverted, active at high level or rising edge"] + pub const NOTINVERTED: Self = Self(0); + #[doc = "ETR is inverted, active at low level or falling edge"] + pub const INVERTED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Opm(pub u8); + impl Opm { + #[doc = "Counter is not stopped at update event"] + pub const DISABLED: Self = Self(0); + #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Arpe(pub u8); + impl Arpe { + #[doc = "TIMx_APRR register is not buffered"] + pub const DISABLED: Self = Self(0); + #[doc = "TIMx_APRR register is buffered"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etf(pub u8); + impl Etf { + #[doc = "No filter, sampling is done at fDTS"] + pub const NOFILTER: Self = Self(0); + #[doc = "fSAMPLING=fCK_INT, N=2"] + pub const FCK_INT_N2: Self = Self(0x01); + #[doc = "fSAMPLING=fCK_INT, N=4"] + pub const FCK_INT_N4: Self = Self(0x02); + #[doc = "fSAMPLING=fCK_INT, N=8"] + pub const FCK_INT_N8: Self = Self(0x03); + #[doc = "fSAMPLING=fDTS/2, N=6"] + pub const FDTS_DIV2_N6: Self = Self(0x04); + #[doc = "fSAMPLING=fDTS/2, N=8"] + pub const FDTS_DIV2_N8: Self = Self(0x05); + #[doc = "fSAMPLING=fDTS/4, N=6"] + pub const FDTS_DIV4_N6: Self = Self(0x06); + #[doc = "fSAMPLING=fDTS/4, N=8"] + pub const FDTS_DIV4_N8: Self = Self(0x07); + #[doc = "fSAMPLING=fDTS/8, N=6"] + pub const FDTS_DIV8_N6: Self = Self(0x08); + #[doc = "fSAMPLING=fDTS/8, N=8"] + pub const FDTS_DIV8_N8: Self = Self(0x09); + #[doc = "fSAMPLING=fDTS/16, N=5"] + pub const FDTS_DIV16_N5: Self = Self(0x0a); + #[doc = "fSAMPLING=fDTS/16, N=6"] + pub const FDTS_DIV16_N6: Self = Self(0x0b); + #[doc = "fSAMPLING=fDTS/16, N=8"] + pub const FDTS_DIV16_N8: Self = Self(0x0c); + #[doc = "fSAMPLING=fDTS/32, N=5"] + pub const FDTS_DIV32_N5: Self = Self(0x0d); + #[doc = "fSAMPLING=fDTS/32, N=6"] + pub const FDTS_DIV32_N6: Self = Self(0x0e); + #[doc = "fSAMPLING=fDTS/32, N=8"] + pub const FDTS_DIV32_N8: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ocm(pub u8); + impl Ocm { + #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] + pub const FROZEN: Self = Self(0); + #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] + pub const ACTIVEONMATCH: Self = Self(0x01); + #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] + pub const INACTIVEONMATCH: Self = Self(0x02); + #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] + pub const TOGGLE: Self = Self(0x03); + #[doc = "OCyREF is forced low"] + pub const FORCEINACTIVE: Self = Self(0x04); + #[doc = "OCyREF is forced high"] + pub const FORCEACTIVE: Self = Self(0x05); + #[doc = "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active"] + pub const PWMMODE1: Self = Self(0x06); + #[doc = "Inversely to PwmMode1"] + pub const PWMMODE2: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Urs(pub u8); + impl Urs { + #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"] + pub const ANYEVENT: Self = Self(0); + #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"] + pub const COUNTERONLY: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Icf(pub u8); + impl Icf { + #[doc = "No filter, sampling is done at fDTS"] + pub const NOFILTER: Self = Self(0); + #[doc = "fSAMPLING=fCK_INT, N=2"] + pub const FCK_INT_N2: Self = Self(0x01); + #[doc = "fSAMPLING=fCK_INT, N=4"] + pub const FCK_INT_N4: Self = Self(0x02); + #[doc = "fSAMPLING=fCK_INT, N=8"] + pub const FCK_INT_N8: Self = Self(0x03); + #[doc = "fSAMPLING=fDTS/2, N=6"] + pub const FDTS_DIV2_N6: Self = Self(0x04); + #[doc = "fSAMPLING=fDTS/2, N=8"] + pub const FDTS_DIV2_N8: Self = Self(0x05); + #[doc = "fSAMPLING=fDTS/4, N=6"] + pub const FDTS_DIV4_N6: Self = Self(0x06); + #[doc = "fSAMPLING=fDTS/4, N=8"] + pub const FDTS_DIV4_N8: Self = Self(0x07); + #[doc = "fSAMPLING=fDTS/8, N=6"] + pub const FDTS_DIV8_N6: Self = Self(0x08); + #[doc = "fSAMPLING=fDTS/8, N=8"] + pub const FDTS_DIV8_N8: Self = Self(0x09); + #[doc = "fSAMPLING=fDTS/16, N=5"] + pub const FDTS_DIV16_N5: Self = Self(0x0a); + #[doc = "fSAMPLING=fDTS/16, N=6"] + pub const FDTS_DIV16_N6: Self = Self(0x0b); + #[doc = "fSAMPLING=fDTS/16, N=8"] + pub const FDTS_DIV16_N8: Self = Self(0x0c); + #[doc = "fSAMPLING=fDTS/32, N=5"] + pub const FDTS_DIV32_N5: Self = Self(0x0d); + #[doc = "fSAMPLING=fDTS/32, N=6"] + pub const FDTS_DIV32_N6: Self = Self(0x0e); + #[doc = "fSAMPLING=fDTS/32, N=8"] + pub const FDTS_DIV32_N8: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Msm(pub u8); + impl Msm { + #[doc = "No action"] + pub const NOSYNC: Self = Self(0); + #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."] + pub const SYNC: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ece(pub u8); + impl Ece { + #[doc = "External clock mode 2 disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Tis(pub u8); + impl Tis { + #[doc = "The TIMx_CH1 pin is connected to TI1 input"] + pub const NORMAL: Self = Self(0); + #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"] + pub const XOR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ossr(pub u8); + impl Ossr { + #[doc = "When inactive, OC/OCN outputs are disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"] + pub const IDLELEVEL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Counter used as upcounter"] + pub const UP: Self = Self(0); + #[doc = "Counter used as downcounter"] + pub const DOWN: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mms(pub u8); + impl Mms { + #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"] + pub const RESET: Self = Self(0); + #[doc = "The counter enable signal, CNT_EN, is used as trigger output"] + pub const ENABLE: Self = Self(0x01); + #[doc = "The update event is selected as trigger output"] + pub const UPDATE: Self = Self(0x02); + #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"] + pub const COMPAREPULSE: Self = Self(0x03); + #[doc = "OC1REF signal is used as trigger output"] + pub const COMPAREOC1: Self = Self(0x04); + #[doc = "OC2REF signal is used as trigger output"] + pub const COMPAREOC2: Self = Self(0x05); + #[doc = "OC3REF signal is used as trigger output"] + pub const COMPAREOC3: Self = Self(0x06); + #[doc = "OC4REF signal is used as trigger output"] + pub const COMPAREOC4: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ckd(pub u8); + impl Ckd { + #[doc = "t_DTS = t_CK_INT"] + pub const DIV1: Self = Self(0); + #[doc = "t_DTS = 2 × t_CK_INT"] + pub const DIV2: Self = Self(0x01); + #[doc = "t_DTS = 4 × t_CK_INT"] + pub const DIV4: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ocpe(pub u8); + impl Ocpe { + #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"] + pub const DISABLED: Self = Self(0); + #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ossi(pub u8); + impl Ossi { + #[doc = "When inactive, OC/OCN outputs are disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "When inactive, OC/OCN outputs are forced to idle level"] + pub const IDLELEVEL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etps(pub u8); + impl Etps { + #[doc = "Prescaler OFF"] + pub const DIV1: Self = Self(0); + #[doc = "ETRP frequency divided by 2"] + pub const DIV2: Self = Self(0x01); + #[doc = "ETRP frequency divided by 4"] + pub const DIV4: Self = Self(0x02); + #[doc = "ETRP frequency divided by 8"] + pub const DIV8: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct CcmrInputCcs(pub u8); + impl CcmrInputCcs { + #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"] + pub const TI4: Self = Self(0x01); + #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"] + pub const TI3: Self = Self(0x02); + #[doc = "CCx channel is configured as input, ICx is mapped on TRC"] + pub const TRC: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cms(pub u8); + impl Cms { + #[doc = "The counter counts up or down depending on the direction bit"] + pub const EDGEALIGNED: Self = Self(0); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] + pub const CENTERALIGNED1: Self = Self(0x01); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] + pub const CENTERALIGNED2: Self = Self(0x02); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] + pub const CENTERALIGNED3: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ts(pub u8); + impl Ts { + #[doc = "Internal Trigger 0 (ITR0)"] + pub const ITR0: Self = Self(0); + #[doc = "Internal Trigger 1 (ITR1)"] + pub const ITR1: Self = Self(0x01); + #[doc = "Internal Trigger 2 (ITR2)"] + pub const ITR2: Self = Self(0x02); + #[doc = "TI1 Edge Detector (TI1F_ED)"] + pub const TI1F_ED: Self = Self(0x04); + #[doc = "Filtered Timer Input 1 (TI1FP1)"] + pub const TI1FP1: Self = Self(0x05); + #[doc = "Filtered Timer Input 2 (TI2FP2)"] + pub const TI2FP2: Self = Self(0x06); + #[doc = "External Trigger input (ETRF)"] + pub const ETRF: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Sms(pub u8); + impl Sms { + #[doc = "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] + pub const DISABLED: Self = Self(0); + #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."] + pub const ENCODER_MODE_1: Self = Self(0x01); + #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."] + pub const ENCODER_MODE_2: Self = Self(0x02); + #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."] + pub const ENCODER_MODE_3: Self = Self(0x03); + #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."] + pub const RESET_MODE: Self = Self(0x04); + #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."] + pub const GATED_MODE: Self = Self(0x05); + #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."] + pub const TRIGGER_MODE: Self = Self(0x06); + #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."] + pub const EXT_CLOCK_MODE: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ccds(pub u8); + impl Ccds { + #[doc = "CCx DMA request sent when CCx event occurs"] + pub const ONCOMPARE: Self = Self(0); + #[doc = "CCx DMA request sent when update event occurs"] + pub const ONUPDATE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct CcmrOutputCcs(pub u8); + impl CcmrOutputCcs { + #[doc = "CCx channel is configured as output"] + pub const OUTPUT: Self = Self(0); + } + } } -pub mod rng_v1 { +pub mod spi_v2 { use crate::generic::*; - #[doc = "Random number generator"] + #[doc = "Serial peripheral interface"] #[derive(Copy, Clone)] - pub struct Rng(pub *mut u8); - unsafe impl Send for Rng {} - unsafe impl Sync for Rng {} - impl Rng { - #[doc = "control register"] - pub fn cr(self) -> Reg { + pub struct Spi(pub *mut u8); + unsafe impl Send for Spi {} + unsafe impl Sync for Spi {} + impl Spi { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(0usize)) } } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } #[doc = "status register"] pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } + unsafe { Reg::from_ptr(self.0.add(8usize)) } } #[doc = "data register"] - pub fn dr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "CRC polynomial register"] + pub fn crcpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "RX CRC register"] + pub fn rxcrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "TX CRC register"] + pub fn txcrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mstr(pub u8); + impl Mstr { + #[doc = "Slave configuration"] + pub const SLAVE: Self = Self(0); + #[doc = "Master configuration"] + pub const MASTER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frxth(pub u8); + impl Frxth { + #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"] + pub const HALF: Self = Self(0); + #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"] + pub const QUARTER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpol(pub u8); + impl Cpol { + #[doc = "CK to 0 when idle"] + pub const IDLELOW: Self = Self(0); + #[doc = "CK to 1 when idle"] + pub const IDLEHIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct LdmaTx(pub u8); + impl LdmaTx { + #[doc = "Number of data to transfer for transmit is even"] + pub const EVEN: Self = Self(0); + #[doc = "Number of data to transfer for transmit is odd"] + pub const ODD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lsbfirst(pub u8); + impl Lsbfirst { + #[doc = "Data is transmitted/received with the MSB first"] + pub const MSBFIRST: Self = Self(0); + #[doc = "Data is transmitted/received with the LSB first"] + pub const LSBFIRST: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rxonly(pub u8); + impl Rxonly { + #[doc = "Full duplex (Transmit and receive)"] + pub const FULLDUPLEX: Self = Self(0); + #[doc = "Output disabled (Receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct LdmaRx(pub u8); + impl LdmaRx { + #[doc = "Number of data to transfer for receive is even"] + pub const EVEN: Self = Self(0); + #[doc = "Number of data to transfer for receive is odd"] + pub const ODD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frer(pub u8); + impl Frer { + #[doc = "No frame format error"] + pub const NOERROR: Self = Self(0); + #[doc = "A frame format error occurred"] + pub const ERROR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frf(pub u8); + impl Frf { + #[doc = "SPI Motorola mode"] + pub const MOTOROLA: Self = Self(0); + #[doc = "SPI TI mode"] + pub const TI: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Crcnext(pub u8); + impl Crcnext { + #[doc = "Next transmit value is from Tx buffer"] + pub const TXBUFFER: Self = Self(0); + #[doc = "Next transmit value is from Tx CRC register"] + pub const CRC: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Crcl(pub u8); + impl Crcl { + #[doc = "8-bit CRC length"] + pub const EIGHTBIT: Self = Self(0); + #[doc = "16-bit CRC length"] + pub const SIXTEENBIT: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ds(pub u8); + impl Ds { + #[doc = "4-bit"] + pub const FOURBIT: Self = Self(0x03); + #[doc = "5-bit"] + pub const FIVEBIT: Self = Self(0x04); + #[doc = "6-bit"] + pub const SIXBIT: Self = Self(0x05); + #[doc = "7-bit"] + pub const SEVENBIT: Self = Self(0x06); + #[doc = "8-bit"] + pub const EIGHTBIT: Self = Self(0x07); + #[doc = "9-bit"] + pub const NINEBIT: Self = Self(0x08); + #[doc = "10-bit"] + pub const TENBIT: Self = Self(0x09); + #[doc = "11-bit"] + pub const ELEVENBIT: Self = Self(0x0a); + #[doc = "12-bit"] + pub const TWELVEBIT: Self = Self(0x0b); + #[doc = "13-bit"] + pub const THIRTEENBIT: Self = Self(0x0c); + #[doc = "14-bit"] + pub const FOURTEENBIT: Self = Self(0x0d); + #[doc = "15-bit"] + pub const FIFTEENBIT: Self = Self(0x0e); + #[doc = "16-bit"] + pub const SIXTEENBIT: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidioe(pub u8); + impl Bidioe { + #[doc = "Output disabled (receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0); + #[doc = "Output enabled (transmit-only mode)"] + pub const OUTPUTENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Br(pub u8); + impl Br { + #[doc = "f_PCLK / 2"] + pub const DIV2: Self = Self(0); + #[doc = "f_PCLK / 4"] + pub const DIV4: Self = Self(0x01); + #[doc = "f_PCLK / 8"] + pub const DIV8: Self = Self(0x02); + #[doc = "f_PCLK / 16"] + pub const DIV16: Self = Self(0x03); + #[doc = "f_PCLK / 32"] + pub const DIV32: Self = Self(0x04); + #[doc = "f_PCLK / 64"] + pub const DIV64: Self = Self(0x05); + #[doc = "f_PCLK / 128"] + pub const DIV128: Self = Self(0x06); + #[doc = "f_PCLK / 256"] + pub const DIV256: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRSTEDGE: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECONDEDGE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frlvlr(pub u8); + impl Frlvlr { + #[doc = "Rx FIFO Empty"] + pub const EMPTY: Self = Self(0); + #[doc = "Rx 1/4 FIFO"] + pub const QUARTER: Self = Self(0x01); + #[doc = "Rx 1/2 FIFO"] + pub const HALF: Self = Self(0x02); + #[doc = "Rx FIFO full"] + pub const FULL: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidimode(pub u8); + impl Bidimode { + #[doc = "2-line unidirectional data mode selected"] + pub const UNIDIRECTIONAL: Self = Self(0); + #[doc = "1-line bidirectional data mode selected"] + pub const BIDIRECTIONAL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ftlvlr(pub u8); + impl Ftlvlr { + #[doc = "Tx FIFO Empty"] + pub const EMPTY: Self = Self(0); + #[doc = "Tx 1/4 FIFO"] + pub const QUARTER: Self = Self(0x01); + #[doc = "Tx 1/2 FIFO"] + pub const HALF: Self = Self(0x02); + #[doc = "Tx FIFO full"] + pub const FULL: Self = Self(0x03); } } pub mod regs { use crate::generic::*; - #[doc = "control register"] + #[doc = "control register 1"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr(pub u32); - impl Cr { - #[doc = "Random number generator enable"] - pub const fn rngen(&self) -> bool { + pub struct Cr1(pub u32); + impl Cr1 { + #[doc = "Clock phase"] + pub const fn cpha(&self) -> super::vals::Cpha { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Cpha(val as u8) + } + #[doc = "Clock phase"] + pub fn set_cpha(&mut self, val: super::vals::Cpha) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); + } + #[doc = "Clock polarity"] + pub const fn cpol(&self) -> super::vals::Cpol { + let val = (self.0 >> 1usize) & 0x01; + super::vals::Cpol(val as u8) + } + #[doc = "Clock polarity"] + pub fn set_cpol(&mut self, val: super::vals::Cpol) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); + } + #[doc = "Master selection"] + pub const fn mstr(&self) -> super::vals::Mstr { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Mstr(val as u8) + } + #[doc = "Master selection"] + pub fn set_mstr(&mut self, val: super::vals::Mstr) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Baud rate control"] + pub const fn br(&self) -> super::vals::Br { + let val = (self.0 >> 3usize) & 0x07; + super::vals::Br(val as u8) + } + #[doc = "Baud rate control"] + pub fn set_br(&mut self, val: super::vals::Br) { + self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); + } + #[doc = "SPI enable"] + pub const fn spe(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "SPI enable"] + pub fn set_spe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Frame format"] + pub const fn lsbfirst(&self) -> super::vals::Lsbfirst { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Lsbfirst(val as u8) + } + #[doc = "Frame format"] + pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Internal slave select"] + pub const fn ssi(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Internal slave select"] + pub fn set_ssi(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Software slave management"] + pub const fn ssm(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Software slave management"] + pub fn set_ssm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Receive only"] + pub const fn rxonly(&self) -> super::vals::Rxonly { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Rxonly(val as u8) + } + #[doc = "Receive only"] + pub fn set_rxonly(&mut self, val: super::vals::Rxonly) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "CRC length"] + pub const fn crcl(&self) -> super::vals::Crcl { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Crcl(val as u8) + } + #[doc = "CRC length"] + pub fn set_crcl(&mut self, val: super::vals::Crcl) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "CRC transfer next"] + pub const fn crcnext(&self) -> super::vals::Crcnext { + let val = (self.0 >> 12usize) & 0x01; + super::vals::Crcnext(val as u8) + } + #[doc = "CRC transfer next"] + pub fn set_crcnext(&mut self, val: super::vals::Crcnext) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "Hardware CRC calculation enable"] + pub const fn crcen(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Hardware CRC calculation enable"] + pub fn set_crcen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Output enable in bidirectional mode"] + pub const fn bidioe(&self) -> super::vals::Bidioe { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Bidioe(val as u8) + } + #[doc = "Output enable in bidirectional mode"] + pub fn set_bidioe(&mut self, val: super::vals::Bidioe) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + #[doc = "Bidirectional data mode enable"] + pub const fn bidimode(&self) -> super::vals::Bidimode { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Bidimode(val as u8) + } + #[doc = "Bidirectional data mode enable"] + pub fn set_bidimode(&mut self, val: super::vals::Bidimode) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + } + impl Default for Cr1 { + fn default() -> Cr1 { + Cr1(0) + } + } + #[doc = "RX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rxcrcr(pub u32); + impl Rxcrcr { + #[doc = "Rx CRC register"] + pub const fn rx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Rx CRC register"] + pub fn set_rx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Rxcrcr { + fn default() -> Rxcrcr { + Rxcrcr(0) + } + } + #[doc = "CRC polynomial register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Crcpr(pub u32); + impl Crcpr { + #[doc = "CRC polynomial register"] + pub const fn crcpoly(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "CRC polynomial register"] + pub fn set_crcpoly(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Crcpr { + fn default() -> Crcpr { + Crcpr(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2(pub u32); + impl Cr2 { + #[doc = "Rx buffer DMA enable"] + pub const fn rxdmaen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Rx buffer DMA enable"] + pub fn set_rxdmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Tx buffer DMA enable"] + pub const fn txdmaen(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Tx buffer DMA enable"] + pub fn set_txdmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "SS output enable"] + pub const fn ssoe(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Random number generator enable"] - pub fn set_rngen(&mut self, val: bool) { + #[doc = "SS output enable"] + pub fn set_ssoe(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Interrupt enable"] - pub const fn ie(&self) -> bool { + #[doc = "NSS pulse management"] + pub const fn nssp(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Interrupt enable"] - pub fn set_ie(&mut self, val: bool) { + #[doc = "NSS pulse management"] + pub fn set_nssp(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } + #[doc = "Frame format"] + pub const fn frf(&self) -> super::vals::Frf { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Frf(val as u8) + } + #[doc = "Frame format"] + pub fn set_frf(&mut self, val: super::vals::Frf) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Error interrupt enable"] + pub const fn errie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_errie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "RX buffer not empty interrupt enable"] + pub const fn rxneie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "RX buffer not empty interrupt enable"] + pub fn set_rxneie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Tx buffer empty interrupt enable"] + pub const fn txeie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Tx buffer empty interrupt enable"] + pub fn set_txeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Data size"] + pub const fn ds(&self) -> super::vals::Ds { + let val = (self.0 >> 8usize) & 0x0f; + super::vals::Ds(val as u8) + } + #[doc = "Data size"] + pub fn set_ds(&mut self, val: super::vals::Ds) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); + } + #[doc = "FIFO reception threshold"] + pub const fn frxth(&self) -> super::vals::Frxth { + let val = (self.0 >> 12usize) & 0x01; + super::vals::Frxth(val as u8) + } + #[doc = "FIFO reception threshold"] + pub fn set_frxth(&mut self, val: super::vals::Frxth) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "Last DMA transfer for reception"] + pub const fn ldma_rx(&self) -> super::vals::LdmaRx { + let val = (self.0 >> 13usize) & 0x01; + super::vals::LdmaRx(val as u8) + } + #[doc = "Last DMA transfer for reception"] + pub fn set_ldma_rx(&mut self, val: super::vals::LdmaRx) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val.0 as u32) & 0x01) << 13usize); + } + #[doc = "Last DMA transfer for transmission"] + pub const fn ldma_tx(&self) -> super::vals::LdmaTx { + let val = (self.0 >> 14usize) & 0x01; + super::vals::LdmaTx(val as u8) + } + #[doc = "Last DMA transfer for transmission"] + pub fn set_ldma_tx(&mut self, val: super::vals::LdmaTx) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } } - impl Default for Cr { - fn default() -> Cr { - Cr(0) + impl Default for Cr2 { + fn default() -> Cr2 { + Cr2(0) + } + } + #[doc = "data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dr(pub u32); + impl Dr { + #[doc = "Data register"] + pub const fn dr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Data register"] + pub fn set_dr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Dr { + fn default() -> Dr { + Dr(0) } } #[doc = "status register"] @@ -5791,57 +4324,1022 @@ pub mod rng_v1 { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Sr(pub u32); impl Sr { - #[doc = "Data ready"] - pub const fn drdy(&self) -> bool { + #[doc = "Receive buffer not empty"] + pub const fn rxne(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Data ready"] - pub fn set_drdy(&mut self, val: bool) { + #[doc = "Receive buffer not empty"] + pub fn set_rxne(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Clock error current status"] - pub const fn cecs(&self) -> bool { + #[doc = "Transmit buffer empty"] + pub const fn txe(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Clock error current status"] - pub fn set_cecs(&mut self, val: bool) { + #[doc = "Transmit buffer empty"] + pub fn set_txe(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Seed error current status"] - pub const fn secs(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; + #[doc = "CRC error flag"] + pub const fn crcerr(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Seed error current status"] - pub fn set_secs(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + #[doc = "CRC error flag"] + pub fn set_crcerr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Clock error interrupt status"] - pub const fn ceis(&self) -> bool { + #[doc = "Mode fault"] + pub const fn modf(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Clock error interrupt status"] - pub fn set_ceis(&mut self, val: bool) { + #[doc = "Mode fault"] + pub fn set_modf(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Seed error interrupt status"] - pub const fn seis(&self) -> bool { + #[doc = "Overrun flag"] + pub const fn ovr(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Seed error interrupt status"] - pub fn set_seis(&mut self, val: bool) { + #[doc = "Overrun flag"] + pub fn set_ovr(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } + #[doc = "Busy flag"] + pub const fn bsy(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Busy flag"] + pub fn set_bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Frame format error"] + pub const fn fre(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Frame format error"] + pub fn set_fre(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "FIFO reception level"] + pub const fn frlvl(&self) -> u8 { + let val = (self.0 >> 9usize) & 0x03; + val as u8 + } + #[doc = "FIFO reception level"] + pub fn set_frlvl(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 9usize)) | (((val as u32) & 0x03) << 9usize); + } + #[doc = "FIFO Transmission Level"] + pub const fn ftlvl(&self) -> u8 { + let val = (self.0 >> 11usize) & 0x03; + val as u8 + } + #[doc = "FIFO Transmission Level"] + pub fn set_ftlvl(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 11usize)) | (((val as u32) & 0x03) << 11usize); + } } impl Default for Sr { fn default() -> Sr { Sr(0) } } + #[doc = "TX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Txcrcr(pub u32); + impl Txcrcr { + #[doc = "Tx CRC register"] + pub const fn tx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Tx CRC register"] + pub fn set_tx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Txcrcr { + fn default() -> Txcrcr { + Txcrcr(0) + } + } + } +} +pub mod usart_v1 { + use crate::generic::*; + #[doc = "Universal synchronous asynchronous receiver transmitter"] + #[derive(Copy, Clone)] + pub struct Usart(pub *mut u8); + unsafe impl Send for Usart {} + unsafe impl Sync for Usart {} + impl Usart { + #[doc = "Status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Baud rate register"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Control register 3"] + pub fn cr3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "Guard time and prescaler register"] + pub fn gtpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + #[doc = "Universal asynchronous receiver transmitter"] + #[derive(Copy, Clone)] + pub struct Uart(pub *mut u8); + unsafe impl Send for Uart {} + unsafe impl Sync for Uart {} + impl Uart { + #[doc = "Status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Baud rate register"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Control register 3"] + pub fn cr3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ps(pub u8); + impl Ps { + #[doc = "Even parity"] + pub const EVEN: Self = Self(0); + #[doc = "Odd parity"] + pub const ODD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Irlp(pub u8); + impl Irlp { + #[doc = "Normal mode"] + pub const NORMAL: Self = Self(0); + #[doc = "Low-power mode"] + pub const LOWPOWER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Hdsel(pub u8); + impl Hdsel { + #[doc = "Half duplex mode is not selected"] + pub const FULLDUPLEX: Self = Self(0); + #[doc = "Half duplex mode is selected"] + pub const HALFDUPLEX: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpol(pub u8); + impl Cpol { + #[doc = "Steady low value on CK pin outside transmission window"] + pub const LOW: Self = Self(0); + #[doc = "Steady high value on CK pin outside transmission window"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Wake(pub u8); + impl Wake { + #[doc = "USART wakeup on idle line"] + pub const IDLELINE: Self = Self(0); + #[doc = "USART wakeup on address mark"] + pub const ADDRESSMARK: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Sbk(pub u8); + impl Sbk { + #[doc = "No break character is transmitted"] + pub const NOBREAK: Self = Self(0); + #[doc = "Break character transmitted"] + pub const BREAK: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct M(pub u8); + impl M { + #[doc = "8 data bits"] + pub const M8: Self = Self(0); + #[doc = "9 data bits"] + pub const M9: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRST: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECOND: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rwu(pub u8); + impl Rwu { + #[doc = "Receiver in active mode"] + pub const ACTIVE: Self = Self(0); + #[doc = "Receiver in mute mode"] + pub const MUTE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lbdl(pub u8); + impl Lbdl { + #[doc = "10-bit break detection"] + pub const LBDL10: Self = Self(0); + #[doc = "11-bit break detection"] + pub const LBDL11: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Stop(pub u8); + impl Stop { + #[doc = "1 stop bit"] + pub const STOP1: Self = Self(0); + #[doc = "0.5 stop bits"] + pub const STOP0P5: Self = Self(0x01); + #[doc = "2 stop bits"] + pub const STOP2: Self = Self(0x02); + #[doc = "1.5 stop bits"] + pub const STOP1P5: Self = Self(0x03); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "Guard time and prescaler register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Gtpr(pub u32); + impl Gtpr { + #[doc = "Prescaler value"] + pub const fn psc(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Prescaler value"] + pub fn set_psc(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Guard time value"] + pub const fn gt(&self) -> u8 { + let val = (self.0 >> 8usize) & 0xff; + val as u8 + } + #[doc = "Guard time value"] + pub fn set_gt(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); + } + } + impl Default for Gtpr { + fn default() -> Gtpr { + Gtpr(0) + } + } + #[doc = "Control register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr3Usart(pub u32); + impl Cr3Usart { + #[doc = "Error interrupt enable"] + pub const fn eie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_eie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "IrDA mode enable"] + pub const fn iren(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "IrDA mode enable"] + pub fn set_iren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "IrDA low-power"] + pub const fn irlp(&self) -> super::vals::Irlp { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Irlp(val as u8) + } + #[doc = "IrDA low-power"] + pub fn set_irlp(&mut self, val: super::vals::Irlp) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Half-duplex selection"] + pub const fn hdsel(&self) -> super::vals::Hdsel { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Hdsel(val as u8) + } + #[doc = "Half-duplex selection"] + pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Smartcard NACK enable"] + pub const fn nack(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Smartcard NACK enable"] + pub fn set_nack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Smartcard mode enable"] + pub const fn scen(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Smartcard mode enable"] + pub fn set_scen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "DMA enable receiver"] + pub const fn dmar(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "DMA enable receiver"] + pub fn set_dmar(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "DMA enable transmitter"] + pub const fn dmat(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "DMA enable transmitter"] + pub fn set_dmat(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "RTS enable"] + pub const fn rtse(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "RTS enable"] + pub fn set_rtse(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "CTS enable"] + pub const fn ctse(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "CTS enable"] + pub fn set_ctse(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "CTS interrupt enable"] + pub const fn ctsie(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "CTS interrupt enable"] + pub fn set_ctsie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + } + impl Default for Cr3Usart { + fn default() -> Cr3Usart { + Cr3Usart(0) + } + } + #[doc = "Control register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr3(pub u32); + impl Cr3 { + #[doc = "Error interrupt enable"] + pub const fn eie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_eie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "IrDA mode enable"] + pub const fn iren(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "IrDA mode enable"] + pub fn set_iren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "IrDA low-power"] + pub const fn irlp(&self) -> super::vals::Irlp { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Irlp(val as u8) + } + #[doc = "IrDA low-power"] + pub fn set_irlp(&mut self, val: super::vals::Irlp) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Half-duplex selection"] + pub const fn hdsel(&self) -> super::vals::Hdsel { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Hdsel(val as u8) + } + #[doc = "Half-duplex selection"] + pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "DMA enable receiver"] + pub const fn dmar(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "DMA enable receiver"] + pub fn set_dmar(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "DMA enable transmitter"] + pub const fn dmat(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "DMA enable transmitter"] + pub fn set_dmat(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for Cr3 { + fn default() -> Cr3 { + Cr3(0) + } + } + #[doc = "Control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2(pub u32); + impl Cr2 { + #[doc = "Address of the USART node"] + pub const fn add(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Address of the USART node"] + pub fn set_add(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "lin break detection length"] + pub const fn lbdl(&self) -> super::vals::Lbdl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Lbdl(val as u8) + } + #[doc = "lin break detection length"] + pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "LIN break detection interrupt enable"] + pub const fn lbdie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection interrupt enable"] + pub fn set_lbdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "STOP bits"] + pub const fn stop(&self) -> super::vals::Stop { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Stop(val as u8) + } + #[doc = "STOP bits"] + pub fn set_stop(&mut self, val: super::vals::Stop) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "LIN mode enable"] + pub const fn linen(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "LIN mode enable"] + pub fn set_linen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for Cr2 { + fn default() -> Cr2 { + Cr2(0) + } + } + #[doc = "Control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1(pub u32); + impl Cr1 { + #[doc = "Send break"] + pub const fn sbk(&self) -> super::vals::Sbk { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Sbk(val as u8) + } + #[doc = "Send break"] + pub fn set_sbk(&mut self, val: super::vals::Sbk) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); + } + #[doc = "Receiver wakeup"] + pub const fn rwu(&self) -> super::vals::Rwu { + let val = (self.0 >> 1usize) & 0x01; + super::vals::Rwu(val as u8) + } + #[doc = "Receiver wakeup"] + pub fn set_rwu(&mut self, val: super::vals::Rwu) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); + } + #[doc = "Receiver enable"] + pub const fn re(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Receiver enable"] + pub fn set_re(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Transmitter enable"] + pub const fn te(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Transmitter enable"] + pub fn set_te(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE interrupt enable"] + pub const fn idleie(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE interrupt enable"] + pub fn set_idleie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "RXNE interrupt enable"] + pub const fn rxneie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "RXNE interrupt enable"] + pub fn set_rxneie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "TXE interrupt enable"] + pub const fn txeie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "TXE interrupt enable"] + pub fn set_txeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "PE interrupt enable"] + pub const fn peie(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "PE interrupt enable"] + pub fn set_peie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Parity selection"] + pub const fn ps(&self) -> super::vals::Ps { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Ps(val as u8) + } + #[doc = "Parity selection"] + pub fn set_ps(&mut self, val: super::vals::Ps) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Parity control enable"] + pub const fn pce(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Parity control enable"] + pub fn set_pce(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Wakeup method"] + pub const fn wake(&self) -> super::vals::Wake { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Wake(val as u8) + } + #[doc = "Wakeup method"] + pub fn set_wake(&mut self, val: super::vals::Wake) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "Word length"] + pub const fn m(&self) -> super::vals::M { + let val = (self.0 >> 12usize) & 0x01; + super::vals::M(val as u8) + } + #[doc = "Word length"] + pub fn set_m(&mut self, val: super::vals::M) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "USART enable"] + pub const fn ue(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "USART enable"] + pub fn set_ue(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + } + impl Default for Cr1 { + fn default() -> Cr1 { + Cr1(0) + } + } + #[doc = "Baud rate register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Brr(pub u32); + impl Brr { + #[doc = "fraction of USARTDIV"] + pub const fn div_fraction(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "fraction of USARTDIV"] + pub fn set_div_fraction(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "mantissa of USARTDIV"] + pub const fn div_mantissa(&self) -> u16 { + let val = (self.0 >> 4usize) & 0x0fff; + val as u16 + } + #[doc = "mantissa of USARTDIV"] + pub fn set_div_mantissa(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize); + } + } + impl Default for Brr { + fn default() -> Brr { + Brr(0) + } + } + #[doc = "Status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Parity error"] + pub const fn pe(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Parity error"] + pub fn set_pe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Framing error"] + pub const fn fe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Framing error"] + pub fn set_fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Noise error flag"] + pub const fn ne(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Noise error flag"] + pub fn set_ne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Overrun error"] + pub const fn ore(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Overrun error"] + pub fn set_ore(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE line detected"] + pub const fn idle(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE line detected"] + pub fn set_idle(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Read data register not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Read data register not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete"] + pub const fn tc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete"] + pub fn set_tc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Transmit data register empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Transmit data register empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "LIN break detection flag"] + pub const fn lbd(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection flag"] + pub fn set_lbd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + #[doc = "Status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrUsart(pub u32); + impl SrUsart { + #[doc = "Parity error"] + pub const fn pe(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Parity error"] + pub fn set_pe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Framing error"] + pub const fn fe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Framing error"] + pub fn set_fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Noise error flag"] + pub const fn ne(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Noise error flag"] + pub fn set_ne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Overrun error"] + pub const fn ore(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Overrun error"] + pub fn set_ore(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE line detected"] + pub const fn idle(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE line detected"] + pub fn set_idle(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Read data register not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Read data register not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete"] + pub const fn tc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete"] + pub fn set_tc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Transmit data register empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Transmit data register empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "LIN break detection flag"] + pub const fn lbd(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection flag"] + pub fn set_lbd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "CTS flag"] + pub const fn cts(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "CTS flag"] + pub fn set_cts(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + } + impl Default for SrUsart { + fn default() -> SrUsart { + SrUsart(0) + } + } + #[doc = "Data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dr(pub u32); + impl Dr { + #[doc = "Data value"] + pub const fn dr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x01ff; + val as u16 + } + #[doc = "Data value"] + pub fn set_dr(&mut self, val: u16) { + self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize); + } + } + impl Default for Dr { + fn default() -> Dr { + Dr(0) + } + } + #[doc = "Control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Usart(pub u32); + impl Cr2Usart { + #[doc = "Address of the USART node"] + pub const fn add(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Address of the USART node"] + pub fn set_add(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "lin break detection length"] + pub const fn lbdl(&self) -> super::vals::Lbdl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Lbdl(val as u8) + } + #[doc = "lin break detection length"] + pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "LIN break detection interrupt enable"] + pub const fn lbdie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection interrupt enable"] + pub fn set_lbdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Last bit clock pulse"] + pub const fn lbcl(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Last bit clock pulse"] + pub fn set_lbcl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Clock phase"] + pub const fn cpha(&self) -> super::vals::Cpha { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Cpha(val as u8) + } + #[doc = "Clock phase"] + pub fn set_cpha(&mut self, val: super::vals::Cpha) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Clock polarity"] + pub const fn cpol(&self) -> super::vals::Cpol { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Cpol(val as u8) + } + #[doc = "Clock polarity"] + pub fn set_cpol(&mut self, val: super::vals::Cpol) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Clock enable"] + pub const fn clken(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Clock enable"] + pub fn set_clken(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "STOP bits"] + pub const fn stop(&self) -> super::vals::Stop { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Stop(val as u8) + } + #[doc = "STOP bits"] + pub fn set_stop(&mut self, val: super::vals::Stop) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "LIN mode enable"] + pub const fn linen(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "LIN mode enable"] + pub fn set_linen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for Cr2Usart { + fn default() -> Cr2Usart { + Cr2Usart(0) + } + } } } pub mod syscfg_f4 { @@ -5872,6 +5370,44 @@ pub mod syscfg_f4 { } pub mod regs { use crate::generic::*; + #[doc = "memory remap register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Memrm(pub u32); + impl Memrm { + #[doc = "Memory mapping selection"] + pub const fn mem_mode(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x07; + val as u8 + } + #[doc = "Memory mapping selection"] + pub fn set_mem_mode(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); + } + #[doc = "Flash bank mode selection"] + pub const fn fb_mode(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Flash bank mode selection"] + pub fn set_fb_mode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "FMC memory mapping swap"] + pub const fn swp_fmc(&self) -> u8 { + let val = (self.0 >> 10usize) & 0x03; + val as u8 + } + #[doc = "FMC memory mapping swap"] + pub fn set_swp_fmc(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize); + } + } + impl Default for Memrm { + fn default() -> Memrm { + Memrm(0) + } + } #[doc = "Compensation cell control register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -5925,44 +5461,6 @@ pub mod syscfg_f4 { Exticr(0) } } - #[doc = "memory remap register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Memrm(pub u32); - impl Memrm { - #[doc = "Memory mapping selection"] - pub const fn mem_mode(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Memory mapping selection"] - pub fn set_mem_mode(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Flash bank mode selection"] - pub const fn fb_mode(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Flash bank mode selection"] - pub fn set_fb_mode(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "FMC memory mapping swap"] - pub const fn swp_fmc(&self) -> u8 { - let val = (self.0 >> 10usize) & 0x03; - val as u8 - } - #[doc = "FMC memory mapping swap"] - pub fn set_swp_fmc(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize); - } - } - impl Default for Memrm { - fn default() -> Memrm { - Memrm(0) - } - } #[doc = "peripheral mode configuration register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -6108,479 +5606,6 @@ pub mod sdmmc_v2 { } pub mod regs { use crate::generic::*; - #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dcntr(pub u32); - impl Dcntr { - #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] - pub const fn datacount(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x01ff_ffff; - val as u32 - } - #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] - pub fn set_datacount(&mut self, val: u32) { - self.0 = - (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); - } - } - impl Default for Dcntr { - fn default() -> Dcntr { - Dcntr(0) - } - } - #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idmabsizer(pub u32); - impl Idmabsizer { - #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn idmabndt(&self) -> u8 { - let val = (self.0 >> 5usize) & 0xff; - val as u8 - } - #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_idmabndt(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 5usize)) | (((val as u32) & 0xff) << 5usize); - } - } - impl Default for Idmabsizer { - fn default() -> Idmabsizer { - Idmabsizer(0) - } - } - #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Maskr(pub u32); - impl Maskr { - #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."] - pub const fn ccrcfailie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."] - pub fn set_ccrcfailie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."] - pub const fn dcrcfailie(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."] - pub fn set_dcrcfailie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."] - pub const fn ctimeoutie(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."] - pub fn set_ctimeoutie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."] - pub const fn dtimeoutie(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."] - pub fn set_dtimeoutie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."] - pub const fn txunderrie(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."] - pub fn set_txunderrie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."] - pub const fn rxoverrie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."] - pub fn set_rxoverrie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."] - pub const fn cmdrendie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."] - pub fn set_cmdrendie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."] - pub const fn cmdsentie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."] - pub fn set_cmdsentie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."] - pub const fn dataendie(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."] - pub fn set_dataendie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."] - pub const fn dholdie(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."] - pub fn set_dholdie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."] - pub const fn dbckendie(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."] - pub fn set_dbckendie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."] - pub const fn dabortie(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."] - pub fn set_dabortie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."] - pub const fn txfifoheie(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."] - pub fn set_txfifoheie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."] - pub const fn rxfifohfie(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."] - pub fn set_rxfifohfie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } - #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."] - pub const fn rxfifofie(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."] - pub fn set_rxfifofie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."] - pub const fn txfifoeie(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."] - pub fn set_txfifoeie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."] - pub const fn busyd0endie(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."] - pub fn set_busyd0endie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."] - pub const fn sdioitie(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."] - pub fn set_sdioitie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."] - pub const fn ackfailie(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."] - pub fn set_ackfailie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."] - pub const fn acktimeoutie(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."] - pub fn set_acktimeoutie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."] - pub const fn vswendie(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."] - pub fn set_vswendie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."] - pub const fn ckstopie(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."] - pub fn set_ckstopie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."] - pub const fn idmabtcie(&self) -> bool { - let val = (self.0 >> 28usize) & 0x01; - val != 0 - } - #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."] - pub fn set_idmabtcie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); - } - } - impl Default for Maskr { - fn default() -> Maskr { - Maskr(0) - } - } - #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idmabase1r(pub u32); - impl Idmabase1r { - #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] -are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] - pub const fn idmabase1(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] -are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] - pub fn set_idmabase1(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Idmabase1r { - fn default() -> Idmabase1r { - Idmabase1r(0) - } - } - #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Icr(pub u32); - impl Icr { - #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] - pub const fn ccrcfailc(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] - pub fn set_ccrcfailc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] - pub const fn dcrcfailc(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] - pub fn set_dcrcfailc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] - pub const fn ctimeoutc(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] - pub fn set_ctimeoutc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] - pub const fn dtimeoutc(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] - pub fn set_dtimeoutc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] - pub const fn txunderrc(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] - pub fn set_txunderrc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] - pub const fn rxoverrc(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] - pub fn set_rxoverrc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] - pub const fn cmdrendc(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] - pub fn set_cmdrendc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] - pub const fn cmdsentc(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] - pub fn set_cmdsentc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] - pub const fn dataendc(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] - pub fn set_dataendc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] - pub const fn dholdc(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] - pub fn set_dholdc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] - pub const fn dbckendc(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] - pub fn set_dbckendc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] - pub const fn dabortc(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] - pub fn set_dabortc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] - pub const fn busyd0endc(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] - pub fn set_busyd0endc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] - pub const fn sdioitc(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] - pub fn set_sdioitc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] - pub const fn ackfailc(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] - pub fn set_ackfailc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] - pub const fn acktimeoutc(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] - pub fn set_acktimeoutc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] - pub const fn vswendc(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] - pub fn set_vswendc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] - pub const fn ckstopc(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] - pub fn set_ckstopc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] - pub const fn idmatec(&self) -> bool { - let val = (self.0 >> 27usize) & 0x01; - val != 0 - } - #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] - pub fn set_idmatec(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); - } - #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] - pub const fn idmabtcc(&self) -> bool { - let val = (self.0 >> 28usize) & 0x01; - val != 0 - } - #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] - pub fn set_idmabtcc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); - } - } - impl Default for Icr { - fn default() -> Icr { - Icr(0) - } - } #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -6853,434 +5878,433 @@ are always 0 and read only). This register can be written by firmware when DPSM Star(0) } } - #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Resp1r(pub u32); - impl Resp1r { - #[doc = "see Table 432"] - pub const fn cardstatus1(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "see Table 432"] - pub fn set_cardstatus1(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Resp1r { - fn default() -> Resp1r { - Resp1r(0) - } - } - #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dlenr(pub u32); - impl Dlenr { - #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."] - pub const fn datalength(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x01ff_ffff; - val as u32 - } - #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."] - pub fn set_datalength(&mut self, val: u32) { - self.0 = - (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); - } - } - impl Default for Dlenr { - fn default() -> Dlenr { - Dlenr(0) - } - } - #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Argr(pub u32); - impl Argr { - #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] - pub const fn cmdarg(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] - pub fn set_cmdarg(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Argr { - fn default() -> Argr { - Argr(0) - } - } - #[doc = "SDMMC IP version register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ver(pub u32); - impl Ver { - #[doc = "IP minor revision number."] - pub const fn minrev(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "IP minor revision number."] - pub fn set_minrev(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "IP major revision number."] - pub const fn majrev(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 - } - #[doc = "IP major revision number."] - pub fn set_majrev(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); - } - } - impl Default for Ver { - fn default() -> Ver { - Ver(0) - } - } - #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Resp3r(pub u32); - impl Resp3r { - #[doc = "see Table404."] - pub const fn cardstatus3(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "see Table404."] - pub fn set_cardstatus3(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Resp3r { - fn default() -> Resp3r { - Resp3r(0) - } - } - #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Fifor(pub u32); - impl Fifor { - #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] - pub const fn fifodata(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] - pub fn set_fifodata(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Fifor { - fn default() -> Fifor { - Fifor(0) - } - } - #[doc = "SDMMC power control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Power(pub u32); - impl Power { - #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."] - pub const fn pwrctrl(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x03; - val as u8 - } - #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."] - pub fn set_pwrctrl(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); - } - #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"] - pub const fn vswitch(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"] - pub fn set_vswitch(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"] - pub const fn vswitchen(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"] - pub fn set_vswitchen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."] - pub const fn dirpol(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."] - pub fn set_dirpol(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - } - impl Default for Power { - fn default() -> Power { - Power(0) - } - } - #[doc = "SDMMC IP identification register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Id(pub u32); - impl Id { - #[doc = "SDMMC IP identification."] - pub const fn ip_id(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "SDMMC IP identification."] - pub fn set_ip_id(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Id { - fn default() -> Id { - Id(0) - } - } - #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idmabase0r(pub u32); - impl Idmabase0r { - #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] -are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."] - pub const fn idmabase0(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] -are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."] - pub fn set_idmabase0(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Idmabase0r { - fn default() -> Idmabase0r { - Idmabase0r(0) - } - } - #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Acktimer(pub u32); - impl Acktimer { - #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] - pub const fn acktime(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x01ff_ffff; - val as u32 - } - #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] - pub fn set_acktime(&mut self, val: u32) { - self.0 = - (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); - } - } - impl Default for Acktimer { - fn default() -> Acktimer { - Acktimer(0) - } - } - #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Clkcr(pub u32); - impl Clkcr { - #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] - pub const fn clkdiv(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x03ff; - val as u16 - } - #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] - pub fn set_clkdiv(&mut self, val: u16) { - self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize); - } - #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] - pub const fn pwrsav(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] - pub fn set_pwrsav(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub const fn widbus(&self) -> u8 { - let val = (self.0 >> 14usize) & 0x03; - val as u8 - } - #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub fn set_widbus(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize); - } - #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] - pub const fn negedge(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] - pub fn set_negedge(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] - pub const fn hwfc_en(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] - pub fn set_hwfc_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] - pub const fn ddr(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] - pub fn set_ddr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub const fn busspeed(&self) -> bool { - let val = (self.0 >> 19usize) & 0x01; - val != 0 - } - #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub fn set_busspeed(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); - } - #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub const fn selclkrx(&self) -> u8 { - let val = (self.0 >> 20usize) & 0x03; - val as u8 - } - #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub fn set_selclkrx(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize); - } - } - impl Default for Clkcr { - fn default() -> Clkcr { - Clkcr(0) - } - } - #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dctrl(pub u32); - impl Dctrl { - #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."] - pub const fn dten(&self) -> bool { + pub struct Icr(pub u32); + impl Icr { + #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] + pub const fn ccrcfailc(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."] - pub fn set_dten(&mut self, val: bool) { + #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] + pub fn set_ccrcfailc(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn dtdir(&self) -> bool { + #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] + pub const fn dcrcfailc(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_dtdir(&mut self, val: bool) { + #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] + pub fn set_dcrcfailc(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn dtmode(&self) -> u8 { - let val = (self.0 >> 2usize) & 0x03; - val as u8 + #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] + pub const fn ctimeoutc(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 } - #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_dtmode(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize); + #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] + pub fn set_ctimeoutc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"] - pub const fn dblocksize(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 + #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] + pub const fn dtimeoutc(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 } - #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"] - pub fn set_dblocksize(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] + pub fn set_dtimeoutc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Read wait start. If this bit is set, read wait operation starts."] - pub const fn rwstart(&self) -> bool { + #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] + pub const fn txunderrc(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] + pub fn set_txunderrc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] + pub const fn rxoverrc(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] + pub fn set_rxoverrc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] + pub const fn cmdrendc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] + pub fn set_cmdrendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] + pub const fn cmdsentc(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] + pub fn set_cmdsentc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] + pub const fn dataendc(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "Read wait start. If this bit is set, read wait operation starts."] - pub fn set_rwstart(&mut self, val: bool) { + #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] + pub fn set_dataendc(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } - #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."] - pub const fn rwstop(&self) -> bool { + #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] + pub const fn dholdc(&self) -> bool { let val = (self.0 >> 9usize) & 0x01; val != 0 } - #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."] - pub fn set_rwstop(&mut self, val: bool) { + #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] + pub fn set_dholdc(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); } - #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn rwmod(&self) -> bool { + #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] + pub const fn dbckendc(&self) -> bool { let val = (self.0 >> 10usize) & 0x01; val != 0 } - #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_rwmod(&mut self, val: bool) { + #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] + pub fn set_dbckendc(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); } - #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."] - pub const fn sdioen(&self) -> bool { + #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] + pub const fn dabortc(&self) -> bool { let val = (self.0 >> 11usize) & 0x01; val != 0 } - #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."] - pub fn set_sdioen(&mut self, val: bool) { + #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] + pub fn set_dabortc(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); } - #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn bootacken(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; + #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] + pub const fn busyd0endc(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; val != 0 } - #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_bootacken(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] + pub fn set_busyd0endc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); } - #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."] - pub const fn fiforst(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; + #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] + pub const fn sdioitc(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; val != 0 } - #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."] - pub fn set_fiforst(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] + pub fn set_sdioitc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] + pub const fn ackfailc(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] + pub fn set_ackfailc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] + pub const fn acktimeoutc(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] + pub fn set_acktimeoutc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] + pub const fn vswendc(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] + pub fn set_vswendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] + pub const fn ckstopc(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] + pub fn set_ckstopc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] + pub const fn idmatec(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] + pub fn set_idmatec(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] + pub const fn idmabtcc(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] + pub fn set_idmabtcc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); } } - impl Default for Dctrl { - fn default() -> Dctrl { - Dctrl(0) + impl Default for Icr { + fn default() -> Icr { + Icr(0) + } + } + #[doc = "SDMMC command response register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Respcmdr(pub u32); + impl Respcmdr { + #[doc = "Response command index"] + pub const fn respcmd(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x3f; + val as u8 + } + #[doc = "Response command index"] + pub fn set_respcmd(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); + } + } + impl Default for Respcmdr { + fn default() -> Respcmdr { + Respcmdr(0) + } + } + #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Maskr(pub u32); + impl Maskr { + #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."] + pub const fn ccrcfailie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."] + pub fn set_ccrcfailie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."] + pub const fn dcrcfailie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."] + pub fn set_dcrcfailie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."] + pub const fn ctimeoutie(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."] + pub fn set_ctimeoutie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."] + pub const fn dtimeoutie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."] + pub fn set_dtimeoutie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."] + pub const fn txunderrie(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."] + pub fn set_txunderrie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."] + pub const fn rxoverrie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."] + pub fn set_rxoverrie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."] + pub const fn cmdrendie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."] + pub fn set_cmdrendie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."] + pub const fn cmdsentie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."] + pub fn set_cmdsentie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."] + pub const fn dataendie(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."] + pub fn set_dataendie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."] + pub const fn dholdie(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."] + pub fn set_dholdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."] + pub const fn dbckendie(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."] + pub fn set_dbckendie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."] + pub const fn dabortie(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."] + pub fn set_dabortie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."] + pub const fn txfifoheie(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."] + pub fn set_txfifoheie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."] + pub const fn rxfifohfie(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."] + pub fn set_rxfifohfie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."] + pub const fn rxfifofie(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."] + pub fn set_rxfifofie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."] + pub const fn txfifoeie(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."] + pub fn set_txfifoeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."] + pub const fn busyd0endie(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."] + pub fn set_busyd0endie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."] + pub const fn sdioitie(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."] + pub fn set_sdioitie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."] + pub const fn ackfailie(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."] + pub fn set_ackfailie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."] + pub const fn acktimeoutie(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."] + pub fn set_acktimeoutie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."] + pub const fn vswendie(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."] + pub fn set_vswendie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."] + pub const fn ckstopie(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."] + pub fn set_ckstopie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."] + pub const fn idmabtcie(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."] + pub fn set_idmabtcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + } + impl Default for Maskr { + fn default() -> Maskr { + Maskr(0) } } #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."] @@ -7393,45 +6417,306 @@ are always 0 and read only). This register can be written by firmware when DPSM Cmdr(0) } } - #[doc = "SDMMC command response register"] + #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Respcmdr(pub u32); - impl Respcmdr { - #[doc = "Response command index"] - pub const fn respcmd(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; + pub struct Idmabsizer(pub u32); + impl Idmabsizer { + #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn idmabndt(&self) -> u8 { + let val = (self.0 >> 5usize) & 0xff; val as u8 } - #[doc = "Response command index"] - pub fn set_respcmd(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); + #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_idmabndt(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 5usize)) | (((val as u32) & 0xff) << 5usize); } } - impl Default for Respcmdr { - fn default() -> Respcmdr { - Respcmdr(0) + impl Default for Idmabsizer { + fn default() -> Idmabsizer { + Idmabsizer(0) + } + } + #[doc = "SDMMC power control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Power(pub u32); + impl Power { + #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."] + pub const fn pwrctrl(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x03; + val as u8 + } + #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."] + pub fn set_pwrctrl(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); + } + #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"] + pub const fn vswitch(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"] + pub fn set_vswitch(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"] + pub const fn vswitchen(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"] + pub fn set_vswitchen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."] + pub const fn dirpol(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."] + pub fn set_dirpol(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + } + impl Default for Power { + fn default() -> Power { + Power(0) + } + } + #[doc = "SDMMC IP identification register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Id(pub u32); + impl Id { + #[doc = "SDMMC IP identification."] + pub const fn ip_id(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "SDMMC IP identification."] + pub fn set_ip_id(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Id { + fn default() -> Id { + Id(0) + } + } + #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dtimer(pub u32); + impl Dtimer { + #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] + pub const fn datatime(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] + pub fn set_datatime(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Dtimer { + fn default() -> Dtimer { + Dtimer(0) } } #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Resp4r(pub u32); - impl Resp4r { - #[doc = "see Table404."] - pub const fn cardstatus4(&self) -> u32 { + pub struct Resp1r(pub u32); + impl Resp1r { + #[doc = "see Table 432"] + pub const fn cardstatus1(&self) -> u32 { let val = (self.0 >> 0usize) & 0xffff_ffff; val as u32 } - #[doc = "see Table404."] - pub fn set_cardstatus4(&mut self, val: u32) { + #[doc = "see Table 432"] + pub fn set_cardstatus1(&mut self, val: u32) { self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); } } - impl Default for Resp4r { - fn default() -> Resp4r { - Resp4r(0) + impl Default for Resp1r { + fn default() -> Resp1r { + Resp1r(0) + } + } + #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dctrl(pub u32); + impl Dctrl { + #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."] + pub const fn dten(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."] + pub fn set_dten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn dtdir(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_dtdir(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn dtmode(&self) -> u8 { + let val = (self.0 >> 2usize) & 0x03; + val as u8 + } + #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_dtmode(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize); + } + #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"] + pub const fn dblocksize(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"] + pub fn set_dblocksize(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + #[doc = "Read wait start. If this bit is set, read wait operation starts."] + pub const fn rwstart(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Read wait start. If this bit is set, read wait operation starts."] + pub fn set_rwstart(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."] + pub const fn rwstop(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."] + pub fn set_rwstop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn rwmod(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_rwmod(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."] + pub const fn sdioen(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."] + pub fn set_sdioen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn bootacken(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_bootacken(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."] + pub const fn fiforst(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."] + pub fn set_fiforst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + } + impl Default for Dctrl { + fn default() -> Dctrl { + Dctrl(0) + } + } + #[doc = "SDMMC IP version register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ver(pub u32); + impl Ver { + #[doc = "IP minor revision number."] + pub const fn minrev(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "IP minor revision number."] + pub fn set_minrev(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "IP major revision number."] + pub const fn majrev(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "IP major revision number."] + pub fn set_majrev(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + } + impl Default for Ver { + fn default() -> Ver { + Ver(0) + } + } + #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dcntr(pub u32); + impl Dcntr { + #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] + pub const fn datacount(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x01ff_ffff; + val as u32 + } + #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] + pub fn set_datacount(&mut self, val: u32) { + self.0 = + (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); + } + } + impl Default for Dcntr { + fn default() -> Dcntr { + Dcntr(0) + } + } + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Resp3r(pub u32); + impl Resp3r { + #[doc = "see Table404."] + pub const fn cardstatus3(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "see Table404."] + pub fn set_cardstatus3(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Resp3r { + fn default() -> Resp3r { + Resp3r(0) } } #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] @@ -7455,6 +6740,48 @@ are always 0 and read only). This register can be written by firmware when DPSM Resp2r(0) } } + #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Acktimer(pub u32); + impl Acktimer { + #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] + pub const fn acktime(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x01ff_ffff; + val as u32 + } + #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] + pub fn set_acktime(&mut self, val: u32) { + self.0 = + (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); + } + } + impl Default for Acktimer { + fn default() -> Acktimer { + Acktimer(0) + } + } + #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dlenr(pub u32); + impl Dlenr { + #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."] + pub const fn datalength(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x01ff_ffff; + val as u32 + } + #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."] + pub fn set_datalength(&mut self, val: u32) { + self.0 = + (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); + } + } + impl Default for Dlenr { + fn default() -> Dlenr { + Dlenr(0) + } + } #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -7493,828 +6820,484 @@ are always 0 and read only). This register can be written by firmware when DPSM Idmactrlr(0) } } - #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."] + #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dtimer(pub u32); - impl Dtimer { - #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] - pub const fn datatime(&self) -> u32 { + pub struct Argr(pub u32); + impl Argr { + #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] + pub const fn cmdarg(&self) -> u32 { let val = (self.0 >> 0usize) & 0xffff_ffff; val as u32 } - #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] - pub fn set_datatime(&mut self, val: u32) { + #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] + pub fn set_cmdarg(&mut self, val: u32) { self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); } } - impl Default for Dtimer { - fn default() -> Dtimer { - Dtimer(0) + impl Default for Argr { + fn default() -> Argr { + Argr(0) + } + } + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Resp4r(pub u32); + impl Resp4r { + #[doc = "see Table404."] + pub const fn cardstatus4(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "see Table404."] + pub fn set_cardstatus4(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Resp4r { + fn default() -> Resp4r { + Resp4r(0) + } + } + #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idmabase1r(pub u32); + impl Idmabase1r { + #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] + pub const fn idmabase1(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] + pub fn set_idmabase1(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Idmabase1r { + fn default() -> Idmabase1r { + Idmabase1r(0) + } + } + #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Fifor(pub u32); + impl Fifor { + #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] + pub const fn fifodata(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] + pub fn set_fifodata(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Fifor { + fn default() -> Fifor { + Fifor(0) + } + } + #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idmabase0r(pub u32); + impl Idmabase0r { + #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."] + pub const fn idmabase0(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."] + pub fn set_idmabase0(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Idmabase0r { + fn default() -> Idmabase0r { + Idmabase0r(0) + } + } + #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Clkcr(pub u32); + impl Clkcr { + #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] + pub const fn clkdiv(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x03ff; + val as u16 + } + #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] + pub fn set_clkdiv(&mut self, val: u16) { + self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize); + } + #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] + pub const fn pwrsav(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] + pub fn set_pwrsav(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub const fn widbus(&self) -> u8 { + let val = (self.0 >> 14usize) & 0x03; + val as u8 + } + #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub fn set_widbus(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize); + } + #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] + pub const fn negedge(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] + pub fn set_negedge(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] + pub const fn hwfc_en(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] + pub fn set_hwfc_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] + pub const fn ddr(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] + pub fn set_ddr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub const fn busspeed(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub fn set_busspeed(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub const fn selclkrx(&self) -> u8 { + let val = (self.0 >> 20usize) & 0x03; + val as u8 + } + #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub fn set_selclkrx(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize); + } + } + impl Default for Clkcr { + fn default() -> Clkcr { + Clkcr(0) } } } } -pub mod usart_v1 { +pub mod gpio_v2 { use crate::generic::*; - #[doc = "Universal asynchronous receiver transmitter"] + #[doc = "General-purpose I/Os"] #[derive(Copy, Clone)] - pub struct Uart(pub *mut u8); - unsafe impl Send for Uart {} - unsafe impl Sync for Uart {} - impl Uart { - #[doc = "Status register"] - pub fn sr(self) -> Reg { + pub struct Gpio(pub *mut u8); + unsafe impl Send for Gpio {} + unsafe impl Sync for Gpio {} + impl Gpio { + #[doc = "GPIO port mode register"] + pub fn moder(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(0usize)) } } - #[doc = "Data register"] - pub fn dr(self) -> Reg { + #[doc = "GPIO port output type register"] + pub fn otyper(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(4usize)) } } - #[doc = "Baud rate register"] - pub fn brr(self) -> Reg { + #[doc = "GPIO port output speed register"] + pub fn ospeedr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(8usize)) } } - #[doc = "Control register 1"] - pub fn cr1(self) -> Reg { + #[doc = "GPIO port pull-up/pull-down register"] + pub fn pupdr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(12usize)) } } - #[doc = "Control register 2"] - pub fn cr2(self) -> Reg { + #[doc = "GPIO port input data register"] + pub fn idr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(16usize)) } } - #[doc = "Control register 3"] - pub fn cr3(self) -> Reg { + #[doc = "GPIO port output data register"] + pub fn odr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(20usize)) } } - } - #[doc = "Universal synchronous asynchronous receiver transmitter"] - #[derive(Copy, Clone)] - pub struct Usart(pub *mut u8); - unsafe impl Send for Usart {} - unsafe impl Sync for Usart {} - impl Usart { - #[doc = "Status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "Data register"] - pub fn dr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "Baud rate register"] - pub fn brr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "Control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "Control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "Control register 3"] - pub fn cr3(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "Guard time and prescaler register"] - pub fn gtpr(self) -> Reg { + #[doc = "GPIO port bit set/reset register"] + pub fn bsrr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(24usize)) } } + #[doc = "GPIO port configuration lock register"] + pub fn lckr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(28usize)) } + } + #[doc = "GPIO alternate function register (low, high)"] + pub fn afr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(32usize + n * 4usize)) } + } } pub mod regs { use crate::generic::*; - #[doc = "Status register"] + #[doc = "GPIO port output type register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Sr(pub u32); - impl Sr { - #[doc = "Parity error"] - pub const fn pe(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 + pub struct Otyper(pub u32); + impl Otyper { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn ot(&self, n: usize) -> super::vals::Ot { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Ot(val as u8) } - #[doc = "Parity error"] - pub fn set_pe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Framing error"] - pub const fn fe(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Framing error"] - pub fn set_fe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Noise error flag"] - pub const fn ne(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Noise error flag"] - pub fn set_ne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Overrun error"] - pub const fn ore(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Overrun error"] - pub fn set_ore(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "IDLE line detected"] - pub const fn idle(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "IDLE line detected"] - pub fn set_idle(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Read data register not empty"] - pub const fn rxne(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Read data register not empty"] - pub fn set_rxne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Transmission complete"] - pub const fn tc(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Transmission complete"] - pub fn set_tc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Transmit data register empty"] - pub const fn txe(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Transmit data register empty"] - pub fn set_txe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "LIN break detection flag"] - pub const fn lbd(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "LIN break detection flag"] - pub fn set_lbd(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_ot(&mut self, n: usize, val: super::vals::Ot) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); } } - impl Default for Sr { - fn default() -> Sr { - Sr(0) + impl Default for Otyper { + fn default() -> Otyper { + Otyper(0) } } - #[doc = "Control register 3"] + #[doc = "GPIO port pull-up/pull-down register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr3Usart(pub u32); - impl Cr3Usart { - #[doc = "Error interrupt enable"] - pub const fn eie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 + pub struct Pupdr(pub u32); + impl Pupdr { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn pupdr(&self, n: usize) -> super::vals::Pupdr { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Pupdr(val as u8) } - #[doc = "Error interrupt enable"] - pub fn set_eie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "IrDA mode enable"] - pub const fn iren(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "IrDA mode enable"] - pub fn set_iren(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "IrDA low-power"] - pub const fn irlp(&self) -> super::vals::Irlp { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Irlp(val as u8) - } - #[doc = "IrDA low-power"] - pub fn set_irlp(&mut self, val: super::vals::Irlp) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "Half-duplex selection"] - pub const fn hdsel(&self) -> super::vals::Hdsel { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Hdsel(val as u8) - } - #[doc = "Half-duplex selection"] - pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Smartcard NACK enable"] - pub const fn nack(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "Smartcard NACK enable"] - pub fn set_nack(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Smartcard mode enable"] - pub const fn scen(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Smartcard mode enable"] - pub fn set_scen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "DMA enable receiver"] - pub const fn dmar(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "DMA enable receiver"] - pub fn set_dmar(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "DMA enable transmitter"] - pub const fn dmat(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "DMA enable transmitter"] - pub fn set_dmat(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "RTS enable"] - pub const fn rtse(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "RTS enable"] - pub fn set_rtse(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "CTS enable"] - pub const fn ctse(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "CTS enable"] - pub fn set_ctse(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "CTS interrupt enable"] - pub const fn ctsie(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "CTS interrupt enable"] - pub fn set_ctsie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_pupdr(&mut self, n: usize, val: super::vals::Pupdr) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); } } - impl Default for Cr3Usart { - fn default() -> Cr3Usart { - Cr3Usart(0) + impl Default for Pupdr { + fn default() -> Pupdr { + Pupdr(0) } } - #[doc = "Control register 1"] + #[doc = "GPIO port output speed register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1(pub u32); - impl Cr1 { - #[doc = "Send break"] - pub const fn sbk(&self) -> super::vals::Sbk { - let val = (self.0 >> 0usize) & 0x01; - super::vals::Sbk(val as u8) + pub struct Ospeedr(pub u32); + impl Ospeedr { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Ospeedr(val as u8) } - #[doc = "Send break"] - pub fn set_sbk(&mut self, val: super::vals::Sbk) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); - } - #[doc = "Receiver wakeup"] - pub const fn rwu(&self) -> super::vals::Rwu { - let val = (self.0 >> 1usize) & 0x01; - super::vals::Rwu(val as u8) - } - #[doc = "Receiver wakeup"] - pub fn set_rwu(&mut self, val: super::vals::Rwu) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); - } - #[doc = "Receiver enable"] - pub const fn re(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Receiver enable"] - pub fn set_re(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Transmitter enable"] - pub const fn te(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Transmitter enable"] - pub fn set_te(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "IDLE interrupt enable"] - pub const fn idleie(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "IDLE interrupt enable"] - pub fn set_idleie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "RXNE interrupt enable"] - pub const fn rxneie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "RXNE interrupt enable"] - pub fn set_rxneie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Transmission complete interrupt enable"] - pub const fn tcie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Transmission complete interrupt enable"] - pub fn set_tcie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "TXE interrupt enable"] - pub const fn txeie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "TXE interrupt enable"] - pub fn set_txeie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "PE interrupt enable"] - pub const fn peie(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "PE interrupt enable"] - pub fn set_peie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Parity selection"] - pub const fn ps(&self) -> super::vals::Ps { - let val = (self.0 >> 9usize) & 0x01; - super::vals::Ps(val as u8) - } - #[doc = "Parity selection"] - pub fn set_ps(&mut self, val: super::vals::Ps) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); - } - #[doc = "Parity control enable"] - pub const fn pce(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "Parity control enable"] - pub fn set_pce(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "Wakeup method"] - pub const fn wake(&self) -> super::vals::Wake { - let val = (self.0 >> 11usize) & 0x01; - super::vals::Wake(val as u8) - } - #[doc = "Wakeup method"] - pub fn set_wake(&mut self, val: super::vals::Wake) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); - } - #[doc = "Word length"] - pub const fn m(&self) -> super::vals::M { - let val = (self.0 >> 12usize) & 0x01; - super::vals::M(val as u8) - } - #[doc = "Word length"] - pub fn set_m(&mut self, val: super::vals::M) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); - } - #[doc = "USART enable"] - pub const fn ue(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "USART enable"] - pub fn set_ue(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); } } - impl Default for Cr1 { - fn default() -> Cr1 { - Cr1(0) + impl Default for Ospeedr { + fn default() -> Ospeedr { + Ospeedr(0) } } - #[doc = "Control register 2"] + #[doc = "GPIO port bit set/reset register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2(pub u32); - impl Cr2 { - #[doc = "Address of the USART node"] - pub const fn add(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Address of the USART node"] - pub fn set_add(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "lin break detection length"] - pub const fn lbdl(&self) -> super::vals::Lbdl { - let val = (self.0 >> 5usize) & 0x01; - super::vals::Lbdl(val as u8) - } - #[doc = "lin break detection length"] - pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); - } - #[doc = "LIN break detection interrupt enable"] - pub const fn lbdie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; + pub struct Bsrr(pub u32); + impl Bsrr { + #[doc = "Port x set bit y (y= 0..15)"] + pub fn bs(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; val != 0 } - #[doc = "LIN break detection interrupt enable"] - pub fn set_lbdie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + #[doc = "Port x set bit y (y= 0..15)"] + pub fn set_bs(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } - #[doc = "STOP bits"] - pub const fn stop(&self) -> super::vals::Stop { - let val = (self.0 >> 12usize) & 0x03; - super::vals::Stop(val as u8) - } - #[doc = "STOP bits"] - pub fn set_stop(&mut self, val: super::vals::Stop) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); - } - #[doc = "LIN mode enable"] - pub const fn linen(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; + #[doc = "Port x set bit y (y= 0..15)"] + pub fn br(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; val != 0 } - #[doc = "LIN mode enable"] - pub fn set_linen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + #[doc = "Port x set bit y (y= 0..15)"] + pub fn set_br(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } } - impl Default for Cr2 { - fn default() -> Cr2 { - Cr2(0) + impl Default for Bsrr { + fn default() -> Bsrr { + Bsrr(0) } } - #[doc = "Control register 2"] + #[doc = "GPIO alternate function register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2Usart(pub u32); - impl Cr2Usart { - #[doc = "Address of the USART node"] - pub const fn add(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 + pub struct Afr(pub u32); + impl Afr { + #[doc = "Alternate function selection for port x bit y (y = 0..15)"] + pub fn afr(&self, n: usize) -> super::vals::Afr { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + super::vals::Afr(val as u8) } - #[doc = "Address of the USART node"] - pub fn set_add(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "lin break detection length"] - pub const fn lbdl(&self) -> super::vals::Lbdl { - let val = (self.0 >> 5usize) & 0x01; - super::vals::Lbdl(val as u8) - } - #[doc = "lin break detection length"] - pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); - } - #[doc = "LIN break detection interrupt enable"] - pub const fn lbdie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "LIN break detection interrupt enable"] - pub fn set_lbdie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Last bit clock pulse"] - pub const fn lbcl(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Last bit clock pulse"] - pub fn set_lbcl(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Clock phase"] - pub const fn cpha(&self) -> super::vals::Cpha { - let val = (self.0 >> 9usize) & 0x01; - super::vals::Cpha(val as u8) - } - #[doc = "Clock phase"] - pub fn set_cpha(&mut self, val: super::vals::Cpha) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); - } - #[doc = "Clock polarity"] - pub const fn cpol(&self) -> super::vals::Cpol { - let val = (self.0 >> 10usize) & 0x01; - super::vals::Cpol(val as u8) - } - #[doc = "Clock polarity"] - pub fn set_cpol(&mut self, val: super::vals::Cpol) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); - } - #[doc = "Clock enable"] - pub const fn clken(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "Clock enable"] - pub fn set_clken(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "STOP bits"] - pub const fn stop(&self) -> super::vals::Stop { - let val = (self.0 >> 12usize) & 0x03; - super::vals::Stop(val as u8) - } - #[doc = "STOP bits"] - pub fn set_stop(&mut self, val: super::vals::Stop) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); - } - #[doc = "LIN mode enable"] - pub const fn linen(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "LIN mode enable"] - pub fn set_linen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + #[doc = "Alternate function selection for port x bit y (y = 0..15)"] + pub fn set_afr(&mut self, n: usize, val: super::vals::Afr) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); } } - impl Default for Cr2Usart { - fn default() -> Cr2Usart { - Cr2Usart(0) + impl Default for Afr { + fn default() -> Afr { + Afr(0) } } - #[doc = "Control register 3"] + #[doc = "GPIO port output data register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr3(pub u32); - impl Cr3 { - #[doc = "Error interrupt enable"] - pub const fn eie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 + pub struct Odr(pub u32); + impl Odr { + #[doc = "Port output data (y = 0..15)"] + pub fn odr(&self, n: usize) -> super::vals::Odr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Odr(val as u8) } - #[doc = "Error interrupt enable"] - pub fn set_eie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "IrDA mode enable"] - pub const fn iren(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "IrDA mode enable"] - pub fn set_iren(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "IrDA low-power"] - pub const fn irlp(&self) -> super::vals::Irlp { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Irlp(val as u8) - } - #[doc = "IrDA low-power"] - pub fn set_irlp(&mut self, val: super::vals::Irlp) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "Half-duplex selection"] - pub const fn hdsel(&self) -> super::vals::Hdsel { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Hdsel(val as u8) - } - #[doc = "Half-duplex selection"] - pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "DMA enable receiver"] - pub const fn dmar(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "DMA enable receiver"] - pub fn set_dmar(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "DMA enable transmitter"] - pub const fn dmat(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "DMA enable transmitter"] - pub fn set_dmat(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + #[doc = "Port output data (y = 0..15)"] + pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); } } - impl Default for Cr3 { - fn default() -> Cr3 { - Cr3(0) + impl Default for Odr { + fn default() -> Odr { + Odr(0) } } - #[doc = "Baud rate register"] + #[doc = "GPIO port mode register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Brr(pub u32); - impl Brr { - #[doc = "fraction of USARTDIV"] - pub const fn div_fraction(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 + pub struct Moder(pub u32); + impl Moder { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn moder(&self, n: usize) -> super::vals::Moder { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Moder(val as u8) } - #[doc = "fraction of USARTDIV"] - pub fn set_div_fraction(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "mantissa of USARTDIV"] - pub const fn div_mantissa(&self) -> u16 { - let val = (self.0 >> 4usize) & 0x0fff; - val as u16 - } - #[doc = "mantissa of USARTDIV"] - pub fn set_div_mantissa(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize); + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); } } - impl Default for Brr { - fn default() -> Brr { - Brr(0) + impl Default for Moder { + fn default() -> Moder { + Moder(0) } } - #[doc = "Data register"] + #[doc = "GPIO port input data register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dr(pub u32); - impl Dr { - #[doc = "Data value"] - pub const fn dr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x01ff; - val as u16 + pub struct Idr(pub u32); + impl Idr { + #[doc = "Port input data (y = 0..15)"] + pub fn idr(&self, n: usize) -> super::vals::Idr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Idr(val as u8) } - #[doc = "Data value"] - pub fn set_dr(&mut self, val: u16) { - self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize); + #[doc = "Port input data (y = 0..15)"] + pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); } } - impl Default for Dr { - fn default() -> Dr { - Dr(0) + impl Default for Idr { + fn default() -> Idr { + Idr(0) } } - #[doc = "Status register"] + #[doc = "GPIO port configuration lock register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct SrUsart(pub u32); - impl SrUsart { - #[doc = "Parity error"] - pub const fn pe(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 + pub struct Lckr(pub u32); + impl Lckr { + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn lck(&self, n: usize) -> super::vals::Lck { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Lck(val as u8) } - #[doc = "Parity error"] - pub fn set_pe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); } - #[doc = "Framing error"] - pub const fn fe(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 + #[doc = "Port x lock bit y (y= 0..15)"] + pub const fn lckk(&self) -> super::vals::Lckk { + let val = (self.0 >> 16usize) & 0x01; + super::vals::Lckk(val as u8) } - #[doc = "Framing error"] - pub fn set_fe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Noise error flag"] - pub const fn ne(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Noise error flag"] - pub fn set_ne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Overrun error"] - pub const fn ore(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Overrun error"] - pub fn set_ore(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "IDLE line detected"] - pub const fn idle(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "IDLE line detected"] - pub fn set_idle(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Read data register not empty"] - pub const fn rxne(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Read data register not empty"] - pub fn set_rxne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Transmission complete"] - pub const fn tc(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Transmission complete"] - pub fn set_tc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Transmit data register empty"] - pub const fn txe(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Transmit data register empty"] - pub fn set_txe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "LIN break detection flag"] - pub const fn lbd(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "LIN break detection flag"] - pub fn set_lbd(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "CTS flag"] - pub const fn cts(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "CTS flag"] - pub fn set_cts(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn set_lckk(&mut self, val: super::vals::Lckk) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); } } - impl Default for SrUsart { - fn default() -> SrUsart { - SrUsart(0) - } - } - #[doc = "Guard time and prescaler register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Gtpr(pub u32); - impl Gtpr { - #[doc = "Prescaler value"] - pub const fn psc(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Prescaler value"] - pub fn set_psc(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - #[doc = "Guard time value"] - pub const fn gt(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Guard time value"] - pub fn set_gt(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - } - impl Default for Gtpr { - fn default() -> Gtpr { - Gtpr(0) + impl Default for Lckr { + fn default() -> Lckr { + Lckr(0) } } } @@ -8322,110 +7305,140 @@ pub mod usart_v1 { use crate::generic::*; #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpol(pub u8); - impl Cpol { - #[doc = "Steady low value on CK pin outside transmission window"] + pub struct Lck(pub u8); + impl Lck { + #[doc = "Port configuration not locked"] + pub const UNLOCKED: Self = Self(0); + #[doc = "Port configuration locked"] + pub const LOCKED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pupdr(pub u8); + impl Pupdr { + #[doc = "No pull-up, pull-down"] + pub const FLOATING: Self = Self(0); + #[doc = "Pull-up"] + pub const PULLUP: Self = Self(0x01); + #[doc = "Pull-down"] + pub const PULLDOWN: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Idr(pub u8); + impl Idr { + #[doc = "Input is logic low"] pub const LOW: Self = Self(0); - #[doc = "Steady high value on CK pin outside transmission window"] + #[doc = "Input is logic high"] pub const HIGH: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lbdl(pub u8); - impl Lbdl { - #[doc = "10-bit break detection"] - pub const LBDL10: Self = Self(0); - #[doc = "11-bit break detection"] - pub const LBDL11: Self = Self(0x01); + pub struct Ot(pub u8); + impl Ot { + #[doc = "Output push-pull (reset state)"] + pub const PUSHPULL: Self = Self(0); + #[doc = "Output open-drain"] + pub const OPENDRAIN: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Wake(pub u8); - impl Wake { - #[doc = "USART wakeup on idle line"] - pub const IDLELINE: Self = Self(0); - #[doc = "USART wakeup on address mark"] - pub const ADDRESSMARK: Self = Self(0x01); + pub struct Ospeedr(pub u8); + impl Ospeedr { + #[doc = "Low speed"] + pub const LOWSPEED: Self = Self(0); + #[doc = "Medium speed"] + pub const MEDIUMSPEED: Self = Self(0x01); + #[doc = "High speed"] + pub const HIGHSPEED: Self = Self(0x02); + #[doc = "Very high speed"] + pub const VERYHIGHSPEED: Self = Self(0x03); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpha(pub u8); - impl Cpha { - #[doc = "The first clock transition is the first data capture edge"] - pub const FIRST: Self = Self(0); - #[doc = "The second clock transition is the first data capture edge"] - pub const SECOND: Self = Self(0x01); + pub struct Bsw(pub u8); + impl Bsw { + #[doc = "Sets the corresponding ODRx bit"] + pub const SET: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Sbk(pub u8); - impl Sbk { - #[doc = "No break character is transmitted"] - pub const NOBREAK: Self = Self(0); - #[doc = "Break character transmitted"] - pub const BREAK: Self = Self(0x01); + pub struct Lckk(pub u8); + impl Lckk { + #[doc = "Port configuration lock key not active"] + pub const NOTACTIVE: Self = Self(0); + #[doc = "Port configuration lock key active"] + pub const ACTIVE: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Rwu(pub u8); - impl Rwu { - #[doc = "Receiver in active mode"] - pub const ACTIVE: Self = Self(0); - #[doc = "Receiver in mute mode"] - pub const MUTE: Self = Self(0x01); + pub struct Moder(pub u8); + impl Moder { + #[doc = "Input mode (reset state)"] + pub const INPUT: Self = Self(0); + #[doc = "General purpose output mode"] + pub const OUTPUT: Self = Self(0x01); + #[doc = "Alternate function mode"] + pub const ALTERNATE: Self = Self(0x02); + #[doc = "Analog mode"] + pub const ANALOG: Self = Self(0x03); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ps(pub u8); - impl Ps { - #[doc = "Even parity"] - pub const EVEN: Self = Self(0); - #[doc = "Odd parity"] - pub const ODD: Self = Self(0x01); + pub struct Brw(pub u8); + impl Brw { + #[doc = "Resets the corresponding ODRx bit"] + pub const RESET: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Irlp(pub u8); - impl Irlp { - #[doc = "Normal mode"] - pub const NORMAL: Self = Self(0); - #[doc = "Low-power mode"] - pub const LOWPOWER: Self = Self(0x01); + pub struct Afr(pub u8); + impl Afr { + #[doc = "AF0"] + pub const AF0: Self = Self(0); + #[doc = "AF1"] + pub const AF1: Self = Self(0x01); + #[doc = "AF2"] + pub const AF2: Self = Self(0x02); + #[doc = "AF3"] + pub const AF3: Self = Self(0x03); + #[doc = "AF4"] + pub const AF4: Self = Self(0x04); + #[doc = "AF5"] + pub const AF5: Self = Self(0x05); + #[doc = "AF6"] + pub const AF6: Self = Self(0x06); + #[doc = "AF7"] + pub const AF7: Self = Self(0x07); + #[doc = "AF8"] + pub const AF8: Self = Self(0x08); + #[doc = "AF9"] + pub const AF9: Self = Self(0x09); + #[doc = "AF10"] + pub const AF10: Self = Self(0x0a); + #[doc = "AF11"] + pub const AF11: Self = Self(0x0b); + #[doc = "AF12"] + pub const AF12: Self = Self(0x0c); + #[doc = "AF13"] + pub const AF13: Self = Self(0x0d); + #[doc = "AF14"] + pub const AF14: Self = Self(0x0e); + #[doc = "AF15"] + pub const AF15: Self = Self(0x0f); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Hdsel(pub u8); - impl Hdsel { - #[doc = "Half duplex mode is not selected"] - pub const FULLDUPLEX: Self = Self(0); - #[doc = "Half duplex mode is selected"] - pub const HALFDUPLEX: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Stop(pub u8); - impl Stop { - #[doc = "1 stop bit"] - pub const STOP1: Self = Self(0); - #[doc = "0.5 stop bits"] - pub const STOP0P5: Self = Self(0x01); - #[doc = "2 stop bits"] - pub const STOP2: Self = Self(0x02); - #[doc = "1.5 stop bits"] - pub const STOP1P5: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct M(pub u8); - impl M { - #[doc = "8 data bits"] - pub const M8: Self = Self(0); - #[doc = "9 data bits"] - pub const M9: Self = Self(0x01); + pub struct Odr(pub u8); + impl Odr { + #[doc = "Set output to logic low"] + pub const LOW: Self = Self(0); + #[doc = "Set output to logic high"] + pub const HIGH: Self = Self(0x01); } } } -pub mod spi_v2 { +pub mod spi_v1 { use crate::generic::*; #[doc = "Serial peripheral interface"] #[derive(Copy, Clone)] @@ -8462,275 +7475,8 @@ pub mod spi_v2 { unsafe { Reg::from_ptr(self.0.add(24usize)) } } } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mstr(pub u8); - impl Mstr { - #[doc = "Slave configuration"] - pub const SLAVE: Self = Self(0); - #[doc = "Master configuration"] - pub const MASTER: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bidimode(pub u8); - impl Bidimode { - #[doc = "2-line unidirectional data mode selected"] - pub const UNIDIRECTIONAL: Self = Self(0); - #[doc = "1-line bidirectional data mode selected"] - pub const BIDIRECTIONAL: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Crcnext(pub u8); - impl Crcnext { - #[doc = "Next transmit value is from Tx buffer"] - pub const TXBUFFER: Self = Self(0); - #[doc = "Next transmit value is from Tx CRC register"] - pub const CRC: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct LdmaRx(pub u8); - impl LdmaRx { - #[doc = "Number of data to transfer for receive is even"] - pub const EVEN: Self = Self(0); - #[doc = "Number of data to transfer for receive is odd"] - pub const ODD: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lsbfirst(pub u8); - impl Lsbfirst { - #[doc = "Data is transmitted/received with the MSB first"] - pub const MSBFIRST: Self = Self(0); - #[doc = "Data is transmitted/received with the LSB first"] - pub const LSBFIRST: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frlvlr(pub u8); - impl Frlvlr { - #[doc = "Rx FIFO Empty"] - pub const EMPTY: Self = Self(0); - #[doc = "Rx 1/4 FIFO"] - pub const QUARTER: Self = Self(0x01); - #[doc = "Rx 1/2 FIFO"] - pub const HALF: Self = Self(0x02); - #[doc = "Rx FIFO full"] - pub const FULL: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ftlvlr(pub u8); - impl Ftlvlr { - #[doc = "Tx FIFO Empty"] - pub const EMPTY: Self = Self(0); - #[doc = "Tx 1/4 FIFO"] - pub const QUARTER: Self = Self(0x01); - #[doc = "Tx 1/2 FIFO"] - pub const HALF: Self = Self(0x02); - #[doc = "Tx FIFO full"] - pub const FULL: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpol(pub u8); - impl Cpol { - #[doc = "CK to 0 when idle"] - pub const IDLELOW: Self = Self(0); - #[doc = "CK to 1 when idle"] - pub const IDLEHIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bidioe(pub u8); - impl Bidioe { - #[doc = "Output disabled (receive-only mode)"] - pub const OUTPUTDISABLED: Self = Self(0); - #[doc = "Output enabled (transmit-only mode)"] - pub const OUTPUTENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frxth(pub u8); - impl Frxth { - #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"] - pub const HALF: Self = Self(0); - #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"] - pub const QUARTER: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Br(pub u8); - impl Br { - #[doc = "f_PCLK / 2"] - pub const DIV2: Self = Self(0); - #[doc = "f_PCLK / 4"] - pub const DIV4: Self = Self(0x01); - #[doc = "f_PCLK / 8"] - pub const DIV8: Self = Self(0x02); - #[doc = "f_PCLK / 16"] - pub const DIV16: Self = Self(0x03); - #[doc = "f_PCLK / 32"] - pub const DIV32: Self = Self(0x04); - #[doc = "f_PCLK / 64"] - pub const DIV64: Self = Self(0x05); - #[doc = "f_PCLK / 128"] - pub const DIV128: Self = Self(0x06); - #[doc = "f_PCLK / 256"] - pub const DIV256: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ds(pub u8); - impl Ds { - #[doc = "4-bit"] - pub const FOURBIT: Self = Self(0x03); - #[doc = "5-bit"] - pub const FIVEBIT: Self = Self(0x04); - #[doc = "6-bit"] - pub const SIXBIT: Self = Self(0x05); - #[doc = "7-bit"] - pub const SEVENBIT: Self = Self(0x06); - #[doc = "8-bit"] - pub const EIGHTBIT: Self = Self(0x07); - #[doc = "9-bit"] - pub const NINEBIT: Self = Self(0x08); - #[doc = "10-bit"] - pub const TENBIT: Self = Self(0x09); - #[doc = "11-bit"] - pub const ELEVENBIT: Self = Self(0x0a); - #[doc = "12-bit"] - pub const TWELVEBIT: Self = Self(0x0b); - #[doc = "13-bit"] - pub const THIRTEENBIT: Self = Self(0x0c); - #[doc = "14-bit"] - pub const FOURTEENBIT: Self = Self(0x0d); - #[doc = "15-bit"] - pub const FIFTEENBIT: Self = Self(0x0e); - #[doc = "16-bit"] - pub const SIXTEENBIT: Self = Self(0x0f); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Rxonly(pub u8); - impl Rxonly { - #[doc = "Full duplex (Transmit and receive)"] - pub const FULLDUPLEX: Self = Self(0); - #[doc = "Output disabled (Receive-only mode)"] - pub const OUTPUTDISABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Crcl(pub u8); - impl Crcl { - #[doc = "8-bit CRC length"] - pub const EIGHTBIT: Self = Self(0); - #[doc = "16-bit CRC length"] - pub const SIXTEENBIT: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpha(pub u8); - impl Cpha { - #[doc = "The first clock transition is the first data capture edge"] - pub const FIRSTEDGE: Self = Self(0); - #[doc = "The second clock transition is the first data capture edge"] - pub const SECONDEDGE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct LdmaTx(pub u8); - impl LdmaTx { - #[doc = "Number of data to transfer for transmit is even"] - pub const EVEN: Self = Self(0); - #[doc = "Number of data to transfer for transmit is odd"] - pub const ODD: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frf(pub u8); - impl Frf { - #[doc = "SPI Motorola mode"] - pub const MOTOROLA: Self = Self(0); - #[doc = "SPI TI mode"] - pub const TI: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frer(pub u8); - impl Frer { - #[doc = "No frame format error"] - pub const NOERROR: Self = Self(0); - #[doc = "A frame format error occurred"] - pub const ERROR: Self = Self(0x01); - } - } pub mod regs { use crate::generic::*; - #[doc = "data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dr(pub u32); - impl Dr { - #[doc = "Data register"] - pub const fn dr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Data register"] - pub fn set_dr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Dr { - fn default() -> Dr { - Dr(0) - } - } - #[doc = "CRC polynomial register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Crcpr(pub u32); - impl Crcpr { - #[doc = "CRC polynomial register"] - pub const fn crcpoly(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "CRC polynomial register"] - pub fn set_crcpoly(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Crcpr { - fn default() -> Crcpr { - Crcpr(0) - } - } - #[doc = "RX CRC register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Rxcrcr(pub u32); - impl Rxcrcr { - #[doc = "Rx CRC register"] - pub const fn rx_crc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Rx CRC register"] - pub fn set_rx_crc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Rxcrcr { - fn default() -> Rxcrcr { - Rxcrcr(0) - } - } #[doc = "TX CRC register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -8810,39 +7556,81 @@ pub mod spi_v2 { pub fn set_bsy(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - #[doc = "Frame format error"] + #[doc = "TI frame format error"] pub const fn fre(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "Frame format error"] + #[doc = "TI frame format error"] pub fn set_fre(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } - #[doc = "FIFO reception level"] - pub const fn frlvl(&self) -> u8 { - let val = (self.0 >> 9usize) & 0x03; - val as u8 - } - #[doc = "FIFO reception level"] - pub fn set_frlvl(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 9usize)) | (((val as u32) & 0x03) << 9usize); - } - #[doc = "FIFO Transmission Level"] - pub const fn ftlvl(&self) -> u8 { - let val = (self.0 >> 11usize) & 0x03; - val as u8 - } - #[doc = "FIFO Transmission Level"] - pub fn set_ftlvl(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 11usize)) | (((val as u32) & 0x03) << 11usize); - } } impl Default for Sr { fn default() -> Sr { Sr(0) } } + #[doc = "CRC polynomial register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Crcpr(pub u32); + impl Crcpr { + #[doc = "CRC polynomial register"] + pub const fn crcpoly(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "CRC polynomial register"] + pub fn set_crcpoly(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Crcpr { + fn default() -> Crcpr { + Crcpr(0) + } + } + #[doc = "RX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rxcrcr(pub u32); + impl Rxcrcr { + #[doc = "Rx CRC register"] + pub const fn rx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Rx CRC register"] + pub fn set_rx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Rxcrcr { + fn default() -> Rxcrcr { + Rxcrcr(0) + } + } + #[doc = "data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dr(pub u32); + impl Dr { + #[doc = "Data register"] + pub const fn dr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Data register"] + pub fn set_dr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Dr { + fn default() -> Dr { + Dr(0) + } + } #[doc = "control register 1"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -8929,13 +7717,13 @@ pub mod spi_v2 { pub fn set_rxonly(&mut self, val: super::vals::Rxonly) { self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); } - #[doc = "CRC length"] - pub const fn crcl(&self) -> super::vals::Crcl { + #[doc = "Data frame format"] + pub const fn dff(&self) -> super::vals::Dff { let val = (self.0 >> 11usize) & 0x01; - super::vals::Crcl(val as u8) + super::vals::Dff(val as u8) } - #[doc = "CRC length"] - pub fn set_crcl(&mut self, val: super::vals::Crcl) { + #[doc = "Data frame format"] + pub fn set_dff(&mut self, val: super::vals::Dff) { self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); } #[doc = "CRC transfer next"] @@ -9012,15 +7800,6 @@ pub mod spi_v2 { pub fn set_ssoe(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "NSS pulse management"] - pub const fn nssp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "NSS pulse management"] - pub fn set_nssp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } #[doc = "Frame format"] pub const fn frf(&self) -> super::vals::Frf { let val = (self.0 >> 4usize) & 0x01; @@ -9057,42 +7836,6 @@ pub mod spi_v2 { pub fn set_txeie(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - #[doc = "Data size"] - pub const fn ds(&self) -> super::vals::Ds { - let val = (self.0 >> 8usize) & 0x0f; - super::vals::Ds(val as u8) - } - #[doc = "Data size"] - pub fn set_ds(&mut self, val: super::vals::Ds) { - self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); - } - #[doc = "FIFO reception threshold"] - pub const fn frxth(&self) -> super::vals::Frxth { - let val = (self.0 >> 12usize) & 0x01; - super::vals::Frxth(val as u8) - } - #[doc = "FIFO reception threshold"] - pub fn set_frxth(&mut self, val: super::vals::Frxth) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); - } - #[doc = "Last DMA transfer for reception"] - pub const fn ldma_rx(&self) -> super::vals::LdmaRx { - let val = (self.0 >> 13usize) & 0x01; - super::vals::LdmaRx(val as u8) - } - #[doc = "Last DMA transfer for reception"] - pub fn set_ldma_rx(&mut self, val: super::vals::LdmaRx) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val.0 as u32) & 0x01) << 13usize); - } - #[doc = "Last DMA transfer for transmission"] - pub const fn ldma_tx(&self) -> super::vals::LdmaTx { - let val = (self.0 >> 14usize) & 0x01; - super::vals::LdmaTx(val as u8) - } - #[doc = "Last DMA transfer for transmission"] - pub fn set_ldma_tx(&mut self, val: super::vals::LdmaTx) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); - } } impl Default for Cr2 { fn default() -> Cr2 { @@ -9100,4 +7843,1261 @@ pub mod spi_v2 { } } } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Crcnext(pub u8); + impl Crcnext { + #[doc = "Next transmit value is from Tx buffer"] + pub const TXBUFFER: Self = Self(0); + #[doc = "Next transmit value is from Tx CRC register"] + pub const CRC: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRSTEDGE: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECONDEDGE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Iscfg(pub u8); + impl Iscfg { + #[doc = "Slave - transmit"] + pub const SLAVETX: Self = Self(0); + #[doc = "Slave - receive"] + pub const SLAVERX: Self = Self(0x01); + #[doc = "Master - transmit"] + pub const MASTERTX: Self = Self(0x02); + #[doc = "Master - receive"] + pub const MASTERRX: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Br(pub u8); + impl Br { + #[doc = "f_PCLK / 2"] + pub const DIV2: Self = Self(0); + #[doc = "f_PCLK / 4"] + pub const DIV4: Self = Self(0x01); + #[doc = "f_PCLK / 8"] + pub const DIV8: Self = Self(0x02); + #[doc = "f_PCLK / 16"] + pub const DIV16: Self = Self(0x03); + #[doc = "f_PCLK / 32"] + pub const DIV32: Self = Self(0x04); + #[doc = "f_PCLK / 64"] + pub const DIV64: Self = Self(0x05); + #[doc = "f_PCLK / 128"] + pub const DIV128: Self = Self(0x06); + #[doc = "f_PCLK / 256"] + pub const DIV256: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidimode(pub u8); + impl Bidimode { + #[doc = "2-line unidirectional data mode selected"] + pub const UNIDIRECTIONAL: Self = Self(0); + #[doc = "1-line bidirectional data mode selected"] + pub const BIDIRECTIONAL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rxonly(pub u8); + impl Rxonly { + #[doc = "Full duplex (Transmit and receive)"] + pub const FULLDUPLEX: Self = Self(0); + #[doc = "Output disabled (Receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpol(pub u8); + impl Cpol { + #[doc = "CK to 0 when idle"] + pub const IDLELOW: Self = Self(0); + #[doc = "CK to 1 when idle"] + pub const IDLEHIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lsbfirst(pub u8); + impl Lsbfirst { + #[doc = "Data is transmitted/received with the MSB first"] + pub const MSBFIRST: Self = Self(0); + #[doc = "Data is transmitted/received with the LSB first"] + pub const LSBFIRST: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dff(pub u8); + impl Dff { + #[doc = "8-bit data frame format is selected for transmission/reception"] + pub const EIGHTBIT: Self = Self(0); + #[doc = "16-bit data frame format is selected for transmission/reception"] + pub const SIXTEENBIT: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidioe(pub u8); + impl Bidioe { + #[doc = "Output disabled (receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0); + #[doc = "Output enabled (transmit-only mode)"] + pub const OUTPUTENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frer(pub u8); + impl Frer { + #[doc = "No frame format error"] + pub const NOERROR: Self = Self(0); + #[doc = "A frame format error occurred"] + pub const ERROR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mstr(pub u8); + impl Mstr { + #[doc = "Slave configuration"] + pub const SLAVE: Self = Self(0); + #[doc = "Master configuration"] + pub const MASTER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frf(pub u8); + impl Frf { + #[doc = "SPI Motorola mode"] + pub const MOTOROLA: Self = Self(0); + #[doc = "SPI TI mode"] + pub const TI: Self = Self(0x01); + } + } +} +pub mod dma_v1 { + use crate::generic::*; + #[doc = "DMA controller"] + #[derive(Copy, Clone)] + pub struct Dma(pub *mut u8); + unsafe impl Send for Dma {} + unsafe impl Sync for Dma {} + impl Dma { + #[doc = "DMA interrupt status register (DMA_ISR)"] + pub fn isr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] + pub fn ifcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] + pub fn ch(self, n: usize) -> Ch { + assert!(n < 7usize); + unsafe { Ch(self.0.add(8usize + n * 20usize)) } + } + } + #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] + #[derive(Copy, Clone)] + pub struct Ch(pub *mut u8); + unsafe impl Send for Ch {} + unsafe impl Sync for Ch {} + impl Ch { + #[doc = "DMA channel configuration register (DMA_CCR)"] + pub fn cr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "DMA channel 1 number of data register"] + pub fn ndtr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "DMA channel 1 peripheral address register"] + pub fn par(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA channel 1 memory address register"] + pub fn mar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ifcr(pub u32); + impl Ifcr { + #[doc = "Channel 1 Global interrupt clear"] + pub fn cgif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Global interrupt clear"] + pub fn set_cgif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Complete clear"] + pub fn ctcif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Complete clear"] + pub fn set_ctcif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Half Transfer clear"] + pub fn chtif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Half Transfer clear"] + pub fn set_chtif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Error clear"] + pub fn cteif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Error clear"] + pub fn set_cteif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Ifcr { + fn default() -> Ifcr { + Ifcr(0) + } + } + #[doc = "DMA interrupt status register (DMA_ISR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Isr(pub u32); + impl Isr { + #[doc = "Channel 1 Global interrupt flag"] + pub fn gif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Global interrupt flag"] + pub fn set_gif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Complete flag"] + pub fn tcif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Complete flag"] + pub fn set_tcif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Half Transfer Complete flag"] + pub fn htif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Half Transfer Complete flag"] + pub fn set_htif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Error flag"] + pub fn teif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Error flag"] + pub fn set_teif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Isr { + fn default() -> Isr { + Isr(0) + } + } + #[doc = "DMA channel configuration register (DMA_CCR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Channel enable"] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Channel enable"] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Transfer complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Transfer complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Half Transfer interrupt enable"] + pub const fn htie(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Half Transfer interrupt enable"] + pub fn set_htie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Transfer error interrupt enable"] + pub const fn teie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Transfer error interrupt enable"] + pub fn set_teie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Data transfer direction"] + pub const fn dir(&self) -> super::vals::Dir { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Dir(val as u8) + } + #[doc = "Data transfer direction"] + pub fn set_dir(&mut self, val: super::vals::Dir) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Circular mode"] + pub const fn circ(&self) -> super::vals::Circ { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Circ(val as u8) + } + #[doc = "Circular mode"] + pub fn set_circ(&mut self, val: super::vals::Circ) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "Peripheral increment mode"] + pub const fn pinc(&self) -> super::vals::Inc { + let val = (self.0 >> 6usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Peripheral increment mode"] + pub fn set_pinc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize); + } + #[doc = "Memory increment mode"] + pub const fn minc(&self) -> super::vals::Inc { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Memory increment mode"] + pub fn set_minc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Peripheral size"] + pub const fn psize(&self) -> super::vals::Size { + let val = (self.0 >> 8usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Peripheral size"] + pub fn set_psize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); + } + #[doc = "Memory size"] + pub const fn msize(&self) -> super::vals::Size { + let val = (self.0 >> 10usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Memory size"] + pub fn set_msize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 10usize)) | (((val.0 as u32) & 0x03) << 10usize); + } + #[doc = "Channel Priority level"] + pub const fn pl(&self) -> super::vals::Pl { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Pl(val as u8) + } + #[doc = "Channel Priority level"] + pub fn set_pl(&mut self, val: super::vals::Pl) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "Memory to memory mode"] + pub const fn mem2mem(&self) -> super::vals::Memmem { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Memmem(val as u8) + } + #[doc = "Memory to memory mode"] + pub fn set_mem2mem(&mut self, val: super::vals::Memmem) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + #[doc = "DMA channel 1 number of data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ndtr(pub u32); + impl Ndtr { + #[doc = "Number of data to transfer"] + pub const fn ndt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Number of data to transfer"] + pub fn set_ndt(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Ndtr { + fn default() -> Ndtr { + Ndtr(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Read from peripheral"] + pub const FROMPERIPHERAL: Self = Self(0); + #[doc = "Read from memory"] + pub const FROMMEMORY: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Circ(pub u8); + impl Circ { + #[doc = "Circular buffer disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Circular buffer enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pl(pub u8); + impl Pl { + #[doc = "Low priority"] + pub const LOW: Self = Self(0); + #[doc = "Medium priority"] + pub const MEDIUM: Self = Self(0x01); + #[doc = "High priority"] + pub const HIGH: Self = Self(0x02); + #[doc = "Very high priority"] + pub const VERYHIGH: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Inc(pub u8); + impl Inc { + #[doc = "Increment mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Increment mode enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Size(pub u8); + impl Size { + #[doc = "8-bit size"] + pub const BITS8: Self = Self(0); + #[doc = "16-bit size"] + pub const BITS16: Self = Self(0x01); + #[doc = "32-bit size"] + pub const BITS32: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Memmem(pub u8); + impl Memmem { + #[doc = "Memory to memory mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Memory to memory mode enabled"] + pub const ENABLED: Self = Self(0x01); + } + } +} +pub mod gpio_v1 { + use crate::generic::*; + #[doc = "General purpose I/O"] + #[derive(Copy, Clone)] + pub struct Gpio(pub *mut u8); + unsafe impl Send for Gpio {} + unsafe impl Sync for Gpio {} + impl Gpio { + #[doc = "Port configuration register low (GPIOn_CRL)"] + pub fn cr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) } + } + #[doc = "Port input data register (GPIOn_IDR)"] + pub fn idr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Port output data register (GPIOn_ODR)"] + pub fn odr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Port bit set/reset register (GPIOn_BSRR)"] + pub fn bsrr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Port bit reset register (GPIOn_BRR)"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "Port configuration lock register"] + pub fn lckr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "Port input data register (GPIOn_IDR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idr(pub u32); + impl Idr { + #[doc = "Port input data"] + pub fn idr(&self, n: usize) -> super::vals::Idr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Idr(val as u8) + } + #[doc = "Port input data"] + pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Idr { + fn default() -> Idr { + Idr(0) + } + } + #[doc = "Port bit reset register (GPIOn_BRR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Brr(pub u32); + impl Brr { + #[doc = "Reset bit"] + pub fn br(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Reset bit"] + pub fn set_br(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Brr { + fn default() -> Brr { + Brr(0) + } + } + #[doc = "Port output data register (GPIOn_ODR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Odr(pub u32); + impl Odr { + #[doc = "Port output data"] + pub fn odr(&self, n: usize) -> super::vals::Odr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Odr(val as u8) + } + #[doc = "Port output data"] + pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Odr { + fn default() -> Odr { + Odr(0) + } + } + #[doc = "Port configuration register (GPIOn_CRx)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Port n mode bits"] + pub fn mode(&self, n: usize) -> super::vals::Mode { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Mode(val as u8) + } + #[doc = "Port n mode bits"] + pub fn set_mode(&mut self, n: usize, val: super::vals::Mode) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Port n configuration bits"] + pub fn cnf(&self, n: usize) -> super::vals::Cnf { + assert!(n < 8usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Cnf(val as u8) + } + #[doc = "Port n configuration bits"] + pub fn set_cnf(&mut self, n: usize, val: super::vals::Cnf) { + assert!(n < 8usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + #[doc = "Port bit set/reset register (GPIOn_BSRR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Bsrr(pub u32); + impl Bsrr { + #[doc = "Set bit"] + pub fn bs(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Set bit"] + pub fn set_bs(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Reset bit"] + pub fn br(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Reset bit"] + pub fn set_br(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Bsrr { + fn default() -> Bsrr { + Bsrr(0) + } + } + #[doc = "Port configuration lock register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Lckr(pub u32); + impl Lckr { + #[doc = "Port A Lock bit"] + pub fn lck(&self, n: usize) -> super::vals::Lck { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Lck(val as u8) + } + #[doc = "Port A Lock bit"] + pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Lock key"] + pub const fn lckk(&self) -> super::vals::Lckk { + let val = (self.0 >> 16usize) & 0x01; + super::vals::Lckk(val as u8) + } + #[doc = "Lock key"] + pub fn set_lckk(&mut self, val: super::vals::Lckk) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); + } + } + impl Default for Lckr { + fn default() -> Lckr { + Lckr(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cnf(pub u8); + impl Cnf { + #[doc = "Analog mode / Push-Pull mode"] + pub const PUSHPULL: Self = Self(0); + #[doc = "Floating input (reset state) / Open Drain-Mode"] + pub const OPENDRAIN: Self = Self(0x01); + #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"] + pub const ALTPUSHPULL: Self = Self(0x02); + #[doc = "Alternate Function Open-Drain Mode"] + pub const ALTOPENDRAIN: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lck(pub u8); + impl Lck { + #[doc = "Port configuration not locked"] + pub const UNLOCKED: Self = Self(0); + #[doc = "Port configuration locked"] + pub const LOCKED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Odr(pub u8); + impl Odr { + #[doc = "Set output to logic low"] + pub const LOW: Self = Self(0); + #[doc = "Set output to logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mode(pub u8); + impl Mode { + #[doc = "Input mode (reset state)"] + pub const INPUT: Self = Self(0); + #[doc = "Output mode 10 MHz"] + pub const OUTPUT: Self = Self(0x01); + #[doc = "Output mode 2 MHz"] + pub const OUTPUT2: Self = Self(0x02); + #[doc = "Output mode 50 MHz"] + pub const OUTPUT50: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Idr(pub u8); + impl Idr { + #[doc = "Input is logic low"] + pub const LOW: Self = Self(0); + #[doc = "Input is logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Brw(pub u8); + impl Brw { + #[doc = "No action on the corresponding ODx bit"] + pub const NOACTION: Self = Self(0); + #[doc = "Reset the ODx bit"] + pub const RESET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lckk(pub u8); + impl Lckk { + #[doc = "Port configuration lock key not active"] + pub const NOTACTIVE: Self = Self(0); + #[doc = "Port configuration lock key active"] + pub const ACTIVE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bsw(pub u8); + impl Bsw { + #[doc = "No action on the corresponding ODx bit"] + pub const NOACTION: Self = Self(0); + #[doc = "Sets the corresponding ODRx bit"] + pub const SET: Self = Self(0x01); + } + } +} +pub mod syscfg_l4 { + use crate::generic::*; + #[doc = "System configuration controller"] + #[derive(Copy, Clone)] + pub struct Syscfg(pub *mut u8); + unsafe impl Send for Syscfg {} + unsafe impl Sync for Syscfg {} + impl Syscfg { + #[doc = "memory remap register"] + pub fn memrmp(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "configuration register 1"] + pub fn cfgr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "external interrupt configuration register 1"] + pub fn exticr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } + } + #[doc = "SCSR"] + pub fn scsr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + #[doc = "CFGR2"] + pub fn cfgr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(28usize)) } + } + #[doc = "SWPR"] + pub fn swpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "SKR"] + pub fn skr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "SKR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Skr(pub u32); + impl Skr { + #[doc = "SRAM2 write protection key for software erase"] + pub const fn key(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "SRAM2 write protection key for software erase"] + pub fn set_key(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + } + impl Default for Skr { + fn default() -> Skr { + Skr(0) + } + } + #[doc = "external interrupt configuration register 4"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Exticr(pub u32); + impl Exticr { + #[doc = "EXTI12 configuration bits"] + pub fn exti(&self, n: usize) -> u8 { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + val as u8 + } + #[doc = "EXTI12 configuration bits"] + pub fn set_exti(&mut self, n: usize, val: u8) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); + } + } + impl Default for Exticr { + fn default() -> Exticr { + Exticr(0) + } + } + #[doc = "SCSR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Scsr(pub u32); + impl Scsr { + #[doc = "SRAM2 Erase"] + pub const fn sram2er(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 Erase"] + pub fn set_sram2er(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "SRAM2 busy by erase operation"] + pub const fn sram2bsy(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 busy by erase operation"] + pub fn set_sram2bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + } + impl Default for Scsr { + fn default() -> Scsr { + Scsr(0) + } + } + #[doc = "CFGR2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cfgr2(pub u32); + impl Cfgr2 { + #[doc = "Cortex LOCKUP (Hardfault) output enable bit"] + pub const fn cll(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Cortex LOCKUP (Hardfault) output enable bit"] + pub fn set_cll(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "SRAM2 parity lock bit"] + pub const fn spl(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 parity lock bit"] + pub fn set_spl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "PVD lock enable bit"] + pub const fn pvdl(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "PVD lock enable bit"] + pub fn set_pvdl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "ECC Lock"] + pub const fn eccl(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "ECC Lock"] + pub fn set_eccl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "SRAM2 parity error flag"] + pub const fn spf(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 parity error flag"] + pub fn set_spf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Cfgr2 { + fn default() -> Cfgr2 { + Cfgr2(0) + } + } + #[doc = "SWPR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Swpr(pub u32); + impl Swpr { + #[doc = "SRAWM2 write protection."] + pub fn pwp(&self, n: usize) -> bool { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "SRAWM2 write protection."] + pub fn set_pwp(&mut self, n: usize, val: bool) { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Swpr { + fn default() -> Swpr { + Swpr(0) + } + } + #[doc = "configuration register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cfgr1(pub u32); + impl Cfgr1 { + #[doc = "Firewall disable"] + pub const fn fwdis(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Firewall disable"] + pub fn set_fwdis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "I/O analog switch voltage booster enable"] + pub const fn boosten(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "I/O analog switch voltage booster enable"] + pub fn set_boosten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"] + pub const fn i2c_pb6_fmp(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"] + pub fn set_i2c_pb6_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"] + pub const fn i2c_pb7_fmp(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"] + pub fn set_i2c_pb7_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"] + pub const fn i2c_pb8_fmp(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"] + pub fn set_i2c_pb8_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"] + pub const fn i2c_pb9_fmp(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"] + pub fn set_i2c_pb9_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "I2C1 Fast-mode Plus driving capability activation"] + pub const fn i2c1_fmp(&self) -> bool { + let val = (self.0 >> 20usize) & 0x01; + val != 0 + } + #[doc = "I2C1 Fast-mode Plus driving capability activation"] + pub fn set_i2c1_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); + } + #[doc = "I2C2 Fast-mode Plus driving capability activation"] + pub const fn i2c2_fmp(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "I2C2 Fast-mode Plus driving capability activation"] + pub fn set_i2c2_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "I2C3 Fast-mode Plus driving capability activation"] + pub const fn i2c3_fmp(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "I2C3 Fast-mode Plus driving capability activation"] + pub fn set_i2c3_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "Floating Point Unit interrupts enable bits"] + pub const fn fpu_ie(&self) -> u8 { + let val = (self.0 >> 26usize) & 0x3f; + val as u8 + } + #[doc = "Floating Point Unit interrupts enable bits"] + pub fn set_fpu_ie(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 26usize)) | (((val as u32) & 0x3f) << 26usize); + } + } + impl Default for Cfgr1 { + fn default() -> Cfgr1 { + Cfgr1(0) + } + } + #[doc = "memory remap register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Memrmp(pub u32); + impl Memrmp { + #[doc = "Memory mapping selection"] + pub const fn mem_mode(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x07; + val as u8 + } + #[doc = "Memory mapping selection"] + pub fn set_mem_mode(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); + } + #[doc = "QUADSPI memory mapping swap"] + pub const fn qfs(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "QUADSPI memory mapping swap"] + pub fn set_qfs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Flash Bank mode selection"] + pub const fn fb_mode(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Flash Bank mode selection"] + pub fn set_fb_mode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Memrmp { + fn default() -> Memrmp { + Memrmp(0) + } + } + } +} +pub mod rng_v1 { + use crate::generic::*; + #[doc = "Random number generator"] + #[derive(Copy, Clone)] + pub struct Rng(pub *mut u8); + unsafe impl Send for Rng {} + unsafe impl Sync for Rng {} + impl Rng { + #[doc = "control register"] + pub fn cr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Data ready"] + pub const fn drdy(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Data ready"] + pub fn set_drdy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Clock error current status"] + pub const fn cecs(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Clock error current status"] + pub fn set_cecs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Seed error current status"] + pub const fn secs(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Seed error current status"] + pub fn set_secs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Clock error interrupt status"] + pub const fn ceis(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Clock error interrupt status"] + pub fn set_ceis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Seed error interrupt status"] + pub const fn seis(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Seed error interrupt status"] + pub fn set_seis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + #[doc = "control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Random number generator enable"] + pub const fn rngen(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Random number generator enable"] + pub fn set_rngen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Interrupt enable"] + pub const fn ie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Interrupt enable"] + pub fn set_ie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + } } diff --git a/embassy-stm32/src/pac/stm32l431cb.rs b/embassy-stm32/src/pac/stm32l431cb.rs index ea00d69f..ddb208da 100644 --- a/embassy-stm32/src/pac/stm32l431cb.rs +++ b/embassy-stm32/src/pac/stm32l431cb.rs @@ -129,7 +129,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -143,7 +143,7 @@ impl_spi_pin!(SPI1, Sck, PE13, 5); impl_spi_pin!(SPI1, Miso, PE14, 5); impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); impl_spi_pin!(SPI2, Miso, PB14, 5); @@ -154,7 +154,7 @@ impl_spi_pin!(SPI2, Sck, PD1, 5); impl_spi_pin!(SPI2, Miso, PD3, 5); impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l431cc.rs b/embassy-stm32/src/pac/stm32l431cc.rs index ea00d69f..ddb208da 100644 --- a/embassy-stm32/src/pac/stm32l431cc.rs +++ b/embassy-stm32/src/pac/stm32l431cc.rs @@ -129,7 +129,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -143,7 +143,7 @@ impl_spi_pin!(SPI1, Sck, PE13, 5); impl_spi_pin!(SPI1, Miso, PE14, 5); impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); impl_spi_pin!(SPI2, Miso, PB14, 5); @@ -154,7 +154,7 @@ impl_spi_pin!(SPI2, Sck, PD1, 5); impl_spi_pin!(SPI2, Miso, PD3, 5); impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l431kb.rs b/embassy-stm32/src/pac/stm32l431kb.rs index 09ab12d6..89364c77 100644 --- a/embassy-stm32/src/pac/stm32l431kb.rs +++ b/embassy-stm32/src/pac/stm32l431kb.rs @@ -129,7 +129,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -143,7 +143,7 @@ impl_spi_pin!(SPI1, Sck, PE13, 5); impl_spi_pin!(SPI1, Miso, PE14, 5); impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l431kc.rs b/embassy-stm32/src/pac/stm32l431kc.rs index 09ab12d6..89364c77 100644 --- a/embassy-stm32/src/pac/stm32l431kc.rs +++ b/embassy-stm32/src/pac/stm32l431kc.rs @@ -129,7 +129,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -143,7 +143,7 @@ impl_spi_pin!(SPI1, Sck, PE13, 5); impl_spi_pin!(SPI1, Miso, PE14, 5); impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l431rb.rs b/embassy-stm32/src/pac/stm32l431rb.rs index ea00d69f..ddb208da 100644 --- a/embassy-stm32/src/pac/stm32l431rb.rs +++ b/embassy-stm32/src/pac/stm32l431rb.rs @@ -129,7 +129,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -143,7 +143,7 @@ impl_spi_pin!(SPI1, Sck, PE13, 5); impl_spi_pin!(SPI1, Miso, PE14, 5); impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); impl_spi_pin!(SPI2, Miso, PB14, 5); @@ -154,7 +154,7 @@ impl_spi_pin!(SPI2, Sck, PD1, 5); impl_spi_pin!(SPI2, Miso, PD3, 5); impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l431rc.rs b/embassy-stm32/src/pac/stm32l431rc.rs index ea00d69f..ddb208da 100644 --- a/embassy-stm32/src/pac/stm32l431rc.rs +++ b/embassy-stm32/src/pac/stm32l431rc.rs @@ -129,7 +129,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -143,7 +143,7 @@ impl_spi_pin!(SPI1, Sck, PE13, 5); impl_spi_pin!(SPI1, Miso, PE14, 5); impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); impl_spi_pin!(SPI2, Miso, PB14, 5); @@ -154,7 +154,7 @@ impl_spi_pin!(SPI2, Sck, PD1, 5); impl_spi_pin!(SPI2, Miso, PD3, 5); impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l431vc.rs b/embassy-stm32/src/pac/stm32l431vc.rs index ea00d69f..ddb208da 100644 --- a/embassy-stm32/src/pac/stm32l431vc.rs +++ b/embassy-stm32/src/pac/stm32l431vc.rs @@ -129,7 +129,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -143,7 +143,7 @@ impl_spi_pin!(SPI1, Sck, PE13, 5); impl_spi_pin!(SPI1, Miso, PE14, 5); impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); impl_spi_pin!(SPI2, Miso, PB14, 5); @@ -154,7 +154,7 @@ impl_spi_pin!(SPI2, Sck, PD1, 5); impl_spi_pin!(SPI2, Miso, PD3, 5); impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l432kb.rs b/embassy-stm32/src/pac/stm32l432kb.rs index ac3b809c..a5e060d0 100644 --- a/embassy-stm32/src/pac/stm32l432kb.rs +++ b/embassy-stm32/src/pac/stm32l432kb.rs @@ -95,7 +95,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -106,7 +106,7 @@ impl_spi_pin!(SPI1, Sck, PB3, 5); impl_spi_pin!(SPI1, Miso, PB4, 5); impl_spi_pin!(SPI1, Mosi, PB5, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l432kc.rs b/embassy-stm32/src/pac/stm32l432kc.rs index ac3b809c..a5e060d0 100644 --- a/embassy-stm32/src/pac/stm32l432kc.rs +++ b/embassy-stm32/src/pac/stm32l432kc.rs @@ -95,7 +95,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -106,7 +106,7 @@ impl_spi_pin!(SPI1, Sck, PB3, 5); impl_spi_pin!(SPI1, Miso, PB4, 5); impl_spi_pin!(SPI1, Mosi, PB5, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l433cb.rs b/embassy-stm32/src/pac/stm32l433cb.rs index bcfd7f87..0c60e842 100644 --- a/embassy-stm32/src/pac/stm32l433cb.rs +++ b/embassy-stm32/src/pac/stm32l433cb.rs @@ -129,7 +129,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -143,7 +143,7 @@ impl_spi_pin!(SPI1, Sck, PE13, 5); impl_spi_pin!(SPI1, Miso, PE14, 5); impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); impl_spi_pin!(SPI2, Miso, PB14, 5); @@ -154,7 +154,7 @@ impl_spi_pin!(SPI2, Sck, PD1, 5); impl_spi_pin!(SPI2, Miso, PD3, 5); impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l433cc.rs b/embassy-stm32/src/pac/stm32l433cc.rs index bcfd7f87..0c60e842 100644 --- a/embassy-stm32/src/pac/stm32l433cc.rs +++ b/embassy-stm32/src/pac/stm32l433cc.rs @@ -129,7 +129,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -143,7 +143,7 @@ impl_spi_pin!(SPI1, Sck, PE13, 5); impl_spi_pin!(SPI1, Miso, PE14, 5); impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); impl_spi_pin!(SPI2, Miso, PB14, 5); @@ -154,7 +154,7 @@ impl_spi_pin!(SPI2, Sck, PD1, 5); impl_spi_pin!(SPI2, Miso, PD3, 5); impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l433rb.rs b/embassy-stm32/src/pac/stm32l433rb.rs index bcfd7f87..0c60e842 100644 --- a/embassy-stm32/src/pac/stm32l433rb.rs +++ b/embassy-stm32/src/pac/stm32l433rb.rs @@ -129,7 +129,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -143,7 +143,7 @@ impl_spi_pin!(SPI1, Sck, PE13, 5); impl_spi_pin!(SPI1, Miso, PE14, 5); impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); impl_spi_pin!(SPI2, Miso, PB14, 5); @@ -154,7 +154,7 @@ impl_spi_pin!(SPI2, Sck, PD1, 5); impl_spi_pin!(SPI2, Miso, PD3, 5); impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l433rc.rs b/embassy-stm32/src/pac/stm32l433rc.rs index bcfd7f87..0c60e842 100644 --- a/embassy-stm32/src/pac/stm32l433rc.rs +++ b/embassy-stm32/src/pac/stm32l433rc.rs @@ -129,7 +129,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -143,7 +143,7 @@ impl_spi_pin!(SPI1, Sck, PE13, 5); impl_spi_pin!(SPI1, Miso, PE14, 5); impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); impl_spi_pin!(SPI2, Miso, PB14, 5); @@ -154,7 +154,7 @@ impl_spi_pin!(SPI2, Sck, PD1, 5); impl_spi_pin!(SPI2, Miso, PD3, 5); impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l433vc.rs b/embassy-stm32/src/pac/stm32l433vc.rs index bcfd7f87..0c60e842 100644 --- a/embassy-stm32/src/pac/stm32l433vc.rs +++ b/embassy-stm32/src/pac/stm32l433vc.rs @@ -129,7 +129,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -143,7 +143,7 @@ impl_spi_pin!(SPI1, Sck, PE13, 5); impl_spi_pin!(SPI1, Miso, PE14, 5); impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); impl_spi_pin!(SPI2, Miso, PB14, 5); @@ -154,7 +154,7 @@ impl_spi_pin!(SPI2, Sck, PD1, 5); impl_spi_pin!(SPI2, Miso, PD3, 5); impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l442kc.rs b/embassy-stm32/src/pac/stm32l442kc.rs index b54a36ae..dfccb891 100644 --- a/embassy-stm32/src/pac/stm32l442kc.rs +++ b/embassy-stm32/src/pac/stm32l442kc.rs @@ -95,7 +95,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -106,7 +106,7 @@ impl_spi_pin!(SPI1, Sck, PB3, 5); impl_spi_pin!(SPI1, Miso, PB4, 5); impl_spi_pin!(SPI1, Mosi, PB5, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l443cc.rs b/embassy-stm32/src/pac/stm32l443cc.rs index 434050d6..5e4f9fe1 100644 --- a/embassy-stm32/src/pac/stm32l443cc.rs +++ b/embassy-stm32/src/pac/stm32l443cc.rs @@ -129,7 +129,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -143,7 +143,7 @@ impl_spi_pin!(SPI1, Sck, PE13, 5); impl_spi_pin!(SPI1, Miso, PE14, 5); impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); impl_spi_pin!(SPI2, Miso, PB14, 5); @@ -154,7 +154,7 @@ impl_spi_pin!(SPI2, Sck, PD1, 5); impl_spi_pin!(SPI2, Miso, PD3, 5); impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l443rc.rs b/embassy-stm32/src/pac/stm32l443rc.rs index 434050d6..5e4f9fe1 100644 --- a/embassy-stm32/src/pac/stm32l443rc.rs +++ b/embassy-stm32/src/pac/stm32l443rc.rs @@ -129,7 +129,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -143,7 +143,7 @@ impl_spi_pin!(SPI1, Sck, PE13, 5); impl_spi_pin!(SPI1, Miso, PE14, 5); impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); impl_spi_pin!(SPI2, Miso, PB14, 5); @@ -154,7 +154,7 @@ impl_spi_pin!(SPI2, Sck, PD1, 5); impl_spi_pin!(SPI2, Miso, PD3, 5); impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l443vc.rs b/embassy-stm32/src/pac/stm32l443vc.rs index 434050d6..5e4f9fe1 100644 --- a/embassy-stm32/src/pac/stm32l443vc.rs +++ b/embassy-stm32/src/pac/stm32l443vc.rs @@ -129,7 +129,7 @@ impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -143,7 +143,7 @@ impl_spi_pin!(SPI1, Sck, PE13, 5); impl_spi_pin!(SPI1, Miso, PE14, 5); impl_spi_pin!(SPI1, Mosi, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); impl_spi_pin!(SPI2, Miso, PB14, 5); @@ -154,7 +154,7 @@ impl_spi_pin!(SPI2, Sck, PD1, 5); impl_spi_pin!(SPI2, Miso, PD3, 5); impl_spi_pin!(SPI2, Mosi, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l496ae.rs b/embassy-stm32/src/pac/stm32l496ae.rs index 6e2a59f6..22dc6767 100644 --- a/embassy-stm32/src/pac/stm32l496ae.rs +++ b/embassy-stm32/src/pac/stm32l496ae.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l496ag.rs b/embassy-stm32/src/pac/stm32l496ag.rs index 6e2a59f6..22dc6767 100644 --- a/embassy-stm32/src/pac/stm32l496ag.rs +++ b/embassy-stm32/src/pac/stm32l496ag.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l496qe.rs b/embassy-stm32/src/pac/stm32l496qe.rs index 6e2a59f6..22dc6767 100644 --- a/embassy-stm32/src/pac/stm32l496qe.rs +++ b/embassy-stm32/src/pac/stm32l496qe.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l496qg.rs b/embassy-stm32/src/pac/stm32l496qg.rs index 6e2a59f6..22dc6767 100644 --- a/embassy-stm32/src/pac/stm32l496qg.rs +++ b/embassy-stm32/src/pac/stm32l496qg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l496re.rs b/embassy-stm32/src/pac/stm32l496re.rs index 6e2a59f6..22dc6767 100644 --- a/embassy-stm32/src/pac/stm32l496re.rs +++ b/embassy-stm32/src/pac/stm32l496re.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l496rg.rs b/embassy-stm32/src/pac/stm32l496rg.rs index 6e2a59f6..22dc6767 100644 --- a/embassy-stm32/src/pac/stm32l496rg.rs +++ b/embassy-stm32/src/pac/stm32l496rg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l496ve.rs b/embassy-stm32/src/pac/stm32l496ve.rs index 6e2a59f6..22dc6767 100644 --- a/embassy-stm32/src/pac/stm32l496ve.rs +++ b/embassy-stm32/src/pac/stm32l496ve.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l496vg.rs b/embassy-stm32/src/pac/stm32l496vg.rs index 6e2a59f6..22dc6767 100644 --- a/embassy-stm32/src/pac/stm32l496vg.rs +++ b/embassy-stm32/src/pac/stm32l496vg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l496wg.rs b/embassy-stm32/src/pac/stm32l496wg.rs index 6e2a59f6..22dc6767 100644 --- a/embassy-stm32/src/pac/stm32l496wg.rs +++ b/embassy-stm32/src/pac/stm32l496wg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l496ze.rs b/embassy-stm32/src/pac/stm32l496ze.rs index 6e2a59f6..22dc6767 100644 --- a/embassy-stm32/src/pac/stm32l496ze.rs +++ b/embassy-stm32/src/pac/stm32l496ze.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l496zg.rs b/embassy-stm32/src/pac/stm32l496zg.rs index 6e2a59f6..22dc6767 100644 --- a/embassy-stm32/src/pac/stm32l496zg.rs +++ b/embassy-stm32/src/pac/stm32l496zg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4a6ag.rs b/embassy-stm32/src/pac/stm32l4a6ag.rs index 8ca5eca3..3b8c1f09 100644 --- a/embassy-stm32/src/pac/stm32l4a6ag.rs +++ b/embassy-stm32/src/pac/stm32l4a6ag.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4a6qg.rs b/embassy-stm32/src/pac/stm32l4a6qg.rs index 8ca5eca3..3b8c1f09 100644 --- a/embassy-stm32/src/pac/stm32l4a6qg.rs +++ b/embassy-stm32/src/pac/stm32l4a6qg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4a6rg.rs b/embassy-stm32/src/pac/stm32l4a6rg.rs index 8ca5eca3..3b8c1f09 100644 --- a/embassy-stm32/src/pac/stm32l4a6rg.rs +++ b/embassy-stm32/src/pac/stm32l4a6rg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4a6vg.rs b/embassy-stm32/src/pac/stm32l4a6vg.rs index 8ca5eca3..3b8c1f09 100644 --- a/embassy-stm32/src/pac/stm32l4a6vg.rs +++ b/embassy-stm32/src/pac/stm32l4a6vg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4a6zg.rs b/embassy-stm32/src/pac/stm32l4a6zg.rs index 8ca5eca3..3b8c1f09 100644 --- a/embassy-stm32/src/pac/stm32l4a6zg.rs +++ b/embassy-stm32/src/pac/stm32l4a6zg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4p5ae.rs b/embassy-stm32/src/pac/stm32l4p5ae.rs index c406d194..c3627b89 100644 --- a/embassy-stm32/src/pac/stm32l4p5ae.rs +++ b/embassy-stm32/src/pac/stm32l4p5ae.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4p5ag.rs b/embassy-stm32/src/pac/stm32l4p5ag.rs index c406d194..c3627b89 100644 --- a/embassy-stm32/src/pac/stm32l4p5ag.rs +++ b/embassy-stm32/src/pac/stm32l4p5ag.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4p5ce.rs b/embassy-stm32/src/pac/stm32l4p5ce.rs index c406d194..c3627b89 100644 --- a/embassy-stm32/src/pac/stm32l4p5ce.rs +++ b/embassy-stm32/src/pac/stm32l4p5ce.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4p5cg.rs b/embassy-stm32/src/pac/stm32l4p5cg.rs index c406d194..c3627b89 100644 --- a/embassy-stm32/src/pac/stm32l4p5cg.rs +++ b/embassy-stm32/src/pac/stm32l4p5cg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4p5qe.rs b/embassy-stm32/src/pac/stm32l4p5qe.rs index c406d194..c3627b89 100644 --- a/embassy-stm32/src/pac/stm32l4p5qe.rs +++ b/embassy-stm32/src/pac/stm32l4p5qe.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4p5qg.rs b/embassy-stm32/src/pac/stm32l4p5qg.rs index c406d194..c3627b89 100644 --- a/embassy-stm32/src/pac/stm32l4p5qg.rs +++ b/embassy-stm32/src/pac/stm32l4p5qg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4p5re.rs b/embassy-stm32/src/pac/stm32l4p5re.rs index c406d194..c3627b89 100644 --- a/embassy-stm32/src/pac/stm32l4p5re.rs +++ b/embassy-stm32/src/pac/stm32l4p5re.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4p5rg.rs b/embassy-stm32/src/pac/stm32l4p5rg.rs index c406d194..c3627b89 100644 --- a/embassy-stm32/src/pac/stm32l4p5rg.rs +++ b/embassy-stm32/src/pac/stm32l4p5rg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4p5ve.rs b/embassy-stm32/src/pac/stm32l4p5ve.rs index c406d194..c3627b89 100644 --- a/embassy-stm32/src/pac/stm32l4p5ve.rs +++ b/embassy-stm32/src/pac/stm32l4p5ve.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4p5vg.rs b/embassy-stm32/src/pac/stm32l4p5vg.rs index c406d194..c3627b89 100644 --- a/embassy-stm32/src/pac/stm32l4p5vg.rs +++ b/embassy-stm32/src/pac/stm32l4p5vg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4p5ze.rs b/embassy-stm32/src/pac/stm32l4p5ze.rs index c406d194..c3627b89 100644 --- a/embassy-stm32/src/pac/stm32l4p5ze.rs +++ b/embassy-stm32/src/pac/stm32l4p5ze.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4p5zg.rs b/embassy-stm32/src/pac/stm32l4p5zg.rs index c406d194..c3627b89 100644 --- a/embassy-stm32/src/pac/stm32l4p5zg.rs +++ b/embassy-stm32/src/pac/stm32l4p5zg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4q5ag.rs b/embassy-stm32/src/pac/stm32l4q5ag.rs index d8552a71..af7690f9 100644 --- a/embassy-stm32/src/pac/stm32l4q5ag.rs +++ b/embassy-stm32/src/pac/stm32l4q5ag.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4q5cg.rs b/embassy-stm32/src/pac/stm32l4q5cg.rs index d8552a71..af7690f9 100644 --- a/embassy-stm32/src/pac/stm32l4q5cg.rs +++ b/embassy-stm32/src/pac/stm32l4q5cg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4q5qg.rs b/embassy-stm32/src/pac/stm32l4q5qg.rs index d8552a71..af7690f9 100644 --- a/embassy-stm32/src/pac/stm32l4q5qg.rs +++ b/embassy-stm32/src/pac/stm32l4q5qg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4q5rg.rs b/embassy-stm32/src/pac/stm32l4q5rg.rs index d8552a71..af7690f9 100644 --- a/embassy-stm32/src/pac/stm32l4q5rg.rs +++ b/embassy-stm32/src/pac/stm32l4q5rg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4q5vg.rs b/embassy-stm32/src/pac/stm32l4q5vg.rs index d8552a71..af7690f9 100644 --- a/embassy-stm32/src/pac/stm32l4q5vg.rs +++ b/embassy-stm32/src/pac/stm32l4q5vg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4q5zg.rs b/embassy-stm32/src/pac/stm32l4q5zg.rs index d8552a71..af7690f9 100644 --- a/embassy-stm32/src/pac/stm32l4q5zg.rs +++ b/embassy-stm32/src/pac/stm32l4q5zg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r5ag.rs b/embassy-stm32/src/pac/stm32l4r5ag.rs index b739f4df..9f7c5e88 100644 --- a/embassy-stm32/src/pac/stm32l4r5ag.rs +++ b/embassy-stm32/src/pac/stm32l4r5ag.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r5ai.rs b/embassy-stm32/src/pac/stm32l4r5ai.rs index b739f4df..9f7c5e88 100644 --- a/embassy-stm32/src/pac/stm32l4r5ai.rs +++ b/embassy-stm32/src/pac/stm32l4r5ai.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r5qg.rs b/embassy-stm32/src/pac/stm32l4r5qg.rs index b739f4df..9f7c5e88 100644 --- a/embassy-stm32/src/pac/stm32l4r5qg.rs +++ b/embassy-stm32/src/pac/stm32l4r5qg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r5qi.rs b/embassy-stm32/src/pac/stm32l4r5qi.rs index b739f4df..9f7c5e88 100644 --- a/embassy-stm32/src/pac/stm32l4r5qi.rs +++ b/embassy-stm32/src/pac/stm32l4r5qi.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r5vg.rs b/embassy-stm32/src/pac/stm32l4r5vg.rs index b739f4df..9f7c5e88 100644 --- a/embassy-stm32/src/pac/stm32l4r5vg.rs +++ b/embassy-stm32/src/pac/stm32l4r5vg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r5vi.rs b/embassy-stm32/src/pac/stm32l4r5vi.rs index b739f4df..9f7c5e88 100644 --- a/embassy-stm32/src/pac/stm32l4r5vi.rs +++ b/embassy-stm32/src/pac/stm32l4r5vi.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r5zg.rs b/embassy-stm32/src/pac/stm32l4r5zg.rs index b739f4df..9f7c5e88 100644 --- a/embassy-stm32/src/pac/stm32l4r5zg.rs +++ b/embassy-stm32/src/pac/stm32l4r5zg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r5zi.rs b/embassy-stm32/src/pac/stm32l4r5zi.rs index b739f4df..9f7c5e88 100644 --- a/embassy-stm32/src/pac/stm32l4r5zi.rs +++ b/embassy-stm32/src/pac/stm32l4r5zi.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r7ai.rs b/embassy-stm32/src/pac/stm32l4r7ai.rs index 6aa7197f..ae6fb4c4 100644 --- a/embassy-stm32/src/pac/stm32l4r7ai.rs +++ b/embassy-stm32/src/pac/stm32l4r7ai.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r7vi.rs b/embassy-stm32/src/pac/stm32l4r7vi.rs index 6aa7197f..ae6fb4c4 100644 --- a/embassy-stm32/src/pac/stm32l4r7vi.rs +++ b/embassy-stm32/src/pac/stm32l4r7vi.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r7zi.rs b/embassy-stm32/src/pac/stm32l4r7zi.rs index 6aa7197f..ae6fb4c4 100644 --- a/embassy-stm32/src/pac/stm32l4r7zi.rs +++ b/embassy-stm32/src/pac/stm32l4r7zi.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r9ag.rs b/embassy-stm32/src/pac/stm32l4r9ag.rs index cd85f5bf..6bf045d2 100644 --- a/embassy-stm32/src/pac/stm32l4r9ag.rs +++ b/embassy-stm32/src/pac/stm32l4r9ag.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r9ai.rs b/embassy-stm32/src/pac/stm32l4r9ai.rs index cd85f5bf..6bf045d2 100644 --- a/embassy-stm32/src/pac/stm32l4r9ai.rs +++ b/embassy-stm32/src/pac/stm32l4r9ai.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r9vg.rs b/embassy-stm32/src/pac/stm32l4r9vg.rs index cd85f5bf..6bf045d2 100644 --- a/embassy-stm32/src/pac/stm32l4r9vg.rs +++ b/embassy-stm32/src/pac/stm32l4r9vg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r9vi.rs b/embassy-stm32/src/pac/stm32l4r9vi.rs index cd85f5bf..6bf045d2 100644 --- a/embassy-stm32/src/pac/stm32l4r9vi.rs +++ b/embassy-stm32/src/pac/stm32l4r9vi.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r9zg.rs b/embassy-stm32/src/pac/stm32l4r9zg.rs index cd85f5bf..6bf045d2 100644 --- a/embassy-stm32/src/pac/stm32l4r9zg.rs +++ b/embassy-stm32/src/pac/stm32l4r9zg.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4r9zi.rs b/embassy-stm32/src/pac/stm32l4r9zi.rs index cd85f5bf..6bf045d2 100644 --- a/embassy-stm32/src/pac/stm32l4r9zi.rs +++ b/embassy-stm32/src/pac/stm32l4r9zi.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4s5ai.rs b/embassy-stm32/src/pac/stm32l4s5ai.rs index c101f5c5..ef21a80f 100644 --- a/embassy-stm32/src/pac/stm32l4s5ai.rs +++ b/embassy-stm32/src/pac/stm32l4s5ai.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4s5qi.rs b/embassy-stm32/src/pac/stm32l4s5qi.rs index c101f5c5..ef21a80f 100644 --- a/embassy-stm32/src/pac/stm32l4s5qi.rs +++ b/embassy-stm32/src/pac/stm32l4s5qi.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4s5vi.rs b/embassy-stm32/src/pac/stm32l4s5vi.rs index c101f5c5..ef21a80f 100644 --- a/embassy-stm32/src/pac/stm32l4s5vi.rs +++ b/embassy-stm32/src/pac/stm32l4s5vi.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4s5zi.rs b/embassy-stm32/src/pac/stm32l4s5zi.rs index c101f5c5..ef21a80f 100644 --- a/embassy-stm32/src/pac/stm32l4s5zi.rs +++ b/embassy-stm32/src/pac/stm32l4s5zi.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4s7ai.rs b/embassy-stm32/src/pac/stm32l4s7ai.rs index c6cc8f7d..6c527607 100644 --- a/embassy-stm32/src/pac/stm32l4s7ai.rs +++ b/embassy-stm32/src/pac/stm32l4s7ai.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4s7vi.rs b/embassy-stm32/src/pac/stm32l4s7vi.rs index c6cc8f7d..6c527607 100644 --- a/embassy-stm32/src/pac/stm32l4s7vi.rs +++ b/embassy-stm32/src/pac/stm32l4s7vi.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4s7zi.rs b/embassy-stm32/src/pac/stm32l4s7zi.rs index c6cc8f7d..6c527607 100644 --- a/embassy-stm32/src/pac/stm32l4s7zi.rs +++ b/embassy-stm32/src/pac/stm32l4s7zi.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4s9ai.rs b/embassy-stm32/src/pac/stm32l4s9ai.rs index 7b93516a..3694825e 100644 --- a/embassy-stm32/src/pac/stm32l4s9ai.rs +++ b/embassy-stm32/src/pac/stm32l4s9ai.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4s9vi.rs b/embassy-stm32/src/pac/stm32l4s9vi.rs index 7b93516a..3694825e 100644 --- a/embassy-stm32/src/pac/stm32l4s9vi.rs +++ b/embassy-stm32/src/pac/stm32l4s9vi.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/pac/stm32l4s9zi.rs b/embassy-stm32/src/pac/stm32l4s9zi.rs index 7b93516a..3694825e 100644 --- a/embassy-stm32/src/pac/stm32l4s9zi.rs +++ b/embassy-stm32/src/pac/stm32l4s9zi.rs @@ -180,7 +180,7 @@ impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); -impl_spi!(SPI1); +impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); impl_spi_pin!(SPI1, Miso, PA11, 5); impl_spi_pin!(SPI1, Mosi, PA12, 5); @@ -197,7 +197,7 @@ impl_spi_pin!(SPI1, Sck, PG2, 5); impl_spi_pin!(SPI1, Miso, PG3, 5); impl_spi_pin!(SPI1, Mosi, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); -impl_spi!(SPI2); +impl_spi!(SPI2, APB1); impl_spi_pin!(SPI2, Sck, PA9, 3); impl_spi_pin!(SPI2, Sck, PB10, 5); impl_spi_pin!(SPI2, Sck, PB13, 5); @@ -214,7 +214,7 @@ impl_spi_pin!(SPI2, Sck, PI1, 5); impl_spi_pin!(SPI2, Miso, PI2, 5); impl_spi_pin!(SPI2, Mosi, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); -impl_spi!(SPI3); +impl_spi!(SPI3, APB1); impl_spi_pin!(SPI3, Sck, PB3, 6); impl_spi_pin!(SPI3, Miso, PB4, 6); impl_spi_pin!(SPI3, Mosi, PB5, 6); diff --git a/embassy-stm32/src/spi.rs b/embassy-stm32/src/spi.rs index c581f146..d9522458 100644 --- a/embassy-stm32/src/spi.rs +++ b/embassy-stm32/src/spi.rs @@ -7,10 +7,18 @@ use embedded_hal::blocking::spi::{Write, Transfer}; use embassy::util::Unborrow; use embassy_extras::{impl_unborrow, unborrow}; use crate::gpio::{Pin, AnyPin}; -use crate::pac::gpio::vals::Afr; +use crate::pac::gpio::vals::{Afr, Moder}; +use crate::pac::spi; use crate::pac::gpio::Gpio; +use crate::time::Hertz; //use crate::pac::spi; +// TODO move upwards in the tree +pub enum ByteOrder { + LsbFirst, + MsbFirst +} + pub struct Spi<'d, T: Instance> { peri: T, sck: AnyPin, @@ -21,24 +29,78 @@ pub struct Spi<'d, T: Instance> { } impl<'d, T: Instance> Spi<'d, T> { - pub fn new(peri: impl Unborrow + 'd, - sck: impl Unborrow>, - mosi: impl Unborrow>, - miso: impl Unborrow>, - ) -> Self { + pub fn new(pclk: Hertz, + peri: impl Unborrow + 'd, + sck: impl Unborrow>, + mosi: impl Unborrow>, + miso: impl Unborrow>, + mode: Mode, + byte_order: ByteOrder, + freq: F, + ) -> Self + where + F: Into + { unborrow!(peri); unborrow!(sck, mosi, miso); unsafe { - Self::configure_pin( sck.block(), sck.pin() as usize, sck.af() ); - Self::configure_pin( mosi.block(), mosi.pin() as usize, mosi.af() ); - Self::configure_pin( miso.block(), miso.pin() as usize, miso.af() ); + Self::configure_pin(sck.block(), sck.pin() as _, sck.af()); + Self::configure_pin(mosi.block(), mosi.pin() as _, mosi.af()); + Self::configure_pin(miso.block(), miso.pin() as _, miso.af()); } let sck = sck.degrade(); let mosi = mosi.degrade(); let miso = miso.degrade(); + // FRXTH: RXNE event is generated if the FIFO level is greater than or equal to + // 8-bit + // DS: 8-bit data size + // SSOE: Slave Select output disabled + unsafe { + T::regs().cr2() + .write(|w| { + // 8-bit transfers + w.set_ds( spi::vals::Ds(0b0111)); + w.set_frxth( spi::vals::Frxth::QUARTER); + w.set_ssoe(false); + }); + } + + let br = Self::compute_baud_rate(pclk, freq.into()); + + unsafe { + T::regs().cr1().write(|w| { + w.set_cpha( + match mode.phase == Phase::CaptureOnSecondTransition { + true => spi::vals::Cpha::SECONDEDGE, + false => spi::vals::Cpha::FIRSTEDGE, + } + ); + w.set_cpol(match mode.polarity == Polarity::IdleHigh { + true => spi::vals::Cpol::IDLEHIGH, + false => spi::vals::Cpol::IDLELOW, + }); + + w.set_mstr(spi::vals::Mstr::MASTER); + w.set_br(spi::vals::Br(br)); + w.set_spe(true); + w.set_lsbfirst( + match byte_order { + ByteOrder::LsbFirst => spi::vals::Lsbfirst::LSBFIRST, + ByteOrder::MsbFirst => spi::vals::Lsbfirst::MSBFIRST, + } + ); + w.set_ssi(true); + w.set_ssm(true); + w.set_crcen(false); + w.set_bidimode(spi::vals::Bidimode::UNIDIRECTIONAL); + }); + T::regs().cr2().write(|w| { + }) + } + Self { peri, sck, @@ -50,8 +112,38 @@ impl<'d, T: Instance> Spi<'d, T> { unsafe fn configure_pin(block: Gpio, pin: usize, af_num: u8) { let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) }; + block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE)); block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num))); } + + unsafe fn unconfigure_pin(block: Gpio, pin: usize) { + let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) }; + block.moder().modify(|w| w.set_moder(pin, Moder::ANALOG)); + } + + fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 { + match clocks.0 / freq.0 { + 0 => unreachable!(), + 1..=2 => 0b000, + 3..=5 => 0b001, + 6..=11 => 0b010, + 12..=23 => 0b011, + 24..=39 => 0b100, + 40..=95 => 0b101, + 96..=191 => 0b110, + _ => 0b111, + } + } +} + +impl<'d, T: Instance> Drop for Spi<'d, T> { + fn drop(&mut self) { + unsafe { + Self::unconfigure_pin(self.sck.block(), self.sck.pin() as _); + Self::unconfigure_pin(self.mosi.block(), self.mosi.pin() as _); + Self::unconfigure_pin(self.miso.block(), self.miso.pin() as _); + } + } } pub enum Error { @@ -150,25 +242,25 @@ pub(crate) mod sealed { //} pub trait Instance { - fn regs() -> &'static crate::pac::spi::Spi; + fn regs() -> &'static spi::Spi; //fn state() -> &'static State; } - pub trait Sck : Pin { + pub trait Sck: Pin { const AF: u8; fn af(&self) -> u8 { Self::AF } } - pub trait Mosi : Pin { + pub trait Mosi: Pin { const AF: u8; fn af(&self) -> u8 { Self::AF } } - pub trait Miso : Pin { + pub trait Miso: Pin { const AF: u8; fn af(&self) -> u8 { Self::AF @@ -180,20 +272,14 @@ pub trait Instance: sealed::Instance + 'static { //type Interrupt: Interrupt; } -pub trait Sck: sealed::Sck + 'static { +pub trait Sck: sealed::Sck + 'static {} -} +pub trait Mosi: sealed::Mosi + 'static {} -pub trait Mosi: sealed::Mosi + 'static { - -} - -pub trait Miso: sealed::Miso + 'static { - -} +pub trait Miso: sealed::Miso + 'static {} macro_rules! impl_spi { - ($inst:ident) => { + ($inst:ident, $clk:ident) => { impl crate::spi::sealed::Instance for peripherals::$inst { fn regs() -> &'static crate::pac::spi::Spi { &crate::pac::$inst diff --git a/embassy-stm32/src/time.rs b/embassy-stm32/src/time.rs new file mode 100644 index 00000000..4df799e3 --- /dev/null +++ b/embassy-stm32/src/time.rs @@ -0,0 +1,127 @@ + +//! Time units + +/// Bits per second +#[derive(PartialEq, PartialOrd, Clone, Copy, Debug)] +pub struct Bps(pub u32); + +/// Hertz +#[derive(PartialEq, PartialOrd, Clone, Copy, Debug)] +pub struct Hertz(pub u32); + +/// KiloHertz +#[derive(PartialEq, PartialOrd, Clone, Copy, Debug)] +pub struct KiloHertz(pub u32); + +/// MegaHertz +#[derive(PartialEq, PartialOrd, Clone, Copy, Debug)] +pub struct MegaHertz(pub u32); + +/// MilliSeconds +#[derive(PartialEq, PartialOrd, Clone, Copy, Debug)] +pub struct MilliSeconds(pub u32); + +/// MicroSeconds +#[derive(PartialEq, PartialOrd, Clone, Copy, Debug)] +pub struct MicroSeconds(pub u32); + +/// NanoSeconds +#[derive(PartialEq, PartialOrd, Clone, Copy, Debug)] +pub struct NanoSeconds(pub u32); + +/// Extension trait that adds convenience methods to the `u32` type +pub trait U32Ext { + /// Wrap in `Bps` + fn bps(self) -> Bps; + + /// Wrap in `Hertz` + fn hz(self) -> Hertz; + + /// Wrap in `KiloHertz` + fn khz(self) -> KiloHertz; + + /// Wrap in `MegaHertz` + fn mhz(self) -> MegaHertz; + + /// Wrap in "MilliSeconds" + fn ms(self) -> MilliSeconds; + + /// Wrap in "MicroSeconds" + fn us(self) -> MicroSeconds; + + /// Wrap in "NanoSeconds" + fn ns(self) -> NanoSeconds; +} + +impl U32Ext for u32 { + fn bps(self) -> Bps { + Bps(self) + } + + fn hz(self) -> Hertz { + Hertz(self) + } + + fn khz(self) -> KiloHertz { + KiloHertz(self) + } + + fn mhz(self) -> MegaHertz { + MegaHertz(self) + } + + fn ms(self) -> MilliSeconds { + MilliSeconds(self) + } + + fn us(self) -> MicroSeconds { + MicroSeconds(self) + } + + fn ns(self) -> NanoSeconds { + NanoSeconds(self) + } +} + +// Unit conversions +impl Into for Bps { + fn into(self) -> Hertz { + Hertz(self.0) + } +} + +impl Into for KiloHertz { + fn into(self) -> Hertz { + Hertz(self.0 * 1_000) + } +} + +impl Into for MegaHertz { + fn into(self) -> Hertz { + Hertz(self.0 * 1_000_000) + } +} + +impl Into for MegaHertz { + fn into(self) -> KiloHertz { + KiloHertz(self.0 * 1_000) + } +} + +impl Into for MicroSeconds { + fn into(self) -> NanoSeconds { + NanoSeconds(self.0 * 1_000) + } +} + +impl Into for MilliSeconds { + fn into(self) -> NanoSeconds { + NanoSeconds(self.0 * 1_000_000) + } +} + +impl Into for MilliSeconds { + fn into(self) -> MicroSeconds { + MicroSeconds(self.0 * 1_000) + } +} \ No newline at end of file diff --git a/embassy-stm32/stm32-data b/embassy-stm32/stm32-data index 2e550650..e06947f2 160000 --- a/embassy-stm32/stm32-data +++ b/embassy-stm32/stm32-data @@ -1 +1 @@ -Subproject commit 2e55065013cda8b5836d74570530e7fdb75a76b3 +Subproject commit e06947f20f01c938d95410d4310c09d116dbca47 From 07db3ed7c10915f16eeda08909f04afd92902b1b Mon Sep 17 00:00:00 2001 From: Bob McWhirter Date: Wed, 12 May 2021 14:18:42 -0400 Subject: [PATCH 5/8] Further improvement to SPIv2. --- embassy-stm32/src/lib.rs | 2 +- embassy-stm32/src/spi.rs | 152 ++++++++++++++++++++++++++++++--------- 2 files changed, 121 insertions(+), 33 deletions(-) diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs index b54bc4a4..3d8416c7 100644 --- a/embassy-stm32/src/lib.rs +++ b/embassy-stm32/src/lib.rs @@ -23,7 +23,7 @@ pub mod usart; // This must go LAST so that it sees the `impl_foo!` macros mod pac; -mod time; +pub mod time; pub use embassy_macros::interrupt; pub use pac::{interrupt, peripherals, Peripherals}; diff --git a/embassy-stm32/src/spi.rs b/embassy-stm32/src/spi.rs index d9522458..40944d74 100644 --- a/embassy-stm32/src/spi.rs +++ b/embassy-stm32/src/spi.rs @@ -11,12 +11,48 @@ use crate::pac::gpio::vals::{Afr, Moder}; use crate::pac::spi; use crate::pac::gpio::Gpio; use crate::time::Hertz; -//use crate::pac::spi; +use term::terminfo::parm::Param::Words; + +#[non_exhaustive] +pub struct Config { + pub mode: Mode, + pub byte_order: ByteOrder, +} + +impl Default for Config { + fn default() -> Self { + Self { + mode: MODE_0, + byte_order: ByteOrder::MsbFirst, + } + } +} // TODO move upwards in the tree pub enum ByteOrder { LsbFirst, - MsbFirst + MsbFirst, +} + +enum WordSize { + EightBit, + SixteenBit, +} + +impl WordSize { + fn ds(&self) -> spi::vals::Ds { + match self { + WordSize::EightBit => spi::vals::Ds::EIGHTBIT, + WordSize::SixteenBit => spi::vals::Ds::SIXTEENBIT, + } + } + + fn frxth(&self) -> spi::vals::Frxth { + match self { + WordSize::EightBit => spi::vals::Frxth::QUARTER, + WordSize::SixteenBit => spi::vals::Frxth::HALF, + } + } } pub struct Spi<'d, T: Instance> { @@ -34,9 +70,8 @@ impl<'d, T: Instance> Spi<'d, T> { sck: impl Unborrow>, mosi: impl Unborrow>, miso: impl Unborrow>, - mode: Mode, - byte_order: ByteOrder, freq: F, + config: Config, ) -> Self where F: Into @@ -54,16 +89,9 @@ impl<'d, T: Instance> Spi<'d, T> { let mosi = mosi.degrade(); let miso = miso.degrade(); - // FRXTH: RXNE event is generated if the FIFO level is greater than or equal to - // 8-bit - // DS: 8-bit data size - // SSOE: Slave Select output disabled unsafe { T::regs().cr2() .write(|w| { - // 8-bit transfers - w.set_ds( spi::vals::Ds(0b0111)); - w.set_frxth( spi::vals::Frxth::QUARTER); w.set_ssoe(false); }); } @@ -73,12 +101,12 @@ impl<'d, T: Instance> Spi<'d, T> { unsafe { T::regs().cr1().write(|w| { w.set_cpha( - match mode.phase == Phase::CaptureOnSecondTransition { + match config.mode.phase == Phase::CaptureOnSecondTransition { true => spi::vals::Cpha::SECONDEDGE, false => spi::vals::Cpha::FIRSTEDGE, } ); - w.set_cpol(match mode.polarity == Polarity::IdleHigh { + w.set_cpol(match config.mode.polarity == Polarity::IdleHigh { true => spi::vals::Cpol::IDLEHIGH, false => spi::vals::Cpol::IDLELOW, }); @@ -87,7 +115,7 @@ impl<'d, T: Instance> Spi<'d, T> { w.set_br(spi::vals::Br(br)); w.set_spe(true); w.set_lsbfirst( - match byte_order { + match config.byte_order { ByteOrder::LsbFirst => spi::vals::Lsbfirst::LSBFIRST, ByteOrder::MsbFirst => spi::vals::Lsbfirst::MSBFIRST, } @@ -97,8 +125,7 @@ impl<'d, T: Instance> Spi<'d, T> { w.set_crcen(false); w.set_bidimode(spi::vals::Bidimode::UNIDIRECTIONAL); }); - T::regs().cr2().write(|w| { - }) + T::regs().cr2().write(|w| {}) } Self { @@ -134,6 +161,16 @@ impl<'d, T: Instance> Spi<'d, T> { _ => 0b111, } } + + fn set_word_size(word_size: WordSize) { + unsafe { + T::regs().cr2() + .write(|w| { + w.set_ds(word_size.ds()); + w.set_frxth(word_size.frxth()); + }); + } + } } impl<'d, T: Instance> Drop for Spi<'d, T> { @@ -156,6 +193,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { type Error = Error; fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> { + Self::set_word_size(WordSize::EightBit); let regs = T::regs(); for word in words.iter() { @@ -190,6 +228,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { type Error = Error; fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> { + Self::set_word_size(WordSize::EightBit); let regs = T::regs(); for word in words.iter_mut() { @@ -203,6 +242,36 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { // spin waiting for inbound to shift in. } *word = unsafe { regs.dr().read().0 as u8 }; + let sr = unsafe { regs.sr().read() }; + if sr.fre() { + return Err(Error::Framing); + } + if sr.ovr() { + return Err(Error::Overrun); + } + if sr.crcerr() { + return Err(Error::Crc); + } + } + + Ok(words) + } +} + +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { + type Error = Error; + + fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> { + Self::set_word_size(WordSize::SixteenBit); + let regs = T::regs(); + + for word in words.iter() { + while unsafe { !regs.sr().read().txe() } { + // spin + } + unsafe { + regs.dr().write(|reg| reg.0 = *word as u32); + } loop { let sr = unsafe { regs.sr().read() }; if sr.fre() { @@ -220,6 +289,40 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { } } + Ok(()) + } +} + +impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { + type Error = Error; + + fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> { + Self::set_word_size(WordSize::SixteenBit); + let regs = T::regs(); + + for word in words.iter_mut() { + while unsafe { !regs.sr().read().txe() } { + // spin + } + unsafe { + regs.dr().write(|reg| reg.0 = *word as u32); + } + while unsafe { !regs.sr().read().rxne() } { + // spin waiting for inbound to shift in. + } + *word = unsafe { regs.dr().read().0 as u16 }; + let sr = unsafe { regs.sr().read() }; + if sr.fre() { + return Err(Error::Framing); + } + if sr.ovr() { + return Err(Error::Overrun); + } + if sr.crcerr() { + return Err(Error::Crc); + } + } + Ok(words) } } @@ -229,21 +332,8 @@ pub(crate) mod sealed { use super::*; use embassy::util::AtomicWaker; - //pub struct State { - //pub end_waker: AtomicWaker, - //} - - //impl State { - //pub const fn new() -> Self { - //Self { - //end_waker: AtomicWaker::new(), - //} - //} - //} - pub trait Instance { fn regs() -> &'static spi::Spi; - //fn state() -> &'static State; } pub trait Sck: Pin { @@ -268,9 +358,7 @@ pub(crate) mod sealed { } } -pub trait Instance: sealed::Instance + 'static { - //type Interrupt: Interrupt; -} +pub trait Instance: sealed::Instance + 'static {} pub trait Sck: sealed::Sck + 'static {} From 9e93a0999f3fe6588ead99acf423bf83bee10c7c Mon Sep 17 00:00:00 2001 From: Bob McWhirter Date: Thu, 13 May 2021 14:28:53 -0400 Subject: [PATCH 6/8] Add SPIv1, use cfg_attr to pick correct impl. Add IRQ to impl_rng!() to accomodate RNG vs HASH_RNG split. --- embassy-stm32-examples/src/bin/spi.rs | 94 + embassy-stm32/Cargo.toml | 227 +- embassy-stm32/gen.py | 5 +- embassy-stm32/src/lib.rs | 1 + embassy-stm32/src/pac/regs.rs | 16668 +++++++++--------- embassy-stm32/src/pac/stm32f401cb.rs | 29 +- embassy-stm32/src/pac/stm32f401cc.rs | 29 +- embassy-stm32/src/pac/stm32f401cd.rs | 29 +- embassy-stm32/src/pac/stm32f401ce.rs | 29 +- embassy-stm32/src/pac/stm32f401rb.rs | 29 +- embassy-stm32/src/pac/stm32f401rc.rs | 29 +- embassy-stm32/src/pac/stm32f401rd.rs | 29 +- embassy-stm32/src/pac/stm32f401re.rs | 29 +- embassy-stm32/src/pac/stm32f401vb.rs | 37 +- embassy-stm32/src/pac/stm32f401vc.rs | 37 +- embassy-stm32/src/pac/stm32f401vd.rs | 37 +- embassy-stm32/src/pac/stm32f401ve.rs | 37 +- embassy-stm32/src/pac/stm32f405oe.rs | 32 +- embassy-stm32/src/pac/stm32f405og.rs | 32 +- embassy-stm32/src/pac/stm32f405rg.rs | 32 +- embassy-stm32/src/pac/stm32f405vg.rs | 32 +- embassy-stm32/src/pac/stm32f405zg.rs | 32 +- embassy-stm32/src/pac/stm32f407ie.rs | 32 +- embassy-stm32/src/pac/stm32f407ig.rs | 32 +- embassy-stm32/src/pac/stm32f407ve.rs | 32 +- embassy-stm32/src/pac/stm32f407vg.rs | 32 +- embassy-stm32/src/pac/stm32f407ze.rs | 32 +- embassy-stm32/src/pac/stm32f407zg.rs | 32 +- embassy-stm32/src/pac/stm32f410c8.rs | 2 +- embassy-stm32/src/pac/stm32f410cb.rs | 2 +- embassy-stm32/src/pac/stm32f410r8.rs | 2 +- embassy-stm32/src/pac/stm32f410rb.rs | 2 +- embassy-stm32/src/pac/stm32f410t8.rs | 2 +- embassy-stm32/src/pac/stm32f410tb.rs | 2 +- embassy-stm32/src/pac/stm32f411cc.rs | 55 +- embassy-stm32/src/pac/stm32f411ce.rs | 55 +- embassy-stm32/src/pac/stm32f411rc.rs | 55 +- embassy-stm32/src/pac/stm32f411re.rs | 55 +- embassy-stm32/src/pac/stm32f411vc.rs | 55 +- embassy-stm32/src/pac/stm32f411ve.rs | 55 +- embassy-stm32/src/pac/stm32f412ce.rs | 44 +- embassy-stm32/src/pac/stm32f412cg.rs | 44 +- embassy-stm32/src/pac/stm32f412re.rs | 45 +- embassy-stm32/src/pac/stm32f412rg.rs | 45 +- embassy-stm32/src/pac/stm32f412ve.rs | 57 +- embassy-stm32/src/pac/stm32f412vg.rs | 57 +- embassy-stm32/src/pac/stm32f412ze.rs | 57 +- embassy-stm32/src/pac/stm32f412zg.rs | 57 +- embassy-stm32/src/pac/stm32f413cg.rs | 59 +- embassy-stm32/src/pac/stm32f413ch.rs | 59 +- embassy-stm32/src/pac/stm32f413mg.rs | 60 +- embassy-stm32/src/pac/stm32f413mh.rs | 60 +- embassy-stm32/src/pac/stm32f413rg.rs | 60 +- embassy-stm32/src/pac/stm32f413rh.rs | 60 +- embassy-stm32/src/pac/stm32f413vg.rs | 60 +- embassy-stm32/src/pac/stm32f413vh.rs | 60 +- embassy-stm32/src/pac/stm32f413zg.rs | 60 +- embassy-stm32/src/pac/stm32f413zh.rs | 60 +- embassy-stm32/src/pac/stm32f415og.rs | 32 +- embassy-stm32/src/pac/stm32f415rg.rs | 32 +- embassy-stm32/src/pac/stm32f415vg.rs | 32 +- embassy-stm32/src/pac/stm32f415zg.rs | 32 +- embassy-stm32/src/pac/stm32f417ie.rs | 32 +- embassy-stm32/src/pac/stm32f417ig.rs | 32 +- embassy-stm32/src/pac/stm32f417ve.rs | 32 +- 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embassy-stm32/src/pac/stm32f429ig.rs | 55 +- embassy-stm32/src/pac/stm32f429ii.rs | 55 +- embassy-stm32/src/pac/stm32f429ne.rs | 55 +- embassy-stm32/src/pac/stm32f429ng.rs | 55 +- embassy-stm32/src/pac/stm32f429ni.rs | 55 +- embassy-stm32/src/pac/stm32f429ve.rs | 42 +- embassy-stm32/src/pac/stm32f429vg.rs | 42 +- embassy-stm32/src/pac/stm32f429vi.rs | 42 +- embassy-stm32/src/pac/stm32f429ze.rs | 55 +- embassy-stm32/src/pac/stm32f429zg.rs | 55 +- embassy-stm32/src/pac/stm32f429zi.rs | 55 +- embassy-stm32/src/pac/stm32f437ai.rs | 50 +- embassy-stm32/src/pac/stm32f437ig.rs | 55 +- embassy-stm32/src/pac/stm32f437ii.rs | 55 +- embassy-stm32/src/pac/stm32f437vg.rs | 42 +- embassy-stm32/src/pac/stm32f437vi.rs | 42 +- embassy-stm32/src/pac/stm32f437zg.rs | 55 +- embassy-stm32/src/pac/stm32f437zi.rs | 55 +- embassy-stm32/src/pac/stm32f439ai.rs | 50 +- embassy-stm32/src/pac/stm32f439bg.rs | 55 +- embassy-stm32/src/pac/stm32f439bi.rs | 55 +- embassy-stm32/src/pac/stm32f439ig.rs | 55 +- embassy-stm32/src/pac/stm32f439ii.rs | 55 +- embassy-stm32/src/pac/stm32f439ng.rs | 55 +- embassy-stm32/src/pac/stm32f439ni.rs | 55 +- embassy-stm32/src/pac/stm32f439vg.rs | 42 +- embassy-stm32/src/pac/stm32f439vi.rs | 42 +- embassy-stm32/src/pac/stm32f439zg.rs | 55 +- embassy-stm32/src/pac/stm32f439zi.rs | 55 +- embassy-stm32/src/pac/stm32f446mc.rs | 48 +- embassy-stm32/src/pac/stm32f446me.rs | 48 +- embassy-stm32/src/pac/stm32f446rc.rs | 36 +- embassy-stm32/src/pac/stm32f446re.rs | 36 +- embassy-stm32/src/pac/stm32f446vc.rs | 48 +- embassy-stm32/src/pac/stm32f446ve.rs | 48 +- embassy-stm32/src/pac/stm32f446zc.rs | 48 +- embassy-stm32/src/pac/stm32f446ze.rs | 48 +- embassy-stm32/src/pac/stm32f469ae.rs | 2 +- embassy-stm32/src/pac/stm32f469ag.rs | 2 +- embassy-stm32/src/pac/stm32f469ai.rs | 2 +- embassy-stm32/src/pac/stm32f469be.rs | 2 +- embassy-stm32/src/pac/stm32f469bg.rs | 2 +- embassy-stm32/src/pac/stm32f469bi.rs | 2 +- embassy-stm32/src/pac/stm32f469ie.rs | 2 +- embassy-stm32/src/pac/stm32f469ig.rs | 2 +- embassy-stm32/src/pac/stm32f469ii.rs | 2 +- embassy-stm32/src/pac/stm32f469ne.rs | 2 +- embassy-stm32/src/pac/stm32f469ng.rs | 2 +- embassy-stm32/src/pac/stm32f469ni.rs | 2 +- embassy-stm32/src/pac/stm32f469ve.rs | 2 +- embassy-stm32/src/pac/stm32f469vg.rs | 2 +- embassy-stm32/src/pac/stm32f469vi.rs | 2 +- embassy-stm32/src/pac/stm32f469ze.rs | 2 +- embassy-stm32/src/pac/stm32f469zg.rs | 2 +- embassy-stm32/src/pac/stm32f469zi.rs | 2 +- embassy-stm32/src/pac/stm32f479ag.rs | 2 +- embassy-stm32/src/pac/stm32f479ai.rs | 2 +- embassy-stm32/src/pac/stm32f479bg.rs | 2 +- embassy-stm32/src/pac/stm32f479bi.rs | 2 +- embassy-stm32/src/pac/stm32f479ig.rs | 2 +- embassy-stm32/src/pac/stm32f479ii.rs | 2 +- embassy-stm32/src/pac/stm32f479ng.rs | 2 +- embassy-stm32/src/pac/stm32f479ni.rs | 2 +- embassy-stm32/src/pac/stm32f479vg.rs | 2 +- embassy-stm32/src/pac/stm32f479vi.rs | 2 +- embassy-stm32/src/pac/stm32f479zg.rs | 2 +- embassy-stm32/src/pac/stm32f479zi.rs | 2 +- embassy-stm32/src/pac/stm32l412c8.rs | 2 +- embassy-stm32/src/pac/stm32l412cb.rs | 2 +- embassy-stm32/src/pac/stm32l412k8.rs | 2 +- embassy-stm32/src/pac/stm32l412kb.rs | 2 +- embassy-stm32/src/pac/stm32l412r8.rs | 2 +- embassy-stm32/src/pac/stm32l412rb.rs | 2 +- embassy-stm32/src/pac/stm32l412t8.rs | 2 +- embassy-stm32/src/pac/stm32l412tb.rs | 2 +- embassy-stm32/src/pac/stm32l422cb.rs | 2 +- embassy-stm32/src/pac/stm32l422kb.rs | 2 +- embassy-stm32/src/pac/stm32l422rb.rs | 2 +- embassy-stm32/src/pac/stm32l422tb.rs | 2 +- embassy-stm32/src/pac/stm32l431cb.rs | 2 +- embassy-stm32/src/pac/stm32l431cc.rs | 2 +- embassy-stm32/src/pac/stm32l431kb.rs | 2 +- embassy-stm32/src/pac/stm32l431kc.rs | 2 +- embassy-stm32/src/pac/stm32l431rb.rs | 2 +- embassy-stm32/src/pac/stm32l431rc.rs | 2 +- embassy-stm32/src/pac/stm32l431vc.rs | 2 +- embassy-stm32/src/pac/stm32l432kb.rs | 2 +- embassy-stm32/src/pac/stm32l432kc.rs | 2 +- embassy-stm32/src/pac/stm32l433cb.rs | 2 +- embassy-stm32/src/pac/stm32l433cc.rs | 2 +- embassy-stm32/src/pac/stm32l433rb.rs | 2 +- embassy-stm32/src/pac/stm32l433rc.rs | 2 +- embassy-stm32/src/pac/stm32l433vc.rs | 2 +- embassy-stm32/src/pac/stm32l442kc.rs | 2 +- embassy-stm32/src/pac/stm32l443cc.rs | 2 +- embassy-stm32/src/pac/stm32l443rc.rs | 2 +- embassy-stm32/src/pac/stm32l443vc.rs | 2 +- embassy-stm32/src/pac/stm32l451cc.rs | 2 +- embassy-stm32/src/pac/stm32l451ce.rs | 2 +- embassy-stm32/src/pac/stm32l451rc.rs | 2 +- embassy-stm32/src/pac/stm32l451re.rs | 2 +- embassy-stm32/src/pac/stm32l451vc.rs | 2 +- embassy-stm32/src/pac/stm32l451ve.rs | 2 +- embassy-stm32/src/pac/stm32l452cc.rs | 2 +- embassy-stm32/src/pac/stm32l452ce.rs | 2 +- embassy-stm32/src/pac/stm32l452rc.rs | 2 +- embassy-stm32/src/pac/stm32l452re.rs | 2 +- embassy-stm32/src/pac/stm32l452vc.rs | 2 +- embassy-stm32/src/pac/stm32l452ve.rs | 2 +- embassy-stm32/src/pac/stm32l462ce.rs | 2 +- embassy-stm32/src/pac/stm32l462re.rs | 2 +- embassy-stm32/src/pac/stm32l462ve.rs | 2 +- embassy-stm32/src/pac/stm32l471qe.rs | 2 +- embassy-stm32/src/pac/stm32l471qg.rs | 2 +- embassy-stm32/src/pac/stm32l471re.rs | 2 +- embassy-stm32/src/pac/stm32l471rg.rs | 2 +- embassy-stm32/src/pac/stm32l471ve.rs | 2 +- embassy-stm32/src/pac/stm32l471vg.rs | 2 +- embassy-stm32/src/pac/stm32l471ze.rs | 2 +- embassy-stm32/src/pac/stm32l471zg.rs | 2 +- embassy-stm32/src/pac/stm32l475rc.rs | 2 +- embassy-stm32/src/pac/stm32l475re.rs | 2 +- embassy-stm32/src/pac/stm32l475rg.rs | 2 +- embassy-stm32/src/pac/stm32l475vc.rs | 2 +- embassy-stm32/src/pac/stm32l475ve.rs | 2 +- embassy-stm32/src/pac/stm32l475vg.rs | 2 +- embassy-stm32/src/pac/stm32l476je.rs | 2 +- embassy-stm32/src/pac/stm32l476jg.rs | 2 +- embassy-stm32/src/pac/stm32l476me.rs | 2 +- embassy-stm32/src/pac/stm32l476mg.rs | 2 +- embassy-stm32/src/pac/stm32l476qe.rs | 2 +- embassy-stm32/src/pac/stm32l476qg.rs | 2 +- embassy-stm32/src/pac/stm32l476rc.rs | 2 +- embassy-stm32/src/pac/stm32l476re.rs | 2 +- embassy-stm32/src/pac/stm32l476rg.rs | 2 +- embassy-stm32/src/pac/stm32l476vc.rs | 2 +- embassy-stm32/src/pac/stm32l476ve.rs | 2 +- embassy-stm32/src/pac/stm32l476vg.rs | 2 +- embassy-stm32/src/pac/stm32l476ze.rs | 2 +- embassy-stm32/src/pac/stm32l476zg.rs | 2 +- embassy-stm32/src/pac/stm32l485jc.rs | 2 +- embassy-stm32/src/pac/stm32l485je.rs | 2 +- embassy-stm32/src/pac/stm32l486jg.rs | 2 +- embassy-stm32/src/pac/stm32l486qg.rs | 2 +- embassy-stm32/src/pac/stm32l486rg.rs | 2 +- embassy-stm32/src/pac/stm32l486vg.rs | 2 +- embassy-stm32/src/pac/stm32l486zg.rs | 2 +- embassy-stm32/src/pac/stm32l496ae.rs | 2 +- embassy-stm32/src/pac/stm32l496ag.rs | 2 +- embassy-stm32/src/pac/stm32l496qe.rs | 2 +- embassy-stm32/src/pac/stm32l496qg.rs | 2 +- embassy-stm32/src/pac/stm32l496re.rs | 2 +- embassy-stm32/src/pac/stm32l496rg.rs | 2 +- embassy-stm32/src/pac/stm32l496ve.rs | 2 +- embassy-stm32/src/pac/stm32l496vg.rs | 2 +- embassy-stm32/src/pac/stm32l496wg.rs | 2 +- embassy-stm32/src/pac/stm32l496ze.rs | 2 +- embassy-stm32/src/pac/stm32l496zg.rs | 2 +- embassy-stm32/src/pac/stm32l4a6ag.rs | 2 +- embassy-stm32/src/pac/stm32l4a6qg.rs | 2 +- embassy-stm32/src/pac/stm32l4a6rg.rs | 2 +- embassy-stm32/src/pac/stm32l4a6vg.rs | 2 +- embassy-stm32/src/pac/stm32l4a6zg.rs | 2 +- embassy-stm32/src/pac/stm32l4p5ae.rs | 2 +- embassy-stm32/src/pac/stm32l4p5ag.rs | 2 +- embassy-stm32/src/pac/stm32l4p5ce.rs | 2 +- embassy-stm32/src/pac/stm32l4p5cg.rs | 2 +- embassy-stm32/src/pac/stm32l4p5qe.rs | 2 +- embassy-stm32/src/pac/stm32l4p5qg.rs | 2 +- embassy-stm32/src/pac/stm32l4p5re.rs | 2 +- embassy-stm32/src/pac/stm32l4p5rg.rs | 2 +- embassy-stm32/src/pac/stm32l4p5ve.rs | 2 +- embassy-stm32/src/pac/stm32l4p5vg.rs | 2 +- embassy-stm32/src/pac/stm32l4p5ze.rs | 2 +- embassy-stm32/src/pac/stm32l4p5zg.rs | 2 +- embassy-stm32/src/pac/stm32l4q5ag.rs | 2 +- embassy-stm32/src/pac/stm32l4q5cg.rs | 2 +- embassy-stm32/src/pac/stm32l4q5qg.rs | 2 +- embassy-stm32/src/pac/stm32l4q5rg.rs | 2 +- embassy-stm32/src/pac/stm32l4q5vg.rs | 2 +- embassy-stm32/src/pac/stm32l4q5zg.rs | 2 +- embassy-stm32/src/pac/stm32l4r5ag.rs | 2 +- embassy-stm32/src/pac/stm32l4r5ai.rs | 2 +- embassy-stm32/src/pac/stm32l4r5qg.rs | 2 +- embassy-stm32/src/pac/stm32l4r5qi.rs | 2 +- embassy-stm32/src/pac/stm32l4r5vg.rs | 2 +- embassy-stm32/src/pac/stm32l4r5vi.rs | 2 +- embassy-stm32/src/pac/stm32l4r5zg.rs | 2 +- embassy-stm32/src/pac/stm32l4r5zi.rs | 2 +- embassy-stm32/src/pac/stm32l4r7ai.rs | 2 +- embassy-stm32/src/pac/stm32l4r7vi.rs | 2 +- embassy-stm32/src/pac/stm32l4r7zi.rs | 2 +- embassy-stm32/src/pac/stm32l4r9ag.rs | 2 +- embassy-stm32/src/pac/stm32l4r9ai.rs | 2 +- embassy-stm32/src/pac/stm32l4r9vg.rs | 2 +- embassy-stm32/src/pac/stm32l4r9vi.rs | 2 +- embassy-stm32/src/pac/stm32l4r9zg.rs | 2 +- embassy-stm32/src/pac/stm32l4r9zi.rs | 2 +- embassy-stm32/src/pac/stm32l4s5ai.rs | 2 +- embassy-stm32/src/pac/stm32l4s5qi.rs | 2 +- embassy-stm32/src/pac/stm32l4s5vi.rs | 2 +- embassy-stm32/src/pac/stm32l4s5zi.rs | 2 +- embassy-stm32/src/pac/stm32l4s7ai.rs | 2 +- embassy-stm32/src/pac/stm32l4s7vi.rs | 2 +- embassy-stm32/src/pac/stm32l4s7zi.rs | 2 +- embassy-stm32/src/pac/stm32l4s9ai.rs | 2 +- embassy-stm32/src/pac/stm32l4s9vi.rs | 2 +- embassy-stm32/src/pac/stm32l4s9zi.rs | 2 +- embassy-stm32/src/rng.rs | 24 +- embassy-stm32/src/spi/mod.rs | 34 + embassy-stm32/src/spi/spi_v1.rs | 364 + embassy-stm32/src/{spi.rs => spi/spi_v2.rs} | 29 +- 299 files changed, 14196 insertions(+), 8867 deletions(-) create mode 100644 embassy-stm32-examples/src/bin/spi.rs create mode 100644 embassy-stm32/src/spi/mod.rs create mode 100644 embassy-stm32/src/spi/spi_v1.rs rename embassy-stm32/src/{spi.rs => spi/spi_v2.rs} (95%) diff --git a/embassy-stm32-examples/src/bin/spi.rs b/embassy-stm32-examples/src/bin/spi.rs new file mode 100644 index 00000000..308c1c68 --- /dev/null +++ b/embassy-stm32-examples/src/bin/spi.rs @@ -0,0 +1,94 @@ +#![no_std] +#![no_main] +#![feature(trait_alias)] +#![feature(min_type_alias_impl_trait)] +#![feature(impl_trait_in_bindings)] +#![feature(type_alias_impl_trait)] + +#[path = "../example_common.rs"] +mod example_common; + +use embassy_stm32::gpio::{Level, Output, Input, Pull}; +use embedded_hal::digital::v2::{OutputPin, InputPin}; +use example_common::*; + +use cortex_m_rt::entry; +use stm32f4::stm32f429 as pac; +//use stm32l4::stm32l4x5 as pac; +use embassy_stm32::spi::{Spi, MODE_0, ByteOrder, Config}; +use embassy_stm32::time::Hertz; +use embedded_hal::blocking::spi::Transfer; + +#[entry] +fn main() -> ! { + info!("Hello World, dude!"); + + let pp = pac::Peripherals::take().unwrap(); + + pp.DBGMCU.cr.modify(|_, w| { + w.dbg_sleep().set_bit(); + w.dbg_standby().set_bit(); + w.dbg_stop().set_bit() + }); + pp.RCC.ahb1enr.modify(|_, w| w.dma1en().set_bit()); + + pp.RCC.apb1enr.modify(|_, w| { + w.spi3en().enabled(); + w + }); + + pp.RCC.ahb1enr.modify(|_, w| { + w.gpioaen().enabled(); + w.gpioben().enabled(); + w.gpiocen().enabled(); + w.gpioden().enabled(); + w.gpioeen().enabled(); + w.gpiofen().enabled(); + w + }); + + let rc = pp.RCC.cfgr.read().sws().bits(); + info!("rcc -> {}", rc); + let p = embassy_stm32::init(Default::default()); + + let mut led = Output::new(p.PA5, Level::High); + let mut spi = Spi::new( + Hertz(16_000_000), + p.SPI3, + p.PC10, + p.PC12, + p.PC11, + Hertz(1_000_000), + Config::default(), + ); + + let mut cs = Output::new( p.PE0, Level::High); + cs.set_low(); + + let mut rdy = Input::new(p.PE1, Pull::Down); + let mut wake = Output::new( p.PB13, Level::Low); + let mut reset = Output::new( p.PE8, Level::Low); + + wake.set_high().unwrap(); + reset.set_high().unwrap(); + + loop { + info!("loop"); + while rdy.is_low().unwrap() { + info!("await ready") + } + info!("ready"); + let mut buf = [0x0A;4]; + spi.transfer(&mut buf); + info!("xfer {=[u8]:x}", buf); + } + + loop { + info!("high"); + led.set_high().unwrap(); + cortex_m::asm::delay(10_000_000); + info!("low"); + led.set_low().unwrap(); + cortex_m::asm::delay(10_000_000); + } +} diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml index cd940c58..f4f5b085 100644 --- a/embassy-stm32/Cargo.toml +++ b/embassy-stm32/Cargo.toml @@ -28,125 +28,125 @@ defmt-warn = [ ] defmt-error = [ ] # BEGIN GENERATED FEATURES -stm32f401cb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f401cc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f401cd = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f401ce = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f401rb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f401rc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f401rd = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f401re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f401vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f401vc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f401vd = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f401ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f405oe = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f405og = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f405rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f405vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f405zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f407ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f407ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f407ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f407vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f407ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f407zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401cb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401cc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401cd = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401ce = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401rb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401rc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401rd = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401vc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401vd = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f405oe = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f405og = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f405rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f405vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f405zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f407ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f407ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f407ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f407vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f407ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f407zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] stm32f410c8 = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] stm32f410cb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] stm32f410r8 = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] stm32f410rb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] stm32f410t8 = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] stm32f410tb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f411cc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f411ce = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f411rc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f411re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f411vc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f411ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f412ce = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f412cg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f412re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f412rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f412ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f412vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f412ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f412zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f413cg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f413ch = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f413mg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f413mh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f413rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f413rh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f413vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f413vh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f413zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f413zh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f415og = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f415rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f415vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f415zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f417ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f417ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f417ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f417vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f417ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f417zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f423ch = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f423mh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f423rh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f423vh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f423zh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f427ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f427ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f427ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f427ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f427vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f427vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f427zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f427zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429be = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429ne = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f429zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f437ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f437ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f437ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f437vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f437vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f437zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f437zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f439ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f439bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f439bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f439ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f439ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f439ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f439ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f439vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f439vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f439zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f439zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f446mc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f446me = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f446rc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f446re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f446vc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f446ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f446zc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] -stm32f446ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f411cc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f411ce = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f411rc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f411re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f411vc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f411ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f412ce = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f412cg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f412re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f412rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f412ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f412vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f412ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f412zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413cg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413ch = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413mg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413mh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413rh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413vh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413zh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f415og = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f415rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f415vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f415zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f417ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f417ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f417ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f417vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f417ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f417zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f423ch = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f423mh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f423rh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f423vh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f423zh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f427ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f427ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f427ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f427ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f427vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f427vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f427zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f427zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429be = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ne = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f437ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f437ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f437ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f437vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f437vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f437zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f437zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f446mc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f446me = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f446rc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f446re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f446vc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f446ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f446zc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f446ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] stm32f469ae = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] stm32f469ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] stm32f469ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] @@ -328,6 +328,7 @@ _gpio_v2 = [] _rng = [ "rand_core",] _rng_v1 = [] _spi = [] +_spi_v1 = [] _spi_v2 = [] _stm32f4 = [] _stm32l4 = [] diff --git a/embassy-stm32/gen.py b/embassy-stm32/gen.py index 3f3fe569..04a2f333 100644 --- a/embassy-stm32/gen.py +++ b/embassy-stm32/gen.py @@ -113,7 +113,10 @@ for chip in chips.values(): f.write(f'impl_usart_pin!({name}, CkPin, {pin}, {func});') if block_mod == 'rng': - f.write(f'impl_rng!({name});') + if 'RNG' in chip['interrupts']: + f.write(f'impl_rng!({name}, RNG);') + else: + f.write(f'impl_rng!({name}, HASH_RNG);') if block_mod == 'spi': clock = peri['clock'] diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs index 3d8416c7..f14dbfae 100644 --- a/embassy-stm32/src/lib.rs +++ b/embassy-stm32/src/lib.rs @@ -17,6 +17,7 @@ pub mod exti; pub mod gpio; #[cfg(feature = "_rng")] pub mod rng; +#[cfg(feature = "_spi")] pub mod spi; #[cfg(feature = "_usart")] pub mod usart; diff --git a/embassy-stm32/src/pac/regs.rs b/embassy-stm32/src/pac/regs.rs index fa31704d..26378413 100644 --- a/embassy-stm32/src/pac/regs.rs +++ b/embassy-stm32/src/pac/regs.rs @@ -1,5 +1,5815 @@ #![no_std] #![doc = "Peripheral access API (generated using svd2rust v0.17.0 (22741fa 2021-04-20))"] +pub mod sdmmc_v2 { + use crate::generic::*; + #[doc = "SDMMC"] + #[derive(Copy, Clone)] + pub struct Sdmmc(pub *mut u8); + unsafe impl Send for Sdmmc {} + unsafe impl Sync for Sdmmc {} + impl Sdmmc { + #[doc = "SDMMC power control register"] + pub fn power(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."] + pub fn clkcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."] + pub fn argr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."] + pub fn cmdr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "SDMMC command response register"] + pub fn respcmdr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + pub fn respr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(20usize + n * 4usize)) } + } + #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."] + pub fn dtimer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."] + pub fn dlenr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."] + pub fn dctrl(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."] + pub fn dcntr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(48usize)) } + } + #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"] + pub fn star(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(52usize)) } + } + #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."] + pub fn icr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(56usize)) } + } + #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."] + pub fn maskr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(60usize)) } + } + #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."] + pub fn acktimer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(64usize)) } + } + #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."] + pub fn idmactrlr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(80usize)) } + } + #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."] + pub fn idmabsizer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(84usize)) } + } + #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."] + pub fn idmabase0r(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(88usize)) } + } + #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."] + pub fn idmabase1r(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(92usize)) } + } + #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."] + pub fn fifor(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(128usize)) } + } + #[doc = "SDMMC IP version register"] + pub fn ver(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(1012usize)) } + } + #[doc = "SDMMC IP identification register"] + pub fn id(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(1016usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dctrl(pub u32); + impl Dctrl { + #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."] + pub const fn dten(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."] + pub fn set_dten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn dtdir(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_dtdir(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn dtmode(&self) -> u8 { + let val = (self.0 >> 2usize) & 0x03; + val as u8 + } + #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_dtmode(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize); + } + #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"] + pub const fn dblocksize(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"] + pub fn set_dblocksize(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + #[doc = "Read wait start. If this bit is set, read wait operation starts."] + pub const fn rwstart(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Read wait start. If this bit is set, read wait operation starts."] + pub fn set_rwstart(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."] + pub const fn rwstop(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."] + pub fn set_rwstop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn rwmod(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_rwmod(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."] + pub const fn sdioen(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."] + pub fn set_sdioen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn bootacken(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_bootacken(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."] + pub const fn fiforst(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."] + pub fn set_fiforst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + } + impl Default for Dctrl { + fn default() -> Dctrl { + Dctrl(0) + } + } + #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Icr(pub u32); + impl Icr { + #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] + pub const fn ccrcfailc(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] + pub fn set_ccrcfailc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] + pub const fn dcrcfailc(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] + pub fn set_dcrcfailc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] + pub const fn ctimeoutc(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] + pub fn set_ctimeoutc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] + pub const fn dtimeoutc(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] + pub fn set_dtimeoutc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] + pub const fn txunderrc(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] + pub fn set_txunderrc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] + pub const fn rxoverrc(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] + pub fn set_rxoverrc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] + pub const fn cmdrendc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] + pub fn set_cmdrendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] + pub const fn cmdsentc(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] + pub fn set_cmdsentc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] + pub const fn dataendc(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] + pub fn set_dataendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] + pub const fn dholdc(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] + pub fn set_dholdc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] + pub const fn dbckendc(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] + pub fn set_dbckendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] + pub const fn dabortc(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] + pub fn set_dabortc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] + pub const fn busyd0endc(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] + pub fn set_busyd0endc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] + pub const fn sdioitc(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] + pub fn set_sdioitc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] + pub const fn ackfailc(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] + pub fn set_ackfailc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] + pub const fn acktimeoutc(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] + pub fn set_acktimeoutc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] + pub const fn vswendc(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] + pub fn set_vswendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] + pub const fn ckstopc(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] + pub fn set_ckstopc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] + pub const fn idmatec(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] + pub fn set_idmatec(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] + pub const fn idmabtcc(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] + pub fn set_idmabtcc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + } + impl Default for Icr { + fn default() -> Icr { + Icr(0) + } + } + #[doc = "SDMMC IP identification register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Id(pub u32); + impl Id { + #[doc = "SDMMC IP identification."] + pub const fn ip_id(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "SDMMC IP identification."] + pub fn set_ip_id(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Id { + fn default() -> Id { + Id(0) + } + } + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Resp2r(pub u32); + impl Resp2r { + #[doc = "see Table404."] + pub const fn cardstatus2(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "see Table404."] + pub fn set_cardstatus2(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Resp2r { + fn default() -> Resp2r { + Resp2r(0) + } + } + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Resp1r(pub u32); + impl Resp1r { + #[doc = "see Table 432"] + pub const fn cardstatus1(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "see Table 432"] + pub fn set_cardstatus1(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Resp1r { + fn default() -> Resp1r { + Resp1r(0) + } + } + #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Argr(pub u32); + impl Argr { + #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] + pub const fn cmdarg(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] + pub fn set_cmdarg(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Argr { + fn default() -> Argr { + Argr(0) + } + } + #[doc = "SDMMC IP version register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ver(pub u32); + impl Ver { + #[doc = "IP minor revision number."] + pub const fn minrev(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "IP minor revision number."] + pub fn set_minrev(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "IP major revision number."] + pub const fn majrev(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "IP major revision number."] + pub fn set_majrev(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + } + impl Default for Ver { + fn default() -> Ver { + Ver(0) + } + } + #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idmactrlr(pub u32); + impl Idmactrlr { + #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn idmaen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_idmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn idmabmode(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_idmabmode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."] + pub const fn idmabact(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."] + pub fn set_idmabact(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + } + impl Default for Idmactrlr { + fn default() -> Idmactrlr { + Idmactrlr(0) + } + } + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Resp4r(pub u32); + impl Resp4r { + #[doc = "see Table404."] + pub const fn cardstatus4(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "see Table404."] + pub fn set_cardstatus4(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Resp4r { + fn default() -> Resp4r { + Resp4r(0) + } + } + #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cmdr(pub u32); + impl Cmdr { + #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."] + pub const fn cmdindex(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x3f; + val as u8 + } + #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."] + pub fn set_cmdindex(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); + } + #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."] + pub const fn cmdtrans(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."] + pub fn set_cmdtrans(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."] + pub const fn cmdstop(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."] + pub fn set_cmdstop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."] + pub const fn waitresp(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x03; + val as u8 + } + #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."] + pub fn set_waitresp(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); + } + #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."] + pub const fn waitint(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."] + pub fn set_waitint(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."] + pub const fn waitpend(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."] + pub fn set_waitpend(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."] + pub const fn cpsmen(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."] + pub fn set_cpsmen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."] + pub const fn dthold(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."] + pub fn set_dthold(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"] + pub const fn bootmode(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"] + pub fn set_bootmode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Enable boot mode procedure."] + pub const fn booten(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Enable boot mode procedure."] + pub fn set_booten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."] + pub const fn cmdsuspend(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."] + pub fn set_cmdsuspend(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Cmdr { + fn default() -> Cmdr { + Cmdr(0) + } + } + #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Maskr(pub u32); + impl Maskr { + #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."] + pub const fn ccrcfailie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."] + pub fn set_ccrcfailie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."] + pub const fn dcrcfailie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."] + pub fn set_dcrcfailie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."] + pub const fn ctimeoutie(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."] + pub fn set_ctimeoutie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."] + pub const fn dtimeoutie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."] + pub fn set_dtimeoutie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."] + pub const fn txunderrie(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."] + pub fn set_txunderrie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."] + pub const fn rxoverrie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."] + pub fn set_rxoverrie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."] + pub const fn cmdrendie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."] + pub fn set_cmdrendie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."] + pub const fn cmdsentie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."] + pub fn set_cmdsentie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."] + pub const fn dataendie(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."] + pub fn set_dataendie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."] + pub const fn dholdie(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."] + pub fn set_dholdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."] + pub const fn dbckendie(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."] + pub fn set_dbckendie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."] + pub const fn dabortie(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."] + pub fn set_dabortie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."] + pub const fn txfifoheie(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."] + pub fn set_txfifoheie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."] + pub const fn rxfifohfie(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."] + pub fn set_rxfifohfie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."] + pub const fn rxfifofie(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."] + pub fn set_rxfifofie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."] + pub const fn txfifoeie(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."] + pub fn set_txfifoeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."] + pub const fn busyd0endie(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."] + pub fn set_busyd0endie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."] + pub const fn sdioitie(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."] + pub fn set_sdioitie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."] + pub const fn ackfailie(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."] + pub fn set_ackfailie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."] + pub const fn acktimeoutie(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."] + pub fn set_acktimeoutie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."] + pub const fn vswendie(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."] + pub fn set_vswendie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."] + pub const fn ckstopie(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."] + pub fn set_ckstopie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."] + pub const fn idmabtcie(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."] + pub fn set_idmabtcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + } + impl Default for Maskr { + fn default() -> Maskr { + Maskr(0) + } + } + #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idmabase1r(pub u32); + impl Idmabase1r { + #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] + pub const fn idmabase1(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] + pub fn set_idmabase1(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Idmabase1r { + fn default() -> Idmabase1r { + Idmabase1r(0) + } + } + #[doc = "SDMMC power control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Power(pub u32); + impl Power { + #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."] + pub const fn pwrctrl(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x03; + val as u8 + } + #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."] + pub fn set_pwrctrl(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); + } + #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"] + pub const fn vswitch(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"] + pub fn set_vswitch(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"] + pub const fn vswitchen(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"] + pub fn set_vswitchen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."] + pub const fn dirpol(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."] + pub fn set_dirpol(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + } + impl Default for Power { + fn default() -> Power { + Power(0) + } + } + #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Acktimer(pub u32); + impl Acktimer { + #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] + pub const fn acktime(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x01ff_ffff; + val as u32 + } + #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] + pub fn set_acktime(&mut self, val: u32) { + self.0 = + (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); + } + } + impl Default for Acktimer { + fn default() -> Acktimer { + Acktimer(0) + } + } + #[doc = "SDMMC command response register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Respcmdr(pub u32); + impl Respcmdr { + #[doc = "Response command index"] + pub const fn respcmd(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x3f; + val as u8 + } + #[doc = "Response command index"] + pub fn set_respcmd(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); + } + } + impl Default for Respcmdr { + fn default() -> Respcmdr { + Respcmdr(0) + } + } + #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Fifor(pub u32); + impl Fifor { + #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] + pub const fn fifodata(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] + pub fn set_fifodata(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Fifor { + fn default() -> Fifor { + Fifor(0) + } + } + #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dlenr(pub u32); + impl Dlenr { + #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."] + pub const fn datalength(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x01ff_ffff; + val as u32 + } + #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."] + pub fn set_datalength(&mut self, val: u32) { + self.0 = + (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); + } + } + impl Default for Dlenr { + fn default() -> Dlenr { + Dlenr(0) + } + } + #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idmabsizer(pub u32); + impl Idmabsizer { + #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn idmabndt(&self) -> u8 { + let val = (self.0 >> 5usize) & 0xff; + val as u8 + } + #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_idmabndt(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 5usize)) | (((val as u32) & 0xff) << 5usize); + } + } + impl Default for Idmabsizer { + fn default() -> Idmabsizer { + Idmabsizer(0) + } + } + #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Star(pub u32); + impl Star { + #[doc = "Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn ccrcfail(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_ccrcfail(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn dcrcfail(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_dcrcfail(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods."] + pub const fn ctimeout(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods."] + pub fn set_ctimeout(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn dtimeout(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_dtimeout(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn txunderr(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_txunderr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn rxoverr(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_rxoverr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn cmdrend(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_cmdrend(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn cmdsent(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_cmdsent(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn dataend(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_dataend(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn dhold(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_dhold(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn dbckend(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_dbckend(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn dabort(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_dabort(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt."] + pub const fn dpsmact(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt."] + pub fn set_dpsmact(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt."] + pub const fn cpsmact(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt."] + pub fn set_cpsmact(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full."] + pub const fn txfifohe(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full."] + pub fn set_txfifohe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty."] + pub const fn rxfifohf(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty."] + pub fn set_rxfifohf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty."] + pub const fn txfifof(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty."] + pub fn set_txfifof(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Receive FIFO full This bit is cleared when one FIFO location becomes empty."] + pub const fn rxfifof(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Receive FIFO full This bit is cleared when one FIFO location becomes empty."] + pub fn set_rxfifof(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Transmit FIFO empty This bit is cleared when one FIFO location becomes full."] + pub const fn txfifoe(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Transmit FIFO empty This bit is cleared when one FIFO location becomes full."] + pub fn set_txfifoe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full."] + pub const fn rxfifoe(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full."] + pub fn set_rxfifoe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt."] + pub const fn busyd0(&self) -> bool { + let val = (self.0 >> 20usize) & 0x01; + val != 0 + } + #[doc = "Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt."] + pub fn set_busyd0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); + } + #[doc = "end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn busyd0end(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_busyd0end(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn sdioit(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_sdioit(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn ackfail(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_ackfail(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn acktimeout(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_acktimeout(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn vswend(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_vswend(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn ckstop(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_ckstop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn idmate(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_idmate(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + #[doc = "IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn idmabtc(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_idmabtc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + } + impl Default for Star { + fn default() -> Star { + Star(0) + } + } + #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Clkcr(pub u32); + impl Clkcr { + #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] + pub const fn clkdiv(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x03ff; + val as u16 + } + #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] + pub fn set_clkdiv(&mut self, val: u16) { + self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize); + } + #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] + pub const fn pwrsav(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] + pub fn set_pwrsav(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub const fn widbus(&self) -> u8 { + let val = (self.0 >> 14usize) & 0x03; + val as u8 + } + #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub fn set_widbus(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize); + } + #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] + pub const fn negedge(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] + pub fn set_negedge(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] + pub const fn hwfc_en(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] + pub fn set_hwfc_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] + pub const fn ddr(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] + pub fn set_ddr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub const fn busspeed(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub fn set_busspeed(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub const fn selclkrx(&self) -> u8 { + let val = (self.0 >> 20usize) & 0x03; + val as u8 + } + #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub fn set_selclkrx(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize); + } + } + impl Default for Clkcr { + fn default() -> Clkcr { + Clkcr(0) + } + } + #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idmabase0r(pub u32); + impl Idmabase0r { + #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."] + pub const fn idmabase0(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."] + pub fn set_idmabase0(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Idmabase0r { + fn default() -> Idmabase0r { + Idmabase0r(0) + } + } + #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dcntr(pub u32); + impl Dcntr { + #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] + pub const fn datacount(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x01ff_ffff; + val as u32 + } + #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] + pub fn set_datacount(&mut self, val: u32) { + self.0 = + (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); + } + } + impl Default for Dcntr { + fn default() -> Dcntr { + Dcntr(0) + } + } + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Resp3r(pub u32); + impl Resp3r { + #[doc = "see Table404."] + pub const fn cardstatus3(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "see Table404."] + pub fn set_cardstatus3(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Resp3r { + fn default() -> Resp3r { + Resp3r(0) + } + } + #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dtimer(pub u32); + impl Dtimer { + #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] + pub const fn datatime(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] + pub fn set_datatime(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Dtimer { + fn default() -> Dtimer { + Dtimer(0) + } + } + } +} +pub mod timer_v1 { + use crate::generic::*; + #[doc = "General purpose 32-bit timer"] + #[derive(Copy, Clone)] + pub struct TimGp32(pub *mut u8); + unsafe impl Send for TimGp32 {} + unsafe impl Sync for TimGp32 {} + impl TimGp32 { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "slave mode control register"] + pub fn smcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "capture/compare mode register 1 (input mode)"] + pub fn ccmr_input(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare mode register 1 (output mode)"] + pub fn ccmr_output(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare enable register"] + pub fn ccer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "capture/compare register"] + pub fn ccr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } + } + #[doc = "DMA control register"] + pub fn dcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(72usize)) } + } + #[doc = "DMA address for full transfer"] + pub fn dmar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(76usize)) } + } + } + #[doc = "Basic timer"] + #[derive(Copy, Clone)] + pub struct TimBasic(pub *mut u8); + unsafe impl Send for TimBasic {} + unsafe impl Sync for TimBasic {} + impl TimBasic { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + } + #[doc = "General purpose 16-bit timer"] + #[derive(Copy, Clone)] + pub struct TimGp16(pub *mut u8); + unsafe impl Send for TimGp16 {} + unsafe impl Sync for TimGp16 {} + impl TimGp16 { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "slave mode control register"] + pub fn smcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "capture/compare mode register 1 (input mode)"] + pub fn ccmr_input(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare mode register 1 (output mode)"] + pub fn ccmr_output(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare enable register"] + pub fn ccer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "capture/compare register"] + pub fn ccr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } + } + #[doc = "DMA control register"] + pub fn dcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(72usize)) } + } + #[doc = "DMA address for full transfer"] + pub fn dmar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(76usize)) } + } + } + #[doc = "Advanced-timers"] + #[derive(Copy, Clone)] + pub struct TimAdv(pub *mut u8); + unsafe impl Send for TimAdv {} + unsafe impl Sync for TimAdv {} + impl TimAdv { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "slave mode control register"] + pub fn smcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "capture/compare mode register 1 (input mode)"] + pub fn ccmr_input(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare mode register 1 (output mode)"] + pub fn ccmr_output(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare enable register"] + pub fn ccer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "repetition counter register"] + pub fn rcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(48usize)) } + } + #[doc = "capture/compare register"] + pub fn ccr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } + } + #[doc = "break and dead-time register"] + pub fn bdtr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(68usize)) } + } + #[doc = "DMA control register"] + pub fn dcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(72usize)) } + } + #[doc = "DMA address for full transfer"] + pub fn dmar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(76usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Gp(pub u32); + impl Cr2Gp { + #[doc = "Capture/compare DMA selection"] + pub const fn ccds(&self) -> super::vals::Ccds { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Ccds(val as u8) + } + #[doc = "Capture/compare DMA selection"] + pub fn set_ccds(&mut self, val: super::vals::Ccds) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "TI1 selection"] + pub const fn ti1s(&self) -> super::vals::Tis { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Tis(val as u8) + } + #[doc = "TI1 selection"] + pub fn set_ti1s(&mut self, val: super::vals::Tis) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + } + impl Default for Cr2Gp { + fn default() -> Cr2Gp { + Cr2Gp(0) + } + } + #[doc = "capture/compare mode register 1 (input mode)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcmrInput(pub u32); + impl CcmrInput { + #[doc = "Capture/Compare 1 selection"] + pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + super::vals::CcmrInputCcs(val as u8) + } + #[doc = "Capture/Compare 1 selection"] + pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Input capture 1 prescaler"] + pub fn icpsc(&self, n: usize) -> u8 { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + val as u8 + } + #[doc = "Input capture 1 prescaler"] + pub fn set_icpsc(&mut self, n: usize, val: u8) { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs); + } + #[doc = "Input capture 1 filter"] + pub fn icf(&self, n: usize) -> super::vals::Icf { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + let val = (self.0 >> offs) & 0x0f; + super::vals::Icf(val as u8) + } + #[doc = "Input capture 1 filter"] + pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); + } + } + impl Default for CcmrInput { + fn default() -> CcmrInput { + CcmrInput(0) + } + } + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierAdv(pub u32); + impl DierAdv { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn ccie(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn set_ccie(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt enable"] + pub const fn comie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt enable"] + pub fn set_comie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt enable"] + pub const fn tie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt enable"] + pub fn set_tie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt enable"] + pub const fn bie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break interrupt enable"] + pub fn set_bie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn ccde(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn set_ccde(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM DMA request enable"] + pub const fn comde(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "COM DMA request enable"] + pub fn set_comde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Trigger DMA request enable"] + pub const fn tde(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Trigger DMA request enable"] + pub fn set_tde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for DierAdv { + fn default() -> DierAdv { + DierAdv(0) + } + } + #[doc = "prescaler"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Psc(pub u32); + impl Psc { + #[doc = "Prescaler value"] + pub const fn psc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Prescaler value"] + pub fn set_psc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Psc { + fn default() -> Psc { + Psc(0) + } + } + #[doc = "event generation register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct EgrAdv(pub u32); + impl EgrAdv { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 generation"] + pub fn ccg(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 generation"] + pub fn set_ccg(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare control update generation"] + pub const fn comg(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Capture/Compare control update generation"] + pub fn set_comg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger generation"] + pub const fn tg(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger generation"] + pub fn set_tg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break generation"] + pub const fn bg(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break generation"] + pub fn set_bg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for EgrAdv { + fn default() -> EgrAdv { + EgrAdv(0) + } + } + #[doc = "capture/compare mode register 2 (output mode)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcmrOutput(pub u32); + impl CcmrOutput { + #[doc = "Capture/Compare 3 selection"] + pub fn ccs(&self, n: usize) -> super::vals::CcmrOutputCcs { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + super::vals::CcmrOutputCcs(val as u8) + } + #[doc = "Capture/Compare 3 selection"] + pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrOutputCcs) { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Output compare 3 fast enable"] + pub fn ocfe(&self, n: usize) -> bool { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output compare 3 fast enable"] + pub fn set_ocfe(&mut self, n: usize, val: bool) { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Output compare 3 preload enable"] + pub fn ocpe(&self, n: usize) -> super::vals::Ocpe { + assert!(n < 2usize); + let offs = 3usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Ocpe(val as u8) + } + #[doc = "Output compare 3 preload enable"] + pub fn set_ocpe(&mut self, n: usize, val: super::vals::Ocpe) { + assert!(n < 2usize); + let offs = 3usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Output compare 3 mode"] + pub fn ocm(&self, n: usize) -> super::vals::Ocm { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + let val = (self.0 >> offs) & 0x07; + super::vals::Ocm(val as u8) + } + #[doc = "Output compare 3 mode"] + pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + self.0 = (self.0 & !(0x07 << offs)) | (((val.0 as u32) & 0x07) << offs); + } + #[doc = "Output compare 3 clear enable"] + pub fn occe(&self, n: usize) -> bool { + assert!(n < 2usize); + let offs = 7usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output compare 3 clear enable"] + pub fn set_occe(&mut self, n: usize, val: bool) { + assert!(n < 2usize); + let offs = 7usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcmrOutput { + fn default() -> CcmrOutput { + CcmrOutput(0) + } + } + #[doc = "auto-reload register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Arr32(pub u32); + impl Arr32 { + #[doc = "Auto-reload value"] + pub const fn arr(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Auto-reload value"] + pub fn set_arr(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Arr32 { + fn default() -> Arr32 { + Arr32(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1Basic(pub u32); + impl Cr1Basic { + #[doc = "Counter enable"] + pub const fn cen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Counter enable"] + pub fn set_cen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update disable"] + pub const fn udis(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Update disable"] + pub fn set_udis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Update request source"] + pub const fn urs(&self) -> super::vals::Urs { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Urs(val as u8) + } + #[doc = "Update request source"] + pub fn set_urs(&mut self, val: super::vals::Urs) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "One-pulse mode"] + pub const fn opm(&self) -> super::vals::Opm { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Opm(val as u8) + } + #[doc = "One-pulse mode"] + pub fn set_opm(&mut self, val: super::vals::Opm) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Auto-reload preload enable"] + pub const fn arpe(&self) -> super::vals::Arpe { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Arpe(val as u8) + } + #[doc = "Auto-reload preload enable"] + pub fn set_arpe(&mut self, val: super::vals::Arpe) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + } + impl Default for Cr1Basic { + fn default() -> Cr1Basic { + Cr1Basic(0) + } + } + #[doc = "DMA control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dcr(pub u32); + impl Dcr { + #[doc = "DMA base address"] + pub const fn dba(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 + } + #[doc = "DMA base address"] + pub fn set_dba(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); + } + #[doc = "DMA burst length"] + pub const fn dbl(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x1f; + val as u8 + } + #[doc = "DMA burst length"] + pub fn set_dbl(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); + } + } + impl Default for Dcr { + fn default() -> Dcr { + Dcr(0) + } + } + #[doc = "slave mode control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Smcr(pub u32); + impl Smcr { + #[doc = "Slave mode selection"] + pub const fn sms(&self) -> super::vals::Sms { + let val = (self.0 >> 0usize) & 0x07; + super::vals::Sms(val as u8) + } + #[doc = "Slave mode selection"] + pub fn set_sms(&mut self, val: super::vals::Sms) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize); + } + #[doc = "Trigger selection"] + pub const fn ts(&self) -> super::vals::Ts { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Ts(val as u8) + } + #[doc = "Trigger selection"] + pub fn set_ts(&mut self, val: super::vals::Ts) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "Master/Slave mode"] + pub const fn msm(&self) -> super::vals::Msm { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Msm(val as u8) + } + #[doc = "Master/Slave mode"] + pub fn set_msm(&mut self, val: super::vals::Msm) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "External trigger filter"] + pub const fn etf(&self) -> super::vals::Etf { + let val = (self.0 >> 8usize) & 0x0f; + super::vals::Etf(val as u8) + } + #[doc = "External trigger filter"] + pub fn set_etf(&mut self, val: super::vals::Etf) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); + } + #[doc = "External trigger prescaler"] + pub const fn etps(&self) -> super::vals::Etps { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Etps(val as u8) + } + #[doc = "External trigger prescaler"] + pub fn set_etps(&mut self, val: super::vals::Etps) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "External clock enable"] + pub const fn ece(&self) -> super::vals::Ece { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Ece(val as u8) + } + #[doc = "External clock enable"] + pub fn set_ece(&mut self, val: super::vals::Ece) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + #[doc = "External trigger polarity"] + pub const fn etp(&self) -> super::vals::Etp { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Etp(val as u8) + } + #[doc = "External trigger polarity"] + pub fn set_etp(&mut self, val: super::vals::Etp) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + } + impl Default for Smcr { + fn default() -> Smcr { + Smcr(0) + } + } + #[doc = "counter"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cnt32(pub u32); + impl Cnt32 { + #[doc = "counter value"] + pub const fn cnt(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "counter value"] + pub fn set_cnt(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Cnt32 { + fn default() -> Cnt32 { + Cnt32(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1Gp(pub u32); + impl Cr1Gp { + #[doc = "Counter enable"] + pub const fn cen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Counter enable"] + pub fn set_cen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update disable"] + pub const fn udis(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Update disable"] + pub fn set_udis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Update request source"] + pub const fn urs(&self) -> super::vals::Urs { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Urs(val as u8) + } + #[doc = "Update request source"] + pub fn set_urs(&mut self, val: super::vals::Urs) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "One-pulse mode"] + pub const fn opm(&self) -> super::vals::Opm { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Opm(val as u8) + } + #[doc = "One-pulse mode"] + pub fn set_opm(&mut self, val: super::vals::Opm) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Direction"] + pub const fn dir(&self) -> super::vals::Dir { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Dir(val as u8) + } + #[doc = "Direction"] + pub fn set_dir(&mut self, val: super::vals::Dir) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Center-aligned mode selection"] + pub const fn cms(&self) -> super::vals::Cms { + let val = (self.0 >> 5usize) & 0x03; + super::vals::Cms(val as u8) + } + #[doc = "Center-aligned mode selection"] + pub fn set_cms(&mut self, val: super::vals::Cms) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize); + } + #[doc = "Auto-reload preload enable"] + pub const fn arpe(&self) -> super::vals::Arpe { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Arpe(val as u8) + } + #[doc = "Auto-reload preload enable"] + pub fn set_arpe(&mut self, val: super::vals::Arpe) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Clock division"] + pub const fn ckd(&self) -> super::vals::Ckd { + let val = (self.0 >> 8usize) & 0x03; + super::vals::Ckd(val as u8) + } + #[doc = "Clock division"] + pub fn set_ckd(&mut self, val: super::vals::Ckd) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); + } + } + impl Default for Cr1Gp { + fn default() -> Cr1Gp { + Cr1Gp(0) + } + } + #[doc = "DMA address for full transfer"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dmar(pub u32); + impl Dmar { + #[doc = "DMA register for burst accesses"] + pub const fn dmab(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "DMA register for burst accesses"] + pub fn set_dmab(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Dmar { + fn default() -> Dmar { + Dmar(0) + } + } + #[doc = "counter"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cnt16(pub u32); + impl Cnt16 { + #[doc = "counter value"] + pub const fn cnt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "counter value"] + pub fn set_cnt(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Cnt16 { + fn default() -> Cnt16 { + Cnt16(0) + } + } + #[doc = "event generation register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct EgrBasic(pub u32); + impl EgrBasic { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for EgrBasic { + fn default() -> EgrBasic { + EgrBasic(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrGp(pub u32); + impl SrGp { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn ccif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn set_ccif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt flag"] + pub const fn comif(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt flag"] + pub fn set_comif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt flag"] + pub const fn tif(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt flag"] + pub fn set_tif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt flag"] + pub const fn bif(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break interrupt flag"] + pub fn set_bif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn ccof(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn set_ccof(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for SrGp { + fn default() -> SrGp { + SrGp(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Basic(pub u32); + impl Cr2Basic { + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + } + impl Default for Cr2Basic { + fn default() -> Cr2Basic { + Cr2Basic(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Adv(pub u32); + impl Cr2Adv { + #[doc = "Capture/compare preloaded control"] + pub const fn ccpc(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Capture/compare preloaded control"] + pub fn set_ccpc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare control update selection"] + pub const fn ccus(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Capture/compare control update selection"] + pub fn set_ccus(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Capture/compare DMA selection"] + pub const fn ccds(&self) -> super::vals::Ccds { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Ccds(val as u8) + } + #[doc = "Capture/compare DMA selection"] + pub fn set_ccds(&mut self, val: super::vals::Ccds) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "TI1 selection"] + pub const fn ti1s(&self) -> super::vals::Tis { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Tis(val as u8) + } + #[doc = "TI1 selection"] + pub fn set_ti1s(&mut self, val: super::vals::Tis) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Output Idle state 1"] + pub fn ois(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 8usize + n * 2usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output Idle state 1"] + pub fn set_ois(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 8usize + n * 2usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Output Idle state 1"] + pub const fn ois1n(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 1"] + pub fn set_ois1n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Output Idle state 2"] + pub const fn ois2n(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 2"] + pub fn set_ois2n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Output Idle state 3"] + pub const fn ois3n(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 3"] + pub fn set_ois3n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + } + impl Default for Cr2Adv { + fn default() -> Cr2Adv { + Cr2Adv(0) + } + } + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierGp(pub u32); + impl DierGp { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn ccie(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn set_ccie(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Trigger interrupt enable"] + pub const fn tie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt enable"] + pub fn set_tie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn ccde(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn set_ccde(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Trigger DMA request enable"] + pub const fn tde(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Trigger DMA request enable"] + pub fn set_tde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for DierGp { + fn default() -> DierGp { + DierGp(0) + } + } + #[doc = "auto-reload register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Arr16(pub u32); + impl Arr16 { + #[doc = "Auto-reload value"] + pub const fn arr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Auto-reload value"] + pub fn set_arr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Arr16 { + fn default() -> Arr16 { + Arr16(0) + } + } + #[doc = "capture/compare enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcerGp(pub u32); + impl CcerGp { + #[doc = "Capture/Compare 1 output enable"] + pub fn cce(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output enable"] + pub fn set_cce(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccnp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccnp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcerGp { + fn default() -> CcerGp { + CcerGp(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrAdv(pub u32); + impl SrAdv { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn ccif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn set_ccif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt flag"] + pub const fn comif(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt flag"] + pub fn set_comif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt flag"] + pub const fn tif(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt flag"] + pub fn set_tif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt flag"] + pub const fn bif(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break interrupt flag"] + pub fn set_bif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn ccof(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn set_ccof(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for SrAdv { + fn default() -> SrAdv { + SrAdv(0) + } + } + #[doc = "capture/compare register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccr16(pub u32); + impl Ccr16 { + #[doc = "Capture/Compare 1 value"] + pub const fn ccr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Capture/Compare 1 value"] + pub fn set_ccr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Ccr16 { + fn default() -> Ccr16 { + Ccr16(0) + } + } + #[doc = "repetition counter register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rcr(pub u32); + impl Rcr { + #[doc = "Repetition counter value"] + pub const fn rep(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Repetition counter value"] + pub fn set_rep(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + } + impl Default for Rcr { + fn default() -> Rcr { + Rcr(0) + } + } + #[doc = "break and dead-time register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Bdtr(pub u32); + impl Bdtr { + #[doc = "Dead-time generator setup"] + pub const fn dtg(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Dead-time generator setup"] + pub fn set_dtg(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Lock configuration"] + pub const fn lock(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x03; + val as u8 + } + #[doc = "Lock configuration"] + pub fn set_lock(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); + } + #[doc = "Off-state selection for Idle mode"] + pub const fn ossi(&self) -> super::vals::Ossi { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Ossi(val as u8) + } + #[doc = "Off-state selection for Idle mode"] + pub fn set_ossi(&mut self, val: super::vals::Ossi) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Off-state selection for Run mode"] + pub const fn ossr(&self) -> super::vals::Ossr { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Ossr(val as u8) + } + #[doc = "Off-state selection for Run mode"] + pub fn set_ossr(&mut self, val: super::vals::Ossr) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "Break enable"] + pub const fn bke(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Break enable"] + pub fn set_bke(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Break polarity"] + pub const fn bkp(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Break polarity"] + pub fn set_bkp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Automatic output enable"] + pub const fn aoe(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Automatic output enable"] + pub fn set_aoe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Main output enable"] + pub const fn moe(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Main output enable"] + pub fn set_moe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + } + impl Default for Bdtr { + fn default() -> Bdtr { + Bdtr(0) + } + } + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierBasic(pub u32); + impl DierBasic { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for DierBasic { + fn default() -> DierBasic { + DierBasic(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrBasic(pub u32); + impl SrBasic { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for SrBasic { + fn default() -> SrBasic { + SrBasic(0) + } + } + #[doc = "capture/compare enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcerAdv(pub u32); + impl CcerAdv { + #[doc = "Capture/Compare 1 output enable"] + pub fn cce(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output enable"] + pub fn set_cce(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 complementary output enable"] + pub fn ccne(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 complementary output enable"] + pub fn set_ccne(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccnp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccnp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcerAdv { + fn default() -> CcerAdv { + CcerAdv(0) + } + } + #[doc = "event generation register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct EgrGp(pub u32); + impl EgrGp { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 generation"] + pub fn ccg(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 generation"] + pub fn set_ccg(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare control update generation"] + pub const fn comg(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Capture/Compare control update generation"] + pub fn set_comg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger generation"] + pub const fn tg(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger generation"] + pub fn set_tg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break generation"] + pub const fn bg(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break generation"] + pub fn set_bg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for EgrGp { + fn default() -> EgrGp { + EgrGp(0) + } + } + #[doc = "capture/compare register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccr32(pub u32); + impl Ccr32 { + #[doc = "Capture/Compare 1 value"] + pub const fn ccr(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Capture/Compare 1 value"] + pub fn set_ccr(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Ccr32 { + fn default() -> Ccr32 { + Ccr32(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etf(pub u8); + impl Etf { + #[doc = "No filter, sampling is done at fDTS"] + pub const NOFILTER: Self = Self(0); + #[doc = "fSAMPLING=fCK_INT, N=2"] + pub const FCK_INT_N2: Self = Self(0x01); + #[doc = "fSAMPLING=fCK_INT, N=4"] + pub const FCK_INT_N4: Self = Self(0x02); + #[doc = "fSAMPLING=fCK_INT, N=8"] + pub const FCK_INT_N8: Self = Self(0x03); + #[doc = "fSAMPLING=fDTS/2, N=6"] + pub const FDTS_DIV2_N6: Self = Self(0x04); + #[doc = "fSAMPLING=fDTS/2, N=8"] + pub const FDTS_DIV2_N8: Self = Self(0x05); + #[doc = "fSAMPLING=fDTS/4, N=6"] + pub const FDTS_DIV4_N6: Self = Self(0x06); + #[doc = "fSAMPLING=fDTS/4, N=8"] + pub const FDTS_DIV4_N8: Self = Self(0x07); + #[doc = "fSAMPLING=fDTS/8, N=6"] + pub const FDTS_DIV8_N6: Self = Self(0x08); + #[doc = "fSAMPLING=fDTS/8, N=8"] + pub const FDTS_DIV8_N8: Self = Self(0x09); + #[doc = "fSAMPLING=fDTS/16, N=5"] + pub const FDTS_DIV16_N5: Self = Self(0x0a); + #[doc = "fSAMPLING=fDTS/16, N=6"] + pub const FDTS_DIV16_N6: Self = Self(0x0b); + #[doc = "fSAMPLING=fDTS/16, N=8"] + pub const FDTS_DIV16_N8: Self = Self(0x0c); + #[doc = "fSAMPLING=fDTS/32, N=5"] + pub const FDTS_DIV32_N5: Self = Self(0x0d); + #[doc = "fSAMPLING=fDTS/32, N=6"] + pub const FDTS_DIV32_N6: Self = Self(0x0e); + #[doc = "fSAMPLING=fDTS/32, N=8"] + pub const FDTS_DIV32_N8: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Tis(pub u8); + impl Tis { + #[doc = "The TIMx_CH1 pin is connected to TI1 input"] + pub const NORMAL: Self = Self(0); + #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"] + pub const XOR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ccds(pub u8); + impl Ccds { + #[doc = "CCx DMA request sent when CCx event occurs"] + pub const ONCOMPARE: Self = Self(0); + #[doc = "CCx DMA request sent when update event occurs"] + pub const ONUPDATE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Sms(pub u8); + impl Sms { + #[doc = "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] + pub const DISABLED: Self = Self(0); + #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."] + pub const ENCODER_MODE_1: Self = Self(0x01); + #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."] + pub const ENCODER_MODE_2: Self = Self(0x02); + #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."] + pub const ENCODER_MODE_3: Self = Self(0x03); + #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."] + pub const RESET_MODE: Self = Self(0x04); + #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."] + pub const GATED_MODE: Self = Self(0x05); + #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."] + pub const TRIGGER_MODE: Self = Self(0x06); + #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."] + pub const EXT_CLOCK_MODE: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Counter used as upcounter"] + pub const UP: Self = Self(0); + #[doc = "Counter used as downcounter"] + pub const DOWN: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mms(pub u8); + impl Mms { + #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"] + pub const RESET: Self = Self(0); + #[doc = "The counter enable signal, CNT_EN, is used as trigger output"] + pub const ENABLE: Self = Self(0x01); + #[doc = "The update event is selected as trigger output"] + pub const UPDATE: Self = Self(0x02); + #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"] + pub const COMPAREPULSE: Self = Self(0x03); + #[doc = "OC1REF signal is used as trigger output"] + pub const COMPAREOC1: Self = Self(0x04); + #[doc = "OC2REF signal is used as trigger output"] + pub const COMPAREOC2: Self = Self(0x05); + #[doc = "OC3REF signal is used as trigger output"] + pub const COMPAREOC3: Self = Self(0x06); + #[doc = "OC4REF signal is used as trigger output"] + pub const COMPAREOC4: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ossi(pub u8); + impl Ossi { + #[doc = "When inactive, OC/OCN outputs are disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "When inactive, OC/OCN outputs are forced to idle level"] + pub const IDLELEVEL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Urs(pub u8); + impl Urs { + #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"] + pub const ANYEVENT: Self = Self(0); + #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"] + pub const COUNTERONLY: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct CcmrOutputCcs(pub u8); + impl CcmrOutputCcs { + #[doc = "CCx channel is configured as output"] + pub const OUTPUT: Self = Self(0); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ossr(pub u8); + impl Ossr { + #[doc = "When inactive, OC/OCN outputs are disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"] + pub const IDLELEVEL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cms(pub u8); + impl Cms { + #[doc = "The counter counts up or down depending on the direction bit"] + pub const EDGEALIGNED: Self = Self(0); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] + pub const CENTERALIGNED1: Self = Self(0x01); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] + pub const CENTERALIGNED2: Self = Self(0x02); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] + pub const CENTERALIGNED3: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct CcmrInputCcs(pub u8); + impl CcmrInputCcs { + #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"] + pub const TI4: Self = Self(0x01); + #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"] + pub const TI3: Self = Self(0x02); + #[doc = "CCx channel is configured as input, ICx is mapped on TRC"] + pub const TRC: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ts(pub u8); + impl Ts { + #[doc = "Internal Trigger 0 (ITR0)"] + pub const ITR0: Self = Self(0); + #[doc = "Internal Trigger 1 (ITR1)"] + pub const ITR1: Self = Self(0x01); + #[doc = "Internal Trigger 2 (ITR2)"] + pub const ITR2: Self = Self(0x02); + #[doc = "TI1 Edge Detector (TI1F_ED)"] + pub const TI1F_ED: Self = Self(0x04); + #[doc = "Filtered Timer Input 1 (TI1FP1)"] + pub const TI1FP1: Self = Self(0x05); + #[doc = "Filtered Timer Input 2 (TI2FP2)"] + pub const TI2FP2: Self = Self(0x06); + #[doc = "External Trigger input (ETRF)"] + pub const ETRF: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ocm(pub u8); + impl Ocm { + #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] + pub const FROZEN: Self = Self(0); + #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] + pub const ACTIVEONMATCH: Self = Self(0x01); + #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] + pub const INACTIVEONMATCH: Self = Self(0x02); + #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] + pub const TOGGLE: Self = Self(0x03); + #[doc = "OCyREF is forced low"] + pub const FORCEINACTIVE: Self = Self(0x04); + #[doc = "OCyREF is forced high"] + pub const FORCEACTIVE: Self = Self(0x05); + #[doc = "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active"] + pub const PWMMODE1: Self = Self(0x06); + #[doc = "Inversely to PwmMode1"] + pub const PWMMODE2: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ckd(pub u8); + impl Ckd { + #[doc = "t_DTS = t_CK_INT"] + pub const DIV1: Self = Self(0); + #[doc = "t_DTS = 2 × t_CK_INT"] + pub const DIV2: Self = Self(0x01); + #[doc = "t_DTS = 4 × t_CK_INT"] + pub const DIV4: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ece(pub u8); + impl Ece { + #[doc = "External clock mode 2 disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Msm(pub u8); + impl Msm { + #[doc = "No action"] + pub const NOSYNC: Self = Self(0); + #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."] + pub const SYNC: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etps(pub u8); + impl Etps { + #[doc = "Prescaler OFF"] + pub const DIV1: Self = Self(0); + #[doc = "ETRP frequency divided by 2"] + pub const DIV2: Self = Self(0x01); + #[doc = "ETRP frequency divided by 4"] + pub const DIV4: Self = Self(0x02); + #[doc = "ETRP frequency divided by 8"] + pub const DIV8: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ocpe(pub u8); + impl Ocpe { + #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"] + pub const DISABLED: Self = Self(0); + #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Arpe(pub u8); + impl Arpe { + #[doc = "TIMx_APRR register is not buffered"] + pub const DISABLED: Self = Self(0); + #[doc = "TIMx_APRR register is buffered"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Icf(pub u8); + impl Icf { + #[doc = "No filter, sampling is done at fDTS"] + pub const NOFILTER: Self = Self(0); + #[doc = "fSAMPLING=fCK_INT, N=2"] + pub const FCK_INT_N2: Self = Self(0x01); + #[doc = "fSAMPLING=fCK_INT, N=4"] + pub const FCK_INT_N4: Self = Self(0x02); + #[doc = "fSAMPLING=fCK_INT, N=8"] + pub const FCK_INT_N8: Self = Self(0x03); + #[doc = "fSAMPLING=fDTS/2, N=6"] + pub const FDTS_DIV2_N6: Self = Self(0x04); + #[doc = "fSAMPLING=fDTS/2, N=8"] + pub const FDTS_DIV2_N8: Self = Self(0x05); + #[doc = "fSAMPLING=fDTS/4, N=6"] + pub const FDTS_DIV4_N6: Self = Self(0x06); + #[doc = "fSAMPLING=fDTS/4, N=8"] + pub const FDTS_DIV4_N8: Self = Self(0x07); + #[doc = "fSAMPLING=fDTS/8, N=6"] + pub const FDTS_DIV8_N6: Self = Self(0x08); + #[doc = "fSAMPLING=fDTS/8, N=8"] + pub const FDTS_DIV8_N8: Self = Self(0x09); + #[doc = "fSAMPLING=fDTS/16, N=5"] + pub const FDTS_DIV16_N5: Self = Self(0x0a); + #[doc = "fSAMPLING=fDTS/16, N=6"] + pub const FDTS_DIV16_N6: Self = Self(0x0b); + #[doc = "fSAMPLING=fDTS/16, N=8"] + pub const FDTS_DIV16_N8: Self = Self(0x0c); + #[doc = "fSAMPLING=fDTS/32, N=5"] + pub const FDTS_DIV32_N5: Self = Self(0x0d); + #[doc = "fSAMPLING=fDTS/32, N=6"] + pub const FDTS_DIV32_N6: Self = Self(0x0e); + #[doc = "fSAMPLING=fDTS/32, N=8"] + pub const FDTS_DIV32_N8: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Opm(pub u8); + impl Opm { + #[doc = "Counter is not stopped at update event"] + pub const DISABLED: Self = Self(0); + #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etp(pub u8); + impl Etp { + #[doc = "ETR is noninverted, active at high level or rising edge"] + pub const NOTINVERTED: Self = Self(0); + #[doc = "ETR is inverted, active at low level or falling edge"] + pub const INVERTED: Self = Self(0x01); + } + } +} +pub mod gpio_v1 { + use crate::generic::*; + #[doc = "General purpose I/O"] + #[derive(Copy, Clone)] + pub struct Gpio(pub *mut u8); + unsafe impl Send for Gpio {} + unsafe impl Sync for Gpio {} + impl Gpio { + #[doc = "Port configuration register low (GPIOn_CRL)"] + pub fn cr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) } + } + #[doc = "Port input data register (GPIOn_IDR)"] + pub fn idr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Port output data register (GPIOn_ODR)"] + pub fn odr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Port bit set/reset register (GPIOn_BSRR)"] + pub fn bsrr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Port bit reset register (GPIOn_BRR)"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "Port configuration lock register"] + pub fn lckr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Odr(pub u8); + impl Odr { + #[doc = "Set output to logic low"] + pub const LOW: Self = Self(0); + #[doc = "Set output to logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lckk(pub u8); + impl Lckk { + #[doc = "Port configuration lock key not active"] + pub const NOTACTIVE: Self = Self(0); + #[doc = "Port configuration lock key active"] + pub const ACTIVE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cnf(pub u8); + impl Cnf { + #[doc = "Analog mode / Push-Pull mode"] + pub const PUSHPULL: Self = Self(0); + #[doc = "Floating input (reset state) / Open Drain-Mode"] + pub const OPENDRAIN: Self = Self(0x01); + #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"] + pub const ALTPUSHPULL: Self = Self(0x02); + #[doc = "Alternate Function Open-Drain Mode"] + pub const ALTOPENDRAIN: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Idr(pub u8); + impl Idr { + #[doc = "Input is logic low"] + pub const LOW: Self = Self(0); + #[doc = "Input is logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bsw(pub u8); + impl Bsw { + #[doc = "No action on the corresponding ODx bit"] + pub const NOACTION: Self = Self(0); + #[doc = "Sets the corresponding ODRx bit"] + pub const SET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Brw(pub u8); + impl Brw { + #[doc = "No action on the corresponding ODx bit"] + pub const NOACTION: Self = Self(0); + #[doc = "Reset the ODx bit"] + pub const RESET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mode(pub u8); + impl Mode { + #[doc = "Input mode (reset state)"] + pub const INPUT: Self = Self(0); + #[doc = "Output mode 10 MHz"] + pub const OUTPUT: Self = Self(0x01); + #[doc = "Output mode 2 MHz"] + pub const OUTPUT2: Self = Self(0x02); + #[doc = "Output mode 50 MHz"] + pub const OUTPUT50: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lck(pub u8); + impl Lck { + #[doc = "Port configuration not locked"] + pub const UNLOCKED: Self = Self(0); + #[doc = "Port configuration locked"] + pub const LOCKED: Self = Self(0x01); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "Port bit reset register (GPIOn_BRR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Brr(pub u32); + impl Brr { + #[doc = "Reset bit"] + pub fn br(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Reset bit"] + pub fn set_br(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Brr { + fn default() -> Brr { + Brr(0) + } + } + #[doc = "Port input data register (GPIOn_IDR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idr(pub u32); + impl Idr { + #[doc = "Port input data"] + pub fn idr(&self, n: usize) -> super::vals::Idr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Idr(val as u8) + } + #[doc = "Port input data"] + pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Idr { + fn default() -> Idr { + Idr(0) + } + } + #[doc = "Port configuration register (GPIOn_CRx)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Port n mode bits"] + pub fn mode(&self, n: usize) -> super::vals::Mode { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Mode(val as u8) + } + #[doc = "Port n mode bits"] + pub fn set_mode(&mut self, n: usize, val: super::vals::Mode) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Port n configuration bits"] + pub fn cnf(&self, n: usize) -> super::vals::Cnf { + assert!(n < 8usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Cnf(val as u8) + } + #[doc = "Port n configuration bits"] + pub fn set_cnf(&mut self, n: usize, val: super::vals::Cnf) { + assert!(n < 8usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + #[doc = "Port configuration lock register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Lckr(pub u32); + impl Lckr { + #[doc = "Port A Lock bit"] + pub fn lck(&self, n: usize) -> super::vals::Lck { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Lck(val as u8) + } + #[doc = "Port A Lock bit"] + pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Lock key"] + pub const fn lckk(&self) -> super::vals::Lckk { + let val = (self.0 >> 16usize) & 0x01; + super::vals::Lckk(val as u8) + } + #[doc = "Lock key"] + pub fn set_lckk(&mut self, val: super::vals::Lckk) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); + } + } + impl Default for Lckr { + fn default() -> Lckr { + Lckr(0) + } + } + #[doc = "Port bit set/reset register (GPIOn_BSRR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Bsrr(pub u32); + impl Bsrr { + #[doc = "Set bit"] + pub fn bs(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Set bit"] + pub fn set_bs(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Reset bit"] + pub fn br(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Reset bit"] + pub fn set_br(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Bsrr { + fn default() -> Bsrr { + Bsrr(0) + } + } + #[doc = "Port output data register (GPIOn_ODR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Odr(pub u32); + impl Odr { + #[doc = "Port output data"] + pub fn odr(&self, n: usize) -> super::vals::Odr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Odr(val as u8) + } + #[doc = "Port output data"] + pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Odr { + fn default() -> Odr { + Odr(0) + } + } + } +} +pub mod spi_v1 { + use crate::generic::*; + #[doc = "Serial peripheral interface"] + #[derive(Copy, Clone)] + pub struct Spi(pub *mut u8); + unsafe impl Send for Spi {} + unsafe impl Sync for Spi {} + impl Spi { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "CRC polynomial register"] + pub fn crcpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "RX CRC register"] + pub fn rxcrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "TX CRC register"] + pub fn txcrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "TX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Txcrcr(pub u32); + impl Txcrcr { + #[doc = "Tx CRC register"] + pub const fn tx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Tx CRC register"] + pub fn set_tx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Txcrcr { + fn default() -> Txcrcr { + Txcrcr(0) + } + } + #[doc = "RX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rxcrcr(pub u32); + impl Rxcrcr { + #[doc = "Rx CRC register"] + pub const fn rx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Rx CRC register"] + pub fn set_rx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Rxcrcr { + fn default() -> Rxcrcr { + Rxcrcr(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2(pub u32); + impl Cr2 { + #[doc = "Rx buffer DMA enable"] + pub const fn rxdmaen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Rx buffer DMA enable"] + pub fn set_rxdmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Tx buffer DMA enable"] + pub const fn txdmaen(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Tx buffer DMA enable"] + pub fn set_txdmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "SS output enable"] + pub const fn ssoe(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "SS output enable"] + pub fn set_ssoe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Frame format"] + pub const fn frf(&self) -> super::vals::Frf { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Frf(val as u8) + } + #[doc = "Frame format"] + pub fn set_frf(&mut self, val: super::vals::Frf) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Error interrupt enable"] + pub const fn errie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_errie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "RX buffer not empty interrupt enable"] + pub const fn rxneie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "RX buffer not empty interrupt enable"] + pub fn set_rxneie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Tx buffer empty interrupt enable"] + pub const fn txeie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Tx buffer empty interrupt enable"] + pub fn set_txeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for Cr2 { + fn default() -> Cr2 { + Cr2(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1(pub u32); + impl Cr1 { + #[doc = "Clock phase"] + pub const fn cpha(&self) -> super::vals::Cpha { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Cpha(val as u8) + } + #[doc = "Clock phase"] + pub fn set_cpha(&mut self, val: super::vals::Cpha) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); + } + #[doc = "Clock polarity"] + pub const fn cpol(&self) -> super::vals::Cpol { + let val = (self.0 >> 1usize) & 0x01; + super::vals::Cpol(val as u8) + } + #[doc = "Clock polarity"] + pub fn set_cpol(&mut self, val: super::vals::Cpol) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); + } + #[doc = "Master selection"] + pub const fn mstr(&self) -> super::vals::Mstr { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Mstr(val as u8) + } + #[doc = "Master selection"] + pub fn set_mstr(&mut self, val: super::vals::Mstr) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Baud rate control"] + pub const fn br(&self) -> super::vals::Br { + let val = (self.0 >> 3usize) & 0x07; + super::vals::Br(val as u8) + } + #[doc = "Baud rate control"] + pub fn set_br(&mut self, val: super::vals::Br) { + self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); + } + #[doc = "SPI enable"] + pub const fn spe(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "SPI enable"] + pub fn set_spe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Frame format"] + pub const fn lsbfirst(&self) -> super::vals::Lsbfirst { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Lsbfirst(val as u8) + } + #[doc = "Frame format"] + pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Internal slave select"] + pub const fn ssi(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Internal slave select"] + pub fn set_ssi(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Software slave management"] + pub const fn ssm(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Software slave management"] + pub fn set_ssm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Receive only"] + pub const fn rxonly(&self) -> super::vals::Rxonly { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Rxonly(val as u8) + } + #[doc = "Receive only"] + pub fn set_rxonly(&mut self, val: super::vals::Rxonly) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Data frame format"] + pub const fn dff(&self) -> super::vals::Dff { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Dff(val as u8) + } + #[doc = "Data frame format"] + pub fn set_dff(&mut self, val: super::vals::Dff) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "CRC transfer next"] + pub const fn crcnext(&self) -> super::vals::Crcnext { + let val = (self.0 >> 12usize) & 0x01; + super::vals::Crcnext(val as u8) + } + #[doc = "CRC transfer next"] + pub fn set_crcnext(&mut self, val: super::vals::Crcnext) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "Hardware CRC calculation enable"] + pub const fn crcen(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Hardware CRC calculation enable"] + pub fn set_crcen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Output enable in bidirectional mode"] + pub const fn bidioe(&self) -> super::vals::Bidioe { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Bidioe(val as u8) + } + #[doc = "Output enable in bidirectional mode"] + pub fn set_bidioe(&mut self, val: super::vals::Bidioe) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + #[doc = "Bidirectional data mode enable"] + pub const fn bidimode(&self) -> super::vals::Bidimode { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Bidimode(val as u8) + } + #[doc = "Bidirectional data mode enable"] + pub fn set_bidimode(&mut self, val: super::vals::Bidimode) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + } + impl Default for Cr1 { + fn default() -> Cr1 { + Cr1(0) + } + } + #[doc = "data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dr(pub u32); + impl Dr { + #[doc = "Data register"] + pub const fn dr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Data register"] + pub fn set_dr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Dr { + fn default() -> Dr { + Dr(0) + } + } + #[doc = "CRC polynomial register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Crcpr(pub u32); + impl Crcpr { + #[doc = "CRC polynomial register"] + pub const fn crcpoly(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "CRC polynomial register"] + pub fn set_crcpoly(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Crcpr { + fn default() -> Crcpr { + Crcpr(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Receive buffer not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Receive buffer not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Transmit buffer empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Transmit buffer empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "CRC error flag"] + pub const fn crcerr(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "CRC error flag"] + pub fn set_crcerr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Mode fault"] + pub const fn modf(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Mode fault"] + pub fn set_modf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Overrun flag"] + pub const fn ovr(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Overrun flag"] + pub fn set_ovr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Busy flag"] + pub const fn bsy(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Busy flag"] + pub fn set_bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "TI frame format error"] + pub const fn fre(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "TI frame format error"] + pub fn set_fre(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frf(pub u8); + impl Frf { + #[doc = "SPI Motorola mode"] + pub const MOTOROLA: Self = Self(0); + #[doc = "SPI TI mode"] + pub const TI: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Iscfg(pub u8); + impl Iscfg { + #[doc = "Slave - transmit"] + pub const SLAVETX: Self = Self(0); + #[doc = "Slave - receive"] + pub const SLAVERX: Self = Self(0x01); + #[doc = "Master - transmit"] + pub const MASTERTX: Self = Self(0x02); + #[doc = "Master - receive"] + pub const MASTERRX: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidioe(pub u8); + impl Bidioe { + #[doc = "Output disabled (receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0); + #[doc = "Output enabled (transmit-only mode)"] + pub const OUTPUTENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dff(pub u8); + impl Dff { + #[doc = "8-bit data frame format is selected for transmission/reception"] + pub const EIGHTBIT: Self = Self(0); + #[doc = "16-bit data frame format is selected for transmission/reception"] + pub const SIXTEENBIT: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidimode(pub u8); + impl Bidimode { + #[doc = "2-line unidirectional data mode selected"] + pub const UNIDIRECTIONAL: Self = Self(0); + #[doc = "1-line bidirectional data mode selected"] + pub const BIDIRECTIONAL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRSTEDGE: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECONDEDGE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rxonly(pub u8); + impl Rxonly { + #[doc = "Full duplex (Transmit and receive)"] + pub const FULLDUPLEX: Self = Self(0); + #[doc = "Output disabled (Receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lsbfirst(pub u8); + impl Lsbfirst { + #[doc = "Data is transmitted/received with the MSB first"] + pub const MSBFIRST: Self = Self(0); + #[doc = "Data is transmitted/received with the LSB first"] + pub const LSBFIRST: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frer(pub u8); + impl Frer { + #[doc = "No frame format error"] + pub const NOERROR: Self = Self(0); + #[doc = "A frame format error occurred"] + pub const ERROR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Crcnext(pub u8); + impl Crcnext { + #[doc = "Next transmit value is from Tx buffer"] + pub const TXBUFFER: Self = Self(0); + #[doc = "Next transmit value is from Tx CRC register"] + pub const CRC: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Br(pub u8); + impl Br { + #[doc = "f_PCLK / 2"] + pub const DIV2: Self = Self(0); + #[doc = "f_PCLK / 4"] + pub const DIV4: Self = Self(0x01); + #[doc = "f_PCLK / 8"] + pub const DIV8: Self = Self(0x02); + #[doc = "f_PCLK / 16"] + pub const DIV16: Self = Self(0x03); + #[doc = "f_PCLK / 32"] + pub const DIV32: Self = Self(0x04); + #[doc = "f_PCLK / 64"] + pub const DIV64: Self = Self(0x05); + #[doc = "f_PCLK / 128"] + pub const DIV128: Self = Self(0x06); + #[doc = "f_PCLK / 256"] + pub const DIV256: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpol(pub u8); + impl Cpol { + #[doc = "CK to 0 when idle"] + pub const IDLELOW: Self = Self(0); + #[doc = "CK to 1 when idle"] + pub const IDLEHIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mstr(pub u8); + impl Mstr { + #[doc = "Slave configuration"] + pub const SLAVE: Self = Self(0); + #[doc = "Master configuration"] + pub const MASTER: Self = Self(0x01); + } + } +} +pub mod exti_v1 { + use crate::generic::*; + #[doc = "External interrupt/event controller"] + #[derive(Copy, Clone)] + pub struct Exti(pub *mut u8); + unsafe impl Send for Exti {} + unsafe impl Sync for Exti {} + impl Exti { + #[doc = "Interrupt mask register (EXTI_IMR)"] + pub fn imr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Event mask register (EXTI_EMR)"] + pub fn emr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Rising Trigger selection register (EXTI_RTSR)"] + pub fn rtsr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Falling Trigger selection register (EXTI_FTSR)"] + pub fn ftsr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Software interrupt event register (EXTI_SWIER)"] + pub fn swier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Pending register (EXTI_PR)"] + pub fn pr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Tr(pub u8); + impl Tr { + #[doc = "Falling edge trigger is disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Falling edge trigger is enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Swierw(pub u8); + impl Swierw { + #[doc = "Generates an interrupt request"] + pub const PEND: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mr(pub u8); + impl Mr { + #[doc = "Interrupt request line is masked"] + pub const MASKED: Self = Self(0); + #[doc = "Interrupt request line is unmasked"] + pub const UNMASKED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Prr(pub u8); + impl Prr { + #[doc = "No trigger request occurred"] + pub const NOTPENDING: Self = Self(0); + #[doc = "Selected trigger request occurred"] + pub const PENDING: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Prw(pub u8); + impl Prw { + #[doc = "Clears pending bit"] + pub const CLEAR: Self = Self(0x01); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "Falling Trigger selection register (EXTI_FTSR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ftsr(pub u32); + impl Ftsr { + #[doc = "Falling trigger event configuration of line 0"] + pub fn tr(&self, n: usize) -> super::vals::Tr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Tr(val as u8) + } + #[doc = "Falling trigger event configuration of line 0"] + pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Ftsr { + fn default() -> Ftsr { + Ftsr(0) + } + } + #[doc = "Rising Trigger selection register (EXTI_RTSR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rtsr(pub u32); + impl Rtsr { + #[doc = "Rising trigger event configuration of line 0"] + pub fn tr(&self, n: usize) -> super::vals::Tr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Tr(val as u8) + } + #[doc = "Rising trigger event configuration of line 0"] + pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Rtsr { + fn default() -> Rtsr { + Rtsr(0) + } + } + #[doc = "Event mask register (EXTI_EMR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Emr(pub u32); + impl Emr { + #[doc = "Event Mask on line 0"] + pub fn mr(&self, n: usize) -> super::vals::Mr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Mr(val as u8) + } + #[doc = "Event Mask on line 0"] + pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Emr { + fn default() -> Emr { + Emr(0) + } + } + #[doc = "Interrupt mask register (EXTI_IMR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Imr(pub u32); + impl Imr { + #[doc = "Interrupt Mask on line 0"] + pub fn mr(&self, n: usize) -> super::vals::Mr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Mr(val as u8) + } + #[doc = "Interrupt Mask on line 0"] + pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Imr { + fn default() -> Imr { + Imr(0) + } + } + #[doc = "Pending register (EXTI_PR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pr(pub u32); + impl Pr { + #[doc = "Pending bit 0"] + pub fn pr(&self, n: usize) -> bool { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Pending bit 0"] + pub fn set_pr(&mut self, n: usize, val: bool) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Pr { + fn default() -> Pr { + Pr(0) + } + } + #[doc = "Software interrupt event register (EXTI_SWIER)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Swier(pub u32); + impl Swier { + #[doc = "Software Interrupt on line 0"] + pub fn swier(&self, n: usize) -> bool { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Software Interrupt on line 0"] + pub fn set_swier(&mut self, n: usize, val: bool) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Swier { + fn default() -> Swier { + Swier(0) + } + } + } +} +pub mod dma_v1 { + use crate::generic::*; + #[doc = "DMA controller"] + #[derive(Copy, Clone)] + pub struct Dma(pub *mut u8); + unsafe impl Send for Dma {} + unsafe impl Sync for Dma {} + impl Dma { + #[doc = "DMA interrupt status register (DMA_ISR)"] + pub fn isr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] + pub fn ifcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] + pub fn ch(self, n: usize) -> Ch { + assert!(n < 7usize); + unsafe { Ch(self.0.add(8usize + n * 20usize)) } + } + } + #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] + #[derive(Copy, Clone)] + pub struct Ch(pub *mut u8); + unsafe impl Send for Ch {} + unsafe impl Sync for Ch {} + impl Ch { + #[doc = "DMA channel configuration register (DMA_CCR)"] + pub fn cr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "DMA channel 1 number of data register"] + pub fn ndtr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "DMA channel 1 peripheral address register"] + pub fn par(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA channel 1 memory address register"] + pub fn mar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pl(pub u8); + impl Pl { + #[doc = "Low priority"] + pub const LOW: Self = Self(0); + #[doc = "Medium priority"] + pub const MEDIUM: Self = Self(0x01); + #[doc = "High priority"] + pub const HIGH: Self = Self(0x02); + #[doc = "Very high priority"] + pub const VERYHIGH: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Read from peripheral"] + pub const FROMPERIPHERAL: Self = Self(0); + #[doc = "Read from memory"] + pub const FROMMEMORY: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Size(pub u8); + impl Size { + #[doc = "8-bit size"] + pub const BITS8: Self = Self(0); + #[doc = "16-bit size"] + pub const BITS16: Self = Self(0x01); + #[doc = "32-bit size"] + pub const BITS32: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Memmem(pub u8); + impl Memmem { + #[doc = "Memory to memory mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Memory to memory mode enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Circ(pub u8); + impl Circ { + #[doc = "Circular buffer disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Circular buffer enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Inc(pub u8); + impl Inc { + #[doc = "Increment mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Increment mode enabled"] + pub const ENABLED: Self = Self(0x01); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "DMA interrupt status register (DMA_ISR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Isr(pub u32); + impl Isr { + #[doc = "Channel 1 Global interrupt flag"] + pub fn gif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Global interrupt flag"] + pub fn set_gif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Complete flag"] + pub fn tcif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Complete flag"] + pub fn set_tcif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Half Transfer Complete flag"] + pub fn htif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Half Transfer Complete flag"] + pub fn set_htif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Error flag"] + pub fn teif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Error flag"] + pub fn set_teif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Isr { + fn default() -> Isr { + Isr(0) + } + } + #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ifcr(pub u32); + impl Ifcr { + #[doc = "Channel 1 Global interrupt clear"] + pub fn cgif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Global interrupt clear"] + pub fn set_cgif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Complete clear"] + pub fn ctcif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Complete clear"] + pub fn set_ctcif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Half Transfer clear"] + pub fn chtif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Half Transfer clear"] + pub fn set_chtif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Error clear"] + pub fn cteif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Error clear"] + pub fn set_cteif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Ifcr { + fn default() -> Ifcr { + Ifcr(0) + } + } + #[doc = "DMA channel configuration register (DMA_CCR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Channel enable"] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Channel enable"] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Transfer complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Transfer complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Half Transfer interrupt enable"] + pub const fn htie(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Half Transfer interrupt enable"] + pub fn set_htie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Transfer error interrupt enable"] + pub const fn teie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Transfer error interrupt enable"] + pub fn set_teie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Data transfer direction"] + pub const fn dir(&self) -> super::vals::Dir { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Dir(val as u8) + } + #[doc = "Data transfer direction"] + pub fn set_dir(&mut self, val: super::vals::Dir) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Circular mode"] + pub const fn circ(&self) -> super::vals::Circ { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Circ(val as u8) + } + #[doc = "Circular mode"] + pub fn set_circ(&mut self, val: super::vals::Circ) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "Peripheral increment mode"] + pub const fn pinc(&self) -> super::vals::Inc { + let val = (self.0 >> 6usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Peripheral increment mode"] + pub fn set_pinc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize); + } + #[doc = "Memory increment mode"] + pub const fn minc(&self) -> super::vals::Inc { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Memory increment mode"] + pub fn set_minc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Peripheral size"] + pub const fn psize(&self) -> super::vals::Size { + let val = (self.0 >> 8usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Peripheral size"] + pub fn set_psize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); + } + #[doc = "Memory size"] + pub const fn msize(&self) -> super::vals::Size { + let val = (self.0 >> 10usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Memory size"] + pub fn set_msize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 10usize)) | (((val.0 as u32) & 0x03) << 10usize); + } + #[doc = "Channel Priority level"] + pub const fn pl(&self) -> super::vals::Pl { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Pl(val as u8) + } + #[doc = "Channel Priority level"] + pub fn set_pl(&mut self, val: super::vals::Pl) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "Memory to memory mode"] + pub const fn mem2mem(&self) -> super::vals::Memmem { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Memmem(val as u8) + } + #[doc = "Memory to memory mode"] + pub fn set_mem2mem(&mut self, val: super::vals::Memmem) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + #[doc = "DMA channel 1 number of data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ndtr(pub u32); + impl Ndtr { + #[doc = "Number of data to transfer"] + pub const fn ndt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Number of data to transfer"] + pub fn set_ndt(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Ndtr { + fn default() -> Ndtr { + Ndtr(0) + } + } + } +} +pub mod rng_v1 { + use crate::generic::*; + #[doc = "Random number generator"] + #[derive(Copy, Clone)] + pub struct Rng(pub *mut u8); + unsafe impl Send for Rng {} + unsafe impl Sync for Rng {} + impl Rng { + #[doc = "control register"] + pub fn cr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Data ready"] + pub const fn drdy(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Data ready"] + pub fn set_drdy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Clock error current status"] + pub const fn cecs(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Clock error current status"] + pub fn set_cecs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Seed error current status"] + pub const fn secs(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Seed error current status"] + pub fn set_secs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Clock error interrupt status"] + pub const fn ceis(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Clock error interrupt status"] + pub fn set_ceis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Seed error interrupt status"] + pub const fn seis(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Seed error interrupt status"] + pub fn set_seis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + #[doc = "control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Random number generator enable"] + pub const fn rngen(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Random number generator enable"] + pub fn set_rngen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Interrupt enable"] + pub const fn ie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Interrupt enable"] + pub fn set_ie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + } +} +pub mod gpio_v2 { + use crate::generic::*; + #[doc = "General-purpose I/Os"] + #[derive(Copy, Clone)] + pub struct Gpio(pub *mut u8); + unsafe impl Send for Gpio {} + unsafe impl Sync for Gpio {} + impl Gpio { + #[doc = "GPIO port mode register"] + pub fn moder(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "GPIO port output type register"] + pub fn otyper(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "GPIO port output speed register"] + pub fn ospeedr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "GPIO port pull-up/pull-down register"] + pub fn pupdr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "GPIO port input data register"] + pub fn idr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "GPIO port output data register"] + pub fn odr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "GPIO port bit set/reset register"] + pub fn bsrr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + #[doc = "GPIO port configuration lock register"] + pub fn lckr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(28usize)) } + } + #[doc = "GPIO alternate function register (low, high)"] + pub fn afr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(32usize + n * 4usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ot(pub u8); + impl Ot { + #[doc = "Output push-pull (reset state)"] + pub const PUSHPULL: Self = Self(0); + #[doc = "Output open-drain"] + pub const OPENDRAIN: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pupdr(pub u8); + impl Pupdr { + #[doc = "No pull-up, pull-down"] + pub const FLOATING: Self = Self(0); + #[doc = "Pull-up"] + pub const PULLUP: Self = Self(0x01); + #[doc = "Pull-down"] + pub const PULLDOWN: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Afr(pub u8); + impl Afr { + #[doc = "AF0"] + pub const AF0: Self = Self(0); + #[doc = "AF1"] + pub const AF1: Self = Self(0x01); + #[doc = "AF2"] + pub const AF2: Self = Self(0x02); + #[doc = "AF3"] + pub const AF3: Self = Self(0x03); + #[doc = "AF4"] + pub const AF4: Self = Self(0x04); + #[doc = "AF5"] + pub const AF5: Self = Self(0x05); + #[doc = "AF6"] + pub const AF6: Self = Self(0x06); + #[doc = "AF7"] + pub const AF7: Self = Self(0x07); + #[doc = "AF8"] + pub const AF8: Self = Self(0x08); + #[doc = "AF9"] + pub const AF9: Self = Self(0x09); + #[doc = "AF10"] + pub const AF10: Self = Self(0x0a); + #[doc = "AF11"] + pub const AF11: Self = Self(0x0b); + #[doc = "AF12"] + pub const AF12: Self = Self(0x0c); + #[doc = "AF13"] + pub const AF13: Self = Self(0x0d); + #[doc = "AF14"] + pub const AF14: Self = Self(0x0e); + #[doc = "AF15"] + pub const AF15: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Moder(pub u8); + impl Moder { + #[doc = "Input mode (reset state)"] + pub const INPUT: Self = Self(0); + #[doc = "General purpose output mode"] + pub const OUTPUT: Self = Self(0x01); + #[doc = "Alternate function mode"] + pub const ALTERNATE: Self = Self(0x02); + #[doc = "Analog mode"] + pub const ANALOG: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ospeedr(pub u8); + impl Ospeedr { + #[doc = "Low speed"] + pub const LOWSPEED: Self = Self(0); + #[doc = "Medium speed"] + pub const MEDIUMSPEED: Self = Self(0x01); + #[doc = "High speed"] + pub const HIGHSPEED: Self = Self(0x02); + #[doc = "Very high speed"] + pub const VERYHIGHSPEED: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Idr(pub u8); + impl Idr { + #[doc = "Input is logic low"] + pub const LOW: Self = Self(0); + #[doc = "Input is logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Odr(pub u8); + impl Odr { + #[doc = "Set output to logic low"] + pub const LOW: Self = Self(0); + #[doc = "Set output to logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Brw(pub u8); + impl Brw { + #[doc = "Resets the corresponding ODRx bit"] + pub const RESET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bsw(pub u8); + impl Bsw { + #[doc = "Sets the corresponding ODRx bit"] + pub const SET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lckk(pub u8); + impl Lckk { + #[doc = "Port configuration lock key not active"] + pub const NOTACTIVE: Self = Self(0); + #[doc = "Port configuration lock key active"] + pub const ACTIVE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lck(pub u8); + impl Lck { + #[doc = "Port configuration not locked"] + pub const UNLOCKED: Self = Self(0); + #[doc = "Port configuration locked"] + pub const LOCKED: Self = Self(0x01); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "GPIO alternate function register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Afr(pub u32); + impl Afr { + #[doc = "Alternate function selection for port x bit y (y = 0..15)"] + pub fn afr(&self, n: usize) -> super::vals::Afr { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + super::vals::Afr(val as u8) + } + #[doc = "Alternate function selection for port x bit y (y = 0..15)"] + pub fn set_afr(&mut self, n: usize, val: super::vals::Afr) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); + } + } + impl Default for Afr { + fn default() -> Afr { + Afr(0) + } + } + #[doc = "GPIO port configuration lock register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Lckr(pub u32); + impl Lckr { + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn lck(&self, n: usize) -> super::vals::Lck { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Lck(val as u8) + } + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Port x lock bit y (y= 0..15)"] + pub const fn lckk(&self) -> super::vals::Lckk { + let val = (self.0 >> 16usize) & 0x01; + super::vals::Lckk(val as u8) + } + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn set_lckk(&mut self, val: super::vals::Lckk) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); + } + } + impl Default for Lckr { + fn default() -> Lckr { + Lckr(0) + } + } + #[doc = "GPIO port output speed register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ospeedr(pub u32); + impl Ospeedr { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Ospeedr(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Ospeedr { + fn default() -> Ospeedr { + Ospeedr(0) + } + } + #[doc = "GPIO port input data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idr(pub u32); + impl Idr { + #[doc = "Port input data (y = 0..15)"] + pub fn idr(&self, n: usize) -> super::vals::Idr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Idr(val as u8) + } + #[doc = "Port input data (y = 0..15)"] + pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Idr { + fn default() -> Idr { + Idr(0) + } + } + #[doc = "GPIO port bit set/reset register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Bsrr(pub u32); + impl Bsrr { + #[doc = "Port x set bit y (y= 0..15)"] + pub fn bs(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Port x set bit y (y= 0..15)"] + pub fn set_bs(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Port x set bit y (y= 0..15)"] + pub fn br(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Port x set bit y (y= 0..15)"] + pub fn set_br(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Bsrr { + fn default() -> Bsrr { + Bsrr(0) + } + } + #[doc = "GPIO port output type register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Otyper(pub u32); + impl Otyper { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn ot(&self, n: usize) -> super::vals::Ot { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Ot(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_ot(&mut self, n: usize, val: super::vals::Ot) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Otyper { + fn default() -> Otyper { + Otyper(0) + } + } + #[doc = "GPIO port mode register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Moder(pub u32); + impl Moder { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn moder(&self, n: usize) -> super::vals::Moder { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Moder(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Moder { + fn default() -> Moder { + Moder(0) + } + } + #[doc = "GPIO port pull-up/pull-down register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pupdr(pub u32); + impl Pupdr { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn pupdr(&self, n: usize) -> super::vals::Pupdr { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Pupdr(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_pupdr(&mut self, n: usize, val: super::vals::Pupdr) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Pupdr { + fn default() -> Pupdr { + Pupdr(0) + } + } + #[doc = "GPIO port output data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Odr(pub u32); + impl Odr { + #[doc = "Port output data (y = 0..15)"] + pub fn odr(&self, n: usize) -> super::vals::Odr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Odr(val as u8) + } + #[doc = "Port output data (y = 0..15)"] + pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Odr { + fn default() -> Odr { + Odr(0) + } + } + } +} +pub mod syscfg_l4 { + use crate::generic::*; + #[doc = "System configuration controller"] + #[derive(Copy, Clone)] + pub struct Syscfg(pub *mut u8); + unsafe impl Send for Syscfg {} + unsafe impl Sync for Syscfg {} + impl Syscfg { + #[doc = "memory remap register"] + pub fn memrmp(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "configuration register 1"] + pub fn cfgr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "external interrupt configuration register 1"] + pub fn exticr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } + } + #[doc = "SCSR"] + pub fn scsr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + #[doc = "CFGR2"] + pub fn cfgr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(28usize)) } + } + #[doc = "SWPR"] + pub fn swpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "SKR"] + pub fn skr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "CFGR2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cfgr2(pub u32); + impl Cfgr2 { + #[doc = "Cortex LOCKUP (Hardfault) output enable bit"] + pub const fn cll(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Cortex LOCKUP (Hardfault) output enable bit"] + pub fn set_cll(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "SRAM2 parity lock bit"] + pub const fn spl(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 parity lock bit"] + pub fn set_spl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "PVD lock enable bit"] + pub const fn pvdl(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "PVD lock enable bit"] + pub fn set_pvdl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "ECC Lock"] + pub const fn eccl(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "ECC Lock"] + pub fn set_eccl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "SRAM2 parity error flag"] + pub const fn spf(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 parity error flag"] + pub fn set_spf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Cfgr2 { + fn default() -> Cfgr2 { + Cfgr2(0) + } + } + #[doc = "configuration register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cfgr1(pub u32); + impl Cfgr1 { + #[doc = "Firewall disable"] + pub const fn fwdis(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Firewall disable"] + pub fn set_fwdis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "I/O analog switch voltage booster enable"] + pub const fn boosten(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "I/O analog switch voltage booster enable"] + pub fn set_boosten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"] + pub const fn i2c_pb6_fmp(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"] + pub fn set_i2c_pb6_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"] + pub const fn i2c_pb7_fmp(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"] + pub fn set_i2c_pb7_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"] + pub const fn i2c_pb8_fmp(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"] + pub fn set_i2c_pb8_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"] + pub const fn i2c_pb9_fmp(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"] + pub fn set_i2c_pb9_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "I2C1 Fast-mode Plus driving capability activation"] + pub const fn i2c1_fmp(&self) -> bool { + let val = (self.0 >> 20usize) & 0x01; + val != 0 + } + #[doc = "I2C1 Fast-mode Plus driving capability activation"] + pub fn set_i2c1_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); + } + #[doc = "I2C2 Fast-mode Plus driving capability activation"] + pub const fn i2c2_fmp(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "I2C2 Fast-mode Plus driving capability activation"] + pub fn set_i2c2_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "I2C3 Fast-mode Plus driving capability activation"] + pub const fn i2c3_fmp(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "I2C3 Fast-mode Plus driving capability activation"] + pub fn set_i2c3_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "Floating Point Unit interrupts enable bits"] + pub const fn fpu_ie(&self) -> u8 { + let val = (self.0 >> 26usize) & 0x3f; + val as u8 + } + #[doc = "Floating Point Unit interrupts enable bits"] + pub fn set_fpu_ie(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 26usize)) | (((val as u32) & 0x3f) << 26usize); + } + } + impl Default for Cfgr1 { + fn default() -> Cfgr1 { + Cfgr1(0) + } + } + #[doc = "external interrupt configuration register 4"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Exticr(pub u32); + impl Exticr { + #[doc = "EXTI12 configuration bits"] + pub fn exti(&self, n: usize) -> u8 { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + val as u8 + } + #[doc = "EXTI12 configuration bits"] + pub fn set_exti(&mut self, n: usize, val: u8) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); + } + } + impl Default for Exticr { + fn default() -> Exticr { + Exticr(0) + } + } + #[doc = "memory remap register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Memrmp(pub u32); + impl Memrmp { + #[doc = "Memory mapping selection"] + pub const fn mem_mode(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x07; + val as u8 + } + #[doc = "Memory mapping selection"] + pub fn set_mem_mode(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); + } + #[doc = "QUADSPI memory mapping swap"] + pub const fn qfs(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "QUADSPI memory mapping swap"] + pub fn set_qfs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Flash Bank mode selection"] + pub const fn fb_mode(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Flash Bank mode selection"] + pub fn set_fb_mode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Memrmp { + fn default() -> Memrmp { + Memrmp(0) + } + } + #[doc = "SKR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Skr(pub u32); + impl Skr { + #[doc = "SRAM2 write protection key for software erase"] + pub const fn key(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "SRAM2 write protection key for software erase"] + pub fn set_key(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + } + impl Default for Skr { + fn default() -> Skr { + Skr(0) + } + } + #[doc = "SCSR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Scsr(pub u32); + impl Scsr { + #[doc = "SRAM2 Erase"] + pub const fn sram2er(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 Erase"] + pub fn set_sram2er(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "SRAM2 busy by erase operation"] + pub const fn sram2bsy(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 busy by erase operation"] + pub fn set_sram2bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + } + impl Default for Scsr { + fn default() -> Scsr { + Scsr(0) + } + } + #[doc = "SWPR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Swpr(pub u32); + impl Swpr { + #[doc = "SRAWM2 write protection."] + pub fn pwp(&self, n: usize) -> bool { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "SRAWM2 write protection."] + pub fn set_pwp(&mut self, n: usize, val: bool) { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Swpr { + fn default() -> Swpr { + Swpr(0) + } + } + } +} pub mod generic { use core::marker::PhantomData; #[derive(Copy, Clone)] @@ -70,7 +5880,1592 @@ pub mod generic { } } } -pub mod syscfg_h7 { +pub mod spi_v2 { + use crate::generic::*; + #[doc = "Serial peripheral interface"] + #[derive(Copy, Clone)] + pub struct Spi(pub *mut u8); + unsafe impl Send for Spi {} + unsafe impl Sync for Spi {} + impl Spi { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "CRC polynomial register"] + pub fn crcpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "RX CRC register"] + pub fn rxcrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "TX CRC register"] + pub fn txcrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "TX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Txcrcr(pub u32); + impl Txcrcr { + #[doc = "Tx CRC register"] + pub const fn tx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Tx CRC register"] + pub fn set_tx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Txcrcr { + fn default() -> Txcrcr { + Txcrcr(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1(pub u32); + impl Cr1 { + #[doc = "Clock phase"] + pub const fn cpha(&self) -> super::vals::Cpha { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Cpha(val as u8) + } + #[doc = "Clock phase"] + pub fn set_cpha(&mut self, val: super::vals::Cpha) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); + } + #[doc = "Clock polarity"] + pub const fn cpol(&self) -> super::vals::Cpol { + let val = (self.0 >> 1usize) & 0x01; + super::vals::Cpol(val as u8) + } + #[doc = "Clock polarity"] + pub fn set_cpol(&mut self, val: super::vals::Cpol) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); + } + #[doc = "Master selection"] + pub const fn mstr(&self) -> super::vals::Mstr { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Mstr(val as u8) + } + #[doc = "Master selection"] + pub fn set_mstr(&mut self, val: super::vals::Mstr) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Baud rate control"] + pub const fn br(&self) -> super::vals::Br { + let val = (self.0 >> 3usize) & 0x07; + super::vals::Br(val as u8) + } + #[doc = "Baud rate control"] + pub fn set_br(&mut self, val: super::vals::Br) { + self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); + } + #[doc = "SPI enable"] + pub const fn spe(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "SPI enable"] + pub fn set_spe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Frame format"] + pub const fn lsbfirst(&self) -> super::vals::Lsbfirst { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Lsbfirst(val as u8) + } + #[doc = "Frame format"] + pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Internal slave select"] + pub const fn ssi(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Internal slave select"] + pub fn set_ssi(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Software slave management"] + pub const fn ssm(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Software slave management"] + pub fn set_ssm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Receive only"] + pub const fn rxonly(&self) -> super::vals::Rxonly { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Rxonly(val as u8) + } + #[doc = "Receive only"] + pub fn set_rxonly(&mut self, val: super::vals::Rxonly) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "CRC length"] + pub const fn crcl(&self) -> super::vals::Crcl { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Crcl(val as u8) + } + #[doc = "CRC length"] + pub fn set_crcl(&mut self, val: super::vals::Crcl) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "CRC transfer next"] + pub const fn crcnext(&self) -> super::vals::Crcnext { + let val = (self.0 >> 12usize) & 0x01; + super::vals::Crcnext(val as u8) + } + #[doc = "CRC transfer next"] + pub fn set_crcnext(&mut self, val: super::vals::Crcnext) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "Hardware CRC calculation enable"] + pub const fn crcen(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Hardware CRC calculation enable"] + pub fn set_crcen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Output enable in bidirectional mode"] + pub const fn bidioe(&self) -> super::vals::Bidioe { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Bidioe(val as u8) + } + #[doc = "Output enable in bidirectional mode"] + pub fn set_bidioe(&mut self, val: super::vals::Bidioe) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + #[doc = "Bidirectional data mode enable"] + pub const fn bidimode(&self) -> super::vals::Bidimode { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Bidimode(val as u8) + } + #[doc = "Bidirectional data mode enable"] + pub fn set_bidimode(&mut self, val: super::vals::Bidimode) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + } + impl Default for Cr1 { + fn default() -> Cr1 { + Cr1(0) + } + } + #[doc = "CRC polynomial register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Crcpr(pub u32); + impl Crcpr { + #[doc = "CRC polynomial register"] + pub const fn crcpoly(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "CRC polynomial register"] + pub fn set_crcpoly(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Crcpr { + fn default() -> Crcpr { + Crcpr(0) + } + } + #[doc = "RX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rxcrcr(pub u32); + impl Rxcrcr { + #[doc = "Rx CRC register"] + pub const fn rx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Rx CRC register"] + pub fn set_rx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Rxcrcr { + fn default() -> Rxcrcr { + Rxcrcr(0) + } + } + #[doc = "data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dr(pub u32); + impl Dr { + #[doc = "Data register"] + pub const fn dr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Data register"] + pub fn set_dr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Dr { + fn default() -> Dr { + Dr(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Receive buffer not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Receive buffer not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Transmit buffer empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Transmit buffer empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "CRC error flag"] + pub const fn crcerr(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "CRC error flag"] + pub fn set_crcerr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Mode fault"] + pub const fn modf(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Mode fault"] + pub fn set_modf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Overrun flag"] + pub const fn ovr(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Overrun flag"] + pub fn set_ovr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Busy flag"] + pub const fn bsy(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Busy flag"] + pub fn set_bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Frame format error"] + pub const fn fre(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Frame format error"] + pub fn set_fre(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "FIFO reception level"] + pub const fn frlvl(&self) -> u8 { + let val = (self.0 >> 9usize) & 0x03; + val as u8 + } + #[doc = "FIFO reception level"] + pub fn set_frlvl(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 9usize)) | (((val as u32) & 0x03) << 9usize); + } + #[doc = "FIFO Transmission Level"] + pub const fn ftlvl(&self) -> u8 { + let val = (self.0 >> 11usize) & 0x03; + val as u8 + } + #[doc = "FIFO Transmission Level"] + pub fn set_ftlvl(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 11usize)) | (((val as u32) & 0x03) << 11usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2(pub u32); + impl Cr2 { + #[doc = "Rx buffer DMA enable"] + pub const fn rxdmaen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Rx buffer DMA enable"] + pub fn set_rxdmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Tx buffer DMA enable"] + pub const fn txdmaen(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Tx buffer DMA enable"] + pub fn set_txdmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "SS output enable"] + pub const fn ssoe(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "SS output enable"] + pub fn set_ssoe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "NSS pulse management"] + pub const fn nssp(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "NSS pulse management"] + pub fn set_nssp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Frame format"] + pub const fn frf(&self) -> super::vals::Frf { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Frf(val as u8) + } + #[doc = "Frame format"] + pub fn set_frf(&mut self, val: super::vals::Frf) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Error interrupt enable"] + pub const fn errie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_errie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "RX buffer not empty interrupt enable"] + pub const fn rxneie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "RX buffer not empty interrupt enable"] + pub fn set_rxneie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Tx buffer empty interrupt enable"] + pub const fn txeie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Tx buffer empty interrupt enable"] + pub fn set_txeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Data size"] + pub const fn ds(&self) -> super::vals::Ds { + let val = (self.0 >> 8usize) & 0x0f; + super::vals::Ds(val as u8) + } + #[doc = "Data size"] + pub fn set_ds(&mut self, val: super::vals::Ds) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); + } + #[doc = "FIFO reception threshold"] + pub const fn frxth(&self) -> super::vals::Frxth { + let val = (self.0 >> 12usize) & 0x01; + super::vals::Frxth(val as u8) + } + #[doc = "FIFO reception threshold"] + pub fn set_frxth(&mut self, val: super::vals::Frxth) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "Last DMA transfer for reception"] + pub const fn ldma_rx(&self) -> super::vals::LdmaRx { + let val = (self.0 >> 13usize) & 0x01; + super::vals::LdmaRx(val as u8) + } + #[doc = "Last DMA transfer for reception"] + pub fn set_ldma_rx(&mut self, val: super::vals::LdmaRx) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val.0 as u32) & 0x01) << 13usize); + } + #[doc = "Last DMA transfer for transmission"] + pub const fn ldma_tx(&self) -> super::vals::LdmaTx { + let val = (self.0 >> 14usize) & 0x01; + super::vals::LdmaTx(val as u8) + } + #[doc = "Last DMA transfer for transmission"] + pub fn set_ldma_tx(&mut self, val: super::vals::LdmaTx) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + } + impl Default for Cr2 { + fn default() -> Cr2 { + Cr2(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ds(pub u8); + impl Ds { + #[doc = "4-bit"] + pub const FOURBIT: Self = Self(0x03); + #[doc = "5-bit"] + pub const FIVEBIT: Self = Self(0x04); + #[doc = "6-bit"] + pub const SIXBIT: Self = Self(0x05); + #[doc = "7-bit"] + pub const SEVENBIT: Self = Self(0x06); + #[doc = "8-bit"] + pub const EIGHTBIT: Self = Self(0x07); + #[doc = "9-bit"] + pub const NINEBIT: Self = Self(0x08); + #[doc = "10-bit"] + pub const TENBIT: Self = Self(0x09); + #[doc = "11-bit"] + pub const ELEVENBIT: Self = Self(0x0a); + #[doc = "12-bit"] + pub const TWELVEBIT: Self = Self(0x0b); + #[doc = "13-bit"] + pub const THIRTEENBIT: Self = Self(0x0c); + #[doc = "14-bit"] + pub const FOURTEENBIT: Self = Self(0x0d); + #[doc = "15-bit"] + pub const FIFTEENBIT: Self = Self(0x0e); + #[doc = "16-bit"] + pub const SIXTEENBIT: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRSTEDGE: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECONDEDGE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct LdmaTx(pub u8); + impl LdmaTx { + #[doc = "Number of data to transfer for transmit is even"] + pub const EVEN: Self = Self(0); + #[doc = "Number of data to transfer for transmit is odd"] + pub const ODD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frxth(pub u8); + impl Frxth { + #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"] + pub const HALF: Self = Self(0); + #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"] + pub const QUARTER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpol(pub u8); + impl Cpol { + #[doc = "CK to 0 when idle"] + pub const IDLELOW: Self = Self(0); + #[doc = "CK to 1 when idle"] + pub const IDLEHIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frf(pub u8); + impl Frf { + #[doc = "SPI Motorola mode"] + pub const MOTOROLA: Self = Self(0); + #[doc = "SPI TI mode"] + pub const TI: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Crcl(pub u8); + impl Crcl { + #[doc = "8-bit CRC length"] + pub const EIGHTBIT: Self = Self(0); + #[doc = "16-bit CRC length"] + pub const SIXTEENBIT: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidimode(pub u8); + impl Bidimode { + #[doc = "2-line unidirectional data mode selected"] + pub const UNIDIRECTIONAL: Self = Self(0); + #[doc = "1-line bidirectional data mode selected"] + pub const BIDIRECTIONAL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mstr(pub u8); + impl Mstr { + #[doc = "Slave configuration"] + pub const SLAVE: Self = Self(0); + #[doc = "Master configuration"] + pub const MASTER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct LdmaRx(pub u8); + impl LdmaRx { + #[doc = "Number of data to transfer for receive is even"] + pub const EVEN: Self = Self(0); + #[doc = "Number of data to transfer for receive is odd"] + pub const ODD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ftlvlr(pub u8); + impl Ftlvlr { + #[doc = "Tx FIFO Empty"] + pub const EMPTY: Self = Self(0); + #[doc = "Tx 1/4 FIFO"] + pub const QUARTER: Self = Self(0x01); + #[doc = "Tx 1/2 FIFO"] + pub const HALF: Self = Self(0x02); + #[doc = "Tx FIFO full"] + pub const FULL: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Br(pub u8); + impl Br { + #[doc = "f_PCLK / 2"] + pub const DIV2: Self = Self(0); + #[doc = "f_PCLK / 4"] + pub const DIV4: Self = Self(0x01); + #[doc = "f_PCLK / 8"] + pub const DIV8: Self = Self(0x02); + #[doc = "f_PCLK / 16"] + pub const DIV16: Self = Self(0x03); + #[doc = "f_PCLK / 32"] + pub const DIV32: Self = Self(0x04); + #[doc = "f_PCLK / 64"] + pub const DIV64: Self = Self(0x05); + #[doc = "f_PCLK / 128"] + pub const DIV128: Self = Self(0x06); + #[doc = "f_PCLK / 256"] + pub const DIV256: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Crcnext(pub u8); + impl Crcnext { + #[doc = "Next transmit value is from Tx buffer"] + pub const TXBUFFER: Self = Self(0); + #[doc = "Next transmit value is from Tx CRC register"] + pub const CRC: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidioe(pub u8); + impl Bidioe { + #[doc = "Output disabled (receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0); + #[doc = "Output enabled (transmit-only mode)"] + pub const OUTPUTENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frer(pub u8); + impl Frer { + #[doc = "No frame format error"] + pub const NOERROR: Self = Self(0); + #[doc = "A frame format error occurred"] + pub const ERROR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lsbfirst(pub u8); + impl Lsbfirst { + #[doc = "Data is transmitted/received with the MSB first"] + pub const MSBFIRST: Self = Self(0); + #[doc = "Data is transmitted/received with the LSB first"] + pub const LSBFIRST: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frlvlr(pub u8); + impl Frlvlr { + #[doc = "Rx FIFO Empty"] + pub const EMPTY: Self = Self(0); + #[doc = "Rx 1/4 FIFO"] + pub const QUARTER: Self = Self(0x01); + #[doc = "Rx 1/2 FIFO"] + pub const HALF: Self = Self(0x02); + #[doc = "Rx FIFO full"] + pub const FULL: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rxonly(pub u8); + impl Rxonly { + #[doc = "Full duplex (Transmit and receive)"] + pub const FULLDUPLEX: Self = Self(0); + #[doc = "Output disabled (Receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0x01); + } + } +} +pub mod usart_v1 { + use crate::generic::*; + #[doc = "Universal asynchronous receiver transmitter"] + #[derive(Copy, Clone)] + pub struct Uart(pub *mut u8); + unsafe impl Send for Uart {} + unsafe impl Sync for Uart {} + impl Uart { + #[doc = "Status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Baud rate register"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Control register 3"] + pub fn cr3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + } + #[doc = "Universal synchronous asynchronous receiver transmitter"] + #[derive(Copy, Clone)] + pub struct Usart(pub *mut u8); + unsafe impl Send for Usart {} + unsafe impl Sync for Usart {} + impl Usart { + #[doc = "Status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Baud rate register"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Control register 3"] + pub fn cr3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "Guard time and prescaler register"] + pub fn gtpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "Status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Parity error"] + pub const fn pe(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Parity error"] + pub fn set_pe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Framing error"] + pub const fn fe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Framing error"] + pub fn set_fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Noise error flag"] + pub const fn ne(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Noise error flag"] + pub fn set_ne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Overrun error"] + pub const fn ore(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Overrun error"] + pub fn set_ore(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE line detected"] + pub const fn idle(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE line detected"] + pub fn set_idle(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Read data register not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Read data register not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete"] + pub const fn tc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete"] + pub fn set_tc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Transmit data register empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Transmit data register empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "LIN break detection flag"] + pub const fn lbd(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection flag"] + pub fn set_lbd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + #[doc = "Control register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr3(pub u32); + impl Cr3 { + #[doc = "Error interrupt enable"] + pub const fn eie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_eie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "IrDA mode enable"] + pub const fn iren(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "IrDA mode enable"] + pub fn set_iren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "IrDA low-power"] + pub const fn irlp(&self) -> super::vals::Irlp { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Irlp(val as u8) + } + #[doc = "IrDA low-power"] + pub fn set_irlp(&mut self, val: super::vals::Irlp) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Half-duplex selection"] + pub const fn hdsel(&self) -> super::vals::Hdsel { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Hdsel(val as u8) + } + #[doc = "Half-duplex selection"] + pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "DMA enable receiver"] + pub const fn dmar(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "DMA enable receiver"] + pub fn set_dmar(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "DMA enable transmitter"] + pub const fn dmat(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "DMA enable transmitter"] + pub fn set_dmat(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for Cr3 { + fn default() -> Cr3 { + Cr3(0) + } + } + #[doc = "Status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrUsart(pub u32); + impl SrUsart { + #[doc = "Parity error"] + pub const fn pe(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Parity error"] + pub fn set_pe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Framing error"] + pub const fn fe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Framing error"] + pub fn set_fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Noise error flag"] + pub const fn ne(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Noise error flag"] + pub fn set_ne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Overrun error"] + pub const fn ore(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Overrun error"] + pub fn set_ore(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE line detected"] + pub const fn idle(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE line detected"] + pub fn set_idle(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Read data register not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Read data register not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete"] + pub const fn tc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete"] + pub fn set_tc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Transmit data register empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Transmit data register empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "LIN break detection flag"] + pub const fn lbd(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection flag"] + pub fn set_lbd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "CTS flag"] + pub const fn cts(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "CTS flag"] + pub fn set_cts(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + } + impl Default for SrUsart { + fn default() -> SrUsart { + SrUsart(0) + } + } + #[doc = "Control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Usart(pub u32); + impl Cr2Usart { + #[doc = "Address of the USART node"] + pub const fn add(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Address of the USART node"] + pub fn set_add(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "lin break detection length"] + pub const fn lbdl(&self) -> super::vals::Lbdl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Lbdl(val as u8) + } + #[doc = "lin break detection length"] + pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "LIN break detection interrupt enable"] + pub const fn lbdie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection interrupt enable"] + pub fn set_lbdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Last bit clock pulse"] + pub const fn lbcl(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Last bit clock pulse"] + pub fn set_lbcl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Clock phase"] + pub const fn cpha(&self) -> super::vals::Cpha { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Cpha(val as u8) + } + #[doc = "Clock phase"] + pub fn set_cpha(&mut self, val: super::vals::Cpha) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Clock polarity"] + pub const fn cpol(&self) -> super::vals::Cpol { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Cpol(val as u8) + } + #[doc = "Clock polarity"] + pub fn set_cpol(&mut self, val: super::vals::Cpol) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Clock enable"] + pub const fn clken(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Clock enable"] + pub fn set_clken(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "STOP bits"] + pub const fn stop(&self) -> super::vals::Stop { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Stop(val as u8) + } + #[doc = "STOP bits"] + pub fn set_stop(&mut self, val: super::vals::Stop) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "LIN mode enable"] + pub const fn linen(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "LIN mode enable"] + pub fn set_linen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for Cr2Usart { + fn default() -> Cr2Usart { + Cr2Usart(0) + } + } + #[doc = "Control register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr3Usart(pub u32); + impl Cr3Usart { + #[doc = "Error interrupt enable"] + pub const fn eie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_eie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "IrDA mode enable"] + pub const fn iren(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "IrDA mode enable"] + pub fn set_iren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "IrDA low-power"] + pub const fn irlp(&self) -> super::vals::Irlp { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Irlp(val as u8) + } + #[doc = "IrDA low-power"] + pub fn set_irlp(&mut self, val: super::vals::Irlp) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Half-duplex selection"] + pub const fn hdsel(&self) -> super::vals::Hdsel { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Hdsel(val as u8) + } + #[doc = "Half-duplex selection"] + pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Smartcard NACK enable"] + pub const fn nack(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Smartcard NACK enable"] + pub fn set_nack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Smartcard mode enable"] + pub const fn scen(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Smartcard mode enable"] + pub fn set_scen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "DMA enable receiver"] + pub const fn dmar(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "DMA enable receiver"] + pub fn set_dmar(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "DMA enable transmitter"] + pub const fn dmat(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "DMA enable transmitter"] + pub fn set_dmat(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "RTS enable"] + pub const fn rtse(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "RTS enable"] + pub fn set_rtse(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "CTS enable"] + pub const fn ctse(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "CTS enable"] + pub fn set_ctse(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "CTS interrupt enable"] + pub const fn ctsie(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "CTS interrupt enable"] + pub fn set_ctsie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + } + impl Default for Cr3Usart { + fn default() -> Cr3Usart { + Cr3Usart(0) + } + } + #[doc = "Data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dr(pub u32); + impl Dr { + #[doc = "Data value"] + pub const fn dr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x01ff; + val as u16 + } + #[doc = "Data value"] + pub fn set_dr(&mut self, val: u16) { + self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize); + } + } + impl Default for Dr { + fn default() -> Dr { + Dr(0) + } + } + #[doc = "Control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2(pub u32); + impl Cr2 { + #[doc = "Address of the USART node"] + pub const fn add(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Address of the USART node"] + pub fn set_add(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "lin break detection length"] + pub const fn lbdl(&self) -> super::vals::Lbdl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Lbdl(val as u8) + } + #[doc = "lin break detection length"] + pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "LIN break detection interrupt enable"] + pub const fn lbdie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection interrupt enable"] + pub fn set_lbdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "STOP bits"] + pub const fn stop(&self) -> super::vals::Stop { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Stop(val as u8) + } + #[doc = "STOP bits"] + pub fn set_stop(&mut self, val: super::vals::Stop) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "LIN mode enable"] + pub const fn linen(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "LIN mode enable"] + pub fn set_linen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for Cr2 { + fn default() -> Cr2 { + Cr2(0) + } + } + #[doc = "Baud rate register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Brr(pub u32); + impl Brr { + #[doc = "fraction of USARTDIV"] + pub const fn div_fraction(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "fraction of USARTDIV"] + pub fn set_div_fraction(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "mantissa of USARTDIV"] + pub const fn div_mantissa(&self) -> u16 { + let val = (self.0 >> 4usize) & 0x0fff; + val as u16 + } + #[doc = "mantissa of USARTDIV"] + pub fn set_div_mantissa(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize); + } + } + impl Default for Brr { + fn default() -> Brr { + Brr(0) + } + } + #[doc = "Control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1(pub u32); + impl Cr1 { + #[doc = "Send break"] + pub const fn sbk(&self) -> super::vals::Sbk { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Sbk(val as u8) + } + #[doc = "Send break"] + pub fn set_sbk(&mut self, val: super::vals::Sbk) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); + } + #[doc = "Receiver wakeup"] + pub const fn rwu(&self) -> super::vals::Rwu { + let val = (self.0 >> 1usize) & 0x01; + super::vals::Rwu(val as u8) + } + #[doc = "Receiver wakeup"] + pub fn set_rwu(&mut self, val: super::vals::Rwu) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); + } + #[doc = "Receiver enable"] + pub const fn re(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Receiver enable"] + pub fn set_re(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Transmitter enable"] + pub const fn te(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Transmitter enable"] + pub fn set_te(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE interrupt enable"] + pub const fn idleie(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE interrupt enable"] + pub fn set_idleie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "RXNE interrupt enable"] + pub const fn rxneie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "RXNE interrupt enable"] + pub fn set_rxneie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "TXE interrupt enable"] + pub const fn txeie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "TXE interrupt enable"] + pub fn set_txeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "PE interrupt enable"] + pub const fn peie(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "PE interrupt enable"] + pub fn set_peie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Parity selection"] + pub const fn ps(&self) -> super::vals::Ps { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Ps(val as u8) + } + #[doc = "Parity selection"] + pub fn set_ps(&mut self, val: super::vals::Ps) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Parity control enable"] + pub const fn pce(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Parity control enable"] + pub fn set_pce(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Wakeup method"] + pub const fn wake(&self) -> super::vals::Wake { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Wake(val as u8) + } + #[doc = "Wakeup method"] + pub fn set_wake(&mut self, val: super::vals::Wake) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "Word length"] + pub const fn m(&self) -> super::vals::M { + let val = (self.0 >> 12usize) & 0x01; + super::vals::M(val as u8) + } + #[doc = "Word length"] + pub fn set_m(&mut self, val: super::vals::M) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "USART enable"] + pub const fn ue(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "USART enable"] + pub fn set_ue(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + } + impl Default for Cr1 { + fn default() -> Cr1 { + Cr1(0) + } + } + #[doc = "Guard time and prescaler register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Gtpr(pub u32); + impl Gtpr { + #[doc = "Prescaler value"] + pub const fn psc(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Prescaler value"] + pub fn set_psc(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Guard time value"] + pub const fn gt(&self) -> u8 { + let val = (self.0 >> 8usize) & 0xff; + val as u8 + } + #[doc = "Guard time value"] + pub fn set_gt(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); + } + } + impl Default for Gtpr { + fn default() -> Gtpr { + Gtpr(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Wake(pub u8); + impl Wake { + #[doc = "USART wakeup on idle line"] + pub const IDLELINE: Self = Self(0); + #[doc = "USART wakeup on address mark"] + pub const ADDRESSMARK: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct M(pub u8); + impl M { + #[doc = "8 data bits"] + pub const M8: Self = Self(0); + #[doc = "9 data bits"] + pub const M9: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ps(pub u8); + impl Ps { + #[doc = "Even parity"] + pub const EVEN: Self = Self(0); + #[doc = "Odd parity"] + pub const ODD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Sbk(pub u8); + impl Sbk { + #[doc = "No break character is transmitted"] + pub const NOBREAK: Self = Self(0); + #[doc = "Break character transmitted"] + pub const BREAK: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Hdsel(pub u8); + impl Hdsel { + #[doc = "Half duplex mode is not selected"] + pub const FULLDUPLEX: Self = Self(0); + #[doc = "Half duplex mode is selected"] + pub const HALFDUPLEX: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rwu(pub u8); + impl Rwu { + #[doc = "Receiver in active mode"] + pub const ACTIVE: Self = Self(0); + #[doc = "Receiver in mute mode"] + pub const MUTE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpol(pub u8); + impl Cpol { + #[doc = "Steady low value on CK pin outside transmission window"] + pub const LOW: Self = Self(0); + #[doc = "Steady high value on CK pin outside transmission window"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Stop(pub u8); + impl Stop { + #[doc = "1 stop bit"] + pub const STOP1: Self = Self(0); + #[doc = "0.5 stop bits"] + pub const STOP0P5: Self = Self(0x01); + #[doc = "2 stop bits"] + pub const STOP2: Self = Self(0x02); + #[doc = "1.5 stop bits"] + pub const STOP1P5: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRST: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECOND: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Irlp(pub u8); + impl Irlp { + #[doc = "Normal mode"] + pub const NORMAL: Self = Self(0); + #[doc = "Low-power mode"] + pub const LOWPOWER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lbdl(pub u8); + impl Lbdl { + #[doc = "10-bit break detection"] + pub const LBDL10: Self = Self(0); + #[doc = "11-bit break detection"] + pub const LBDL11: Self = Self(0x01); + } + } +} +pub mod syscfg_f4 { use crate::generic::*; #[doc = "System configuration controller"] #[derive(Copy, Clone)] @@ -78,615 +7473,124 @@ pub mod syscfg_h7 { unsafe impl Send for Syscfg {} unsafe impl Sync for Syscfg {} impl Syscfg { + #[doc = "memory remap register"] + pub fn memrm(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } #[doc = "peripheral mode configuration register"] - pub fn pmcr(self) -> Reg { + pub fn pmc(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(4usize)) } } - #[doc = "external interrupt configuration register 1"] + #[doc = "external interrupt configuration register"] pub fn exticr(self, n: usize) -> Reg { assert!(n < 4usize); unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } } - #[doc = "compensation cell control/status register"] - pub fn cccsr(self) -> Reg { + #[doc = "Compensation cell control register"] + pub fn cmpcr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(32usize)) } } - #[doc = "SYSCFG compensation cell value register"] - pub fn ccvr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - #[doc = "SYSCFG compensation cell code register"] - pub fn cccr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(40usize)) } - } - #[doc = "SYSCFG power control register"] - pub fn pwrcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(44usize)) } - } - #[doc = "SYSCFG package register"] - pub fn pkgr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(292usize)) } - } - #[doc = "SYSCFG user register 0"] - pub fn ur0(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(768usize)) } - } - #[doc = "SYSCFG user register 2"] - pub fn ur2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(776usize)) } - } - #[doc = "SYSCFG user register 3"] - pub fn ur3(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(780usize)) } - } - #[doc = "SYSCFG user register 4"] - pub fn ur4(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(784usize)) } - } - #[doc = "SYSCFG user register 5"] - pub fn ur5(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(788usize)) } - } - #[doc = "SYSCFG user register 6"] - pub fn ur6(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(792usize)) } - } - #[doc = "SYSCFG user register 7"] - pub fn ur7(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(796usize)) } - } - #[doc = "SYSCFG user register 8"] - pub fn ur8(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(800usize)) } - } - #[doc = "SYSCFG user register 9"] - pub fn ur9(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(804usize)) } - } - #[doc = "SYSCFG user register 10"] - pub fn ur10(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(808usize)) } - } - #[doc = "SYSCFG user register 11"] - pub fn ur11(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(812usize)) } - } - #[doc = "SYSCFG user register 12"] - pub fn ur12(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(816usize)) } - } - #[doc = "SYSCFG user register 13"] - pub fn ur13(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(820usize)) } - } - #[doc = "SYSCFG user register 14"] - pub fn ur14(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(824usize)) } - } - #[doc = "SYSCFG user register 15"] - pub fn ur15(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(828usize)) } - } - #[doc = "SYSCFG user register 16"] - pub fn ur16(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(832usize)) } - } - #[doc = "SYSCFG user register 17"] - pub fn ur17(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(836usize)) } - } } pub mod regs { use crate::generic::*; - #[doc = "SYSCFG power control register"] + #[doc = "memory remap register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pwrcr(pub u32); - impl Pwrcr { - #[doc = "Overdrive enable"] - pub const fn oden(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; + pub struct Memrm(pub u32); + impl Memrm { + #[doc = "Memory mapping selection"] + pub const fn mem_mode(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x07; val as u8 } - #[doc = "Overdrive enable"] - pub fn set_oden(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + #[doc = "Memory mapping selection"] + pub fn set_mem_mode(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); } - } - impl Default for Pwrcr { - fn default() -> Pwrcr { - Pwrcr(0) - } - } - #[doc = "SYSCFG user register 0"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur0(pub u32); - impl Ur0 { - #[doc = "Bank Swap"] - pub const fn bks(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; + #[doc = "Flash bank mode selection"] + pub const fn fb_mode(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "Bank Swap"] - pub fn set_bks(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + #[doc = "Flash bank mode selection"] + pub fn set_fb_mode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } - #[doc = "Readout protection"] - pub const fn rdp(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; + #[doc = "FMC memory mapping swap"] + pub const fn swp_fmc(&self) -> u8 { + let val = (self.0 >> 10usize) & 0x03; val as u8 } - #[doc = "Readout protection"] - pub fn set_rdp(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); + #[doc = "FMC memory mapping swap"] + pub fn set_swp_fmc(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize); } } - impl Default for Ur0 { - fn default() -> Ur0 { - Ur0(0) - } - } - #[doc = "SYSCFG user register 14"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur14(pub u32); - impl Ur14 { - #[doc = "D1 Stop Reset"] - pub const fn d1stprst(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "D1 Stop Reset"] - pub fn set_d1stprst(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for Ur14 { - fn default() -> Ur14 { - Ur14(0) - } - } - #[doc = "SYSCFG user register 5"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur5(pub u32); - impl Ur5 { - #[doc = "Mass erase secured area disabled for bank 1"] - pub const fn mesad_1(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Mass erase secured area disabled for bank 1"] - pub fn set_mesad_1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Write protection for flash bank 1"] - pub const fn wrpn_1(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Write protection for flash bank 1"] - pub fn set_wrpn_1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } - } - impl Default for Ur5 { - fn default() -> Ur5 { - Ur5(0) - } - } - #[doc = "SYSCFG user register 8"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur8(pub u32); - impl Ur8 { - #[doc = "Mass erase protected area disabled for bank 2"] - pub const fn mepad_2(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Mass erase protected area disabled for bank 2"] - pub fn set_mepad_2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Mass erase secured area disabled for bank 2"] - pub const fn mesad_2(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Mass erase secured area disabled for bank 2"] - pub fn set_mesad_2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur8 { - fn default() -> Ur8 { - Ur8(0) + impl Default for Memrm { + fn default() -> Memrm { + Memrm(0) } } #[doc = "peripheral mode configuration register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pmcr(pub u32); - impl Pmcr { - #[doc = "I2C1 Fm+"] - pub const fn i2c1fmp(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "I2C1 Fm+"] - pub fn set_i2c1fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "I2C2 Fm+"] - pub const fn i2c2fmp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "I2C2 Fm+"] - pub fn set_i2c2fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "I2C3 Fm+"] - pub const fn i2c3fmp(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "I2C3 Fm+"] - pub fn set_i2c3fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "I2C4 Fm+"] - pub const fn i2c4fmp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "I2C4 Fm+"] - pub fn set_i2c4fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "PB(6) Fm+"] - pub const fn pb6fmp(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "PB(6) Fm+"] - pub fn set_pb6fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "PB(7) Fast Mode Plus"] - pub const fn pb7fmp(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "PB(7) Fast Mode Plus"] - pub fn set_pb7fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "PB(8) Fast Mode Plus"] - pub const fn pb8fmp(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "PB(8) Fast Mode Plus"] - pub fn set_pb8fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "PB(9) Fm+"] - pub const fn pb9fmp(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "PB(9) Fm+"] - pub fn set_pb9fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Booster Enable"] - pub const fn booste(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Booster Enable"] - pub fn set_booste(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Analog switch supply voltage selection"] - pub const fn boostvddsel(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Analog switch supply voltage selection"] - pub fn set_boostvddsel(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Ethernet PHY Interface Selection"] - pub const fn epis(&self) -> u8 { - let val = (self.0 >> 21usize) & 0x07; - val as u8 - } - #[doc = "Ethernet PHY Interface Selection"] - pub fn set_epis(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 21usize)) | (((val as u32) & 0x07) << 21usize); - } - #[doc = "PA0 Switch Open"] - pub const fn pa0so(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[doc = "PA0 Switch Open"] - pub fn set_pa0so(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[doc = "PA1 Switch Open"] - pub const fn pa1so(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[doc = "PA1 Switch Open"] - pub fn set_pa1so(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[doc = "PC2 Switch Open"] - pub const fn pc2so(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[doc = "PC2 Switch Open"] - pub fn set_pc2so(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[doc = "PC3 Switch Open"] - pub const fn pc3so(&self) -> bool { - let val = (self.0 >> 27usize) & 0x01; - val != 0 - } - #[doc = "PC3 Switch Open"] - pub fn set_pc3so(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); - } - } - impl Default for Pmcr { - fn default() -> Pmcr { - Pmcr(0) - } - } - #[doc = "SYSCFG user register 12"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur12(pub u32); - impl Ur12 { - #[doc = "Secure mode"] - pub const fn secure(&self) -> bool { + pub struct Pmc(pub u32); + impl Pmc { + #[doc = "ADC1DC2"] + pub const fn adc1dc2(&self) -> bool { let val = (self.0 >> 16usize) & 0x01; val != 0 } - #[doc = "Secure mode"] - pub fn set_secure(&mut self, val: bool) { + #[doc = "ADC1DC2"] + pub fn set_adc1dc2(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } - } - impl Default for Ur12 { - fn default() -> Ur12 { - Ur12(0) - } - } - #[doc = "SYSCFG user register 4"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur4(pub u32); - impl Ur4 { - #[doc = "Mass Erase Protected Area Disabled for bank 1"] - pub const fn mepad_1(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; + #[doc = "ADC2DC2"] + pub const fn adc2dc2(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; val != 0 } - #[doc = "Mass Erase Protected Area Disabled for bank 1"] - pub fn set_mepad_1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + #[doc = "ADC2DC2"] + pub fn set_adc2dc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); } - } - impl Default for Ur4 { - fn default() -> Ur4 { - Ur4(0) - } - } - #[doc = "SYSCFG compensation cell value register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ccvr(pub u32); - impl Ccvr { - #[doc = "NMOS compensation value"] - pub const fn ncv(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "NMOS compensation value"] - pub fn set_ncv(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "PMOS compensation value"] - pub const fn pcv(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 - } - #[doc = "PMOS compensation value"] - pub fn set_pcv(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); - } - } - impl Default for Ccvr { - fn default() -> Ccvr { - Ccvr(0) - } - } - #[doc = "SYSCFG user register 13"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur13(pub u32); - impl Ur13 { - #[doc = "Secured DTCM RAM Size"] - pub const fn sdrs(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x03; - val as u8 - } - #[doc = "Secured DTCM RAM Size"] - pub fn set_sdrs(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); - } - #[doc = "D1 Standby reset"] - pub const fn d1sbrst(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; + #[doc = "ADC3DC2"] + pub const fn adc3dc2(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; val != 0 } - #[doc = "D1 Standby reset"] - pub fn set_d1sbrst(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + #[doc = "ADC3DC2"] + pub fn set_adc3dc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); } - } - impl Default for Ur13 { - fn default() -> Ur13 { - Ur13(0) - } - } - #[doc = "compensation cell control/status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cccsr(pub u32); - impl Cccsr { - #[doc = "enable"] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; + #[doc = "Ethernet PHY interface selection"] + pub const fn mii_rmii_sel(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; val != 0 } - #[doc = "enable"] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Code selection"] - pub const fn cs(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Code selection"] - pub fn set_cs(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Compensation cell ready flag"] - pub const fn ready(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Compensation cell ready flag"] - pub fn set_ready(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "High-speed at low-voltage"] - pub const fn hslv(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "High-speed at low-voltage"] - pub fn set_hslv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + #[doc = "Ethernet PHY interface selection"] + pub fn set_mii_rmii_sel(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); } } - impl Default for Cccsr { - fn default() -> Cccsr { - Cccsr(0) + impl Default for Pmc { + fn default() -> Pmc { + Pmc(0) } } - #[doc = "SYSCFG user register 6"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur6(pub u32); - impl Ur6 { - #[doc = "Protected area start address for bank 1"] - pub const fn pa_beg_1(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Protected area start address for bank 1"] - pub fn set_pa_beg_1(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Protected area end address for bank 1"] - pub const fn pa_end_1(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x0fff; - val as u16 - } - #[doc = "Protected area end address for bank 1"] - pub fn set_pa_end_1(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); - } - } - impl Default for Ur6 { - fn default() -> Ur6 { - Ur6(0) - } - } - #[doc = "SYSCFG package register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pkgr(pub u32); - impl Pkgr { - #[doc = "Package"] - pub const fn pkg(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Package"] - pub fn set_pkg(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - } - impl Default for Pkgr { - fn default() -> Pkgr { - Pkgr(0) - } - } - #[doc = "SYSCFG user register 10"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur10(pub u32); - impl Ur10 { - #[doc = "Protected area end address for bank 2"] - pub const fn pa_end_2(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Protected area end address for bank 2"] - pub fn set_pa_end_2(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Secured area start address for bank 2"] - pub const fn sa_beg_2(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x0fff; - val as u16 - } - #[doc = "Secured area start address for bank 2"] - pub fn set_sa_beg_2(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); - } - } - impl Default for Ur10 { - fn default() -> Ur10 { - Ur10(0) - } - } - #[doc = "external interrupt configuration register 2"] + #[doc = "external interrupt configuration register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Exticr(pub u32); impl Exticr { - #[doc = "EXTI x configuration (x = 4 to 7)"] + #[doc = "EXTI x configuration"] pub fn exti(&self, n: usize) -> u8 { assert!(n < 4usize); let offs = 0usize + n * 4usize; let val = (self.0 >> offs) & 0x0f; val as u8 } - #[doc = "EXTI x configuration (x = 4 to 7)"] + #[doc = "EXTI x configuration"] pub fn set_exti(&mut self, n: usize, val: u8) { assert!(n < 4usize); let offs = 0usize + n * 4usize; @@ -698,465 +7602,35 @@ pub mod syscfg_h7 { Exticr(0) } } - #[doc = "SYSCFG user register 15"] + #[doc = "Compensation cell control register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur15(pub u32); - impl Ur15 { - #[doc = "Freeze independent watchdog in Standby mode"] - pub const fn fziwdgstb(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Freeze independent watchdog in Standby mode"] - pub fn set_fziwdgstb(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur15 { - fn default() -> Ur15 { - Ur15(0) - } - } - #[doc = "SYSCFG user register 3"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur3(pub u32); - impl Ur3 { - #[doc = "Boot Address 1"] - pub const fn boot_add1(&self) -> u16 { - let val = (self.0 >> 16usize) & 0xffff; - val as u16 - } - #[doc = "Boot Address 1"] - pub fn set_boot_add1(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); - } - } - impl Default for Ur3 { - fn default() -> Ur3 { - Ur3(0) - } - } - #[doc = "SYSCFG user register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur2(pub u32); - impl Ur2 { - #[doc = "BOR_LVL Brownout Reset Threshold Level"] - pub const fn borh(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x03; - val as u8 - } - #[doc = "BOR_LVL Brownout Reset Threshold Level"] - pub fn set_borh(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); - } - #[doc = "Boot Address 0"] - pub const fn boot_add0(&self) -> u16 { - let val = (self.0 >> 16usize) & 0xffff; - val as u16 - } - #[doc = "Boot Address 0"] - pub fn set_boot_add0(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); - } - } - impl Default for Ur2 { - fn default() -> Ur2 { - Ur2(0) - } - } - #[doc = "SYSCFG user register 17"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur17(pub u32); - impl Ur17 { - #[doc = "I/O high speed / low voltage"] - pub const fn io_hslv(&self) -> bool { + pub struct Cmpcr(pub u32); + impl Cmpcr { + #[doc = "Compensation cell power-down"] + pub const fn cmp_pd(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "I/O high speed / low voltage"] - pub fn set_io_hslv(&mut self, val: bool) { + #[doc = "Compensation cell power-down"] + pub fn set_cmp_pd(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - } - impl Default for Ur17 { - fn default() -> Ur17 { - Ur17(0) - } - } - #[doc = "SYSCFG user register 9"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur9(pub u32); - impl Ur9 { - #[doc = "Write protection for flash bank 2"] - pub const fn wrpn_2(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Write protection for flash bank 2"] - pub fn set_wrpn_2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - #[doc = "Protected area start address for bank 2"] - pub const fn pa_beg_2(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x0fff; - val as u16 - } - #[doc = "Protected area start address for bank 2"] - pub fn set_pa_beg_2(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); - } - } - impl Default for Ur9 { - fn default() -> Ur9 { - Ur9(0) - } - } - #[doc = "SYSCFG compensation cell code register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cccr(pub u32); - impl Cccr { - #[doc = "NMOS compensation code"] - pub const fn ncc(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "NMOS compensation code"] - pub fn set_ncc(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "PMOS compensation code"] - pub const fn pcc(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 - } - #[doc = "PMOS compensation code"] - pub fn set_pcc(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); - } - } - impl Default for Cccr { - fn default() -> Cccr { - Cccr(0) - } - } - #[doc = "SYSCFG user register 11"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur11(pub u32); - impl Ur11 { - #[doc = "Secured area end address for bank 2"] - pub const fn sa_end_2(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Secured area end address for bank 2"] - pub fn set_sa_end_2(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Independent Watchdog 1 mode"] - pub const fn iwdg1m(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; + #[doc = "READY"] + pub const fn ready(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "Independent Watchdog 1 mode"] - pub fn set_iwdg1m(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + #[doc = "READY"] + pub fn set_ready(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } } - impl Default for Ur11 { - fn default() -> Ur11 { - Ur11(0) + impl Default for Cmpcr { + fn default() -> Cmpcr { + Cmpcr(0) } } - #[doc = "SYSCFG user register 16"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur16(pub u32); - impl Ur16 { - #[doc = "Freeze independent watchdog in Stop mode"] - pub const fn fziwdgstp(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Freeze independent watchdog in Stop mode"] - pub fn set_fziwdgstp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Private key programmed"] - pub const fn pkp(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Private key programmed"] - pub fn set_pkp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur16 { - fn default() -> Ur16 { - Ur16(0) - } - } - #[doc = "SYSCFG user register 7"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur7(pub u32); - impl Ur7 { - #[doc = "Secured area start address for bank 1"] - pub const fn sa_beg_1(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Secured area start address for bank 1"] - pub fn set_sa_beg_1(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Secured area end address for bank 1"] - pub const fn sa_end_1(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x0fff; - val as u16 - } - #[doc = "Secured area end address for bank 1"] - pub fn set_sa_end_1(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); - } - } - impl Default for Ur7 { - fn default() -> Ur7 { - Ur7(0) - } - } - } -} -pub mod exti_v1 { - use crate::generic::*; - #[doc = "External interrupt/event controller"] - #[derive(Copy, Clone)] - pub struct Exti(pub *mut u8); - unsafe impl Send for Exti {} - unsafe impl Sync for Exti {} - impl Exti { - #[doc = "Interrupt mask register (EXTI_IMR)"] - pub fn imr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "Event mask register (EXTI_EMR)"] - pub fn emr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "Rising Trigger selection register (EXTI_RTSR)"] - pub fn rtsr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "Falling Trigger selection register (EXTI_FTSR)"] - pub fn ftsr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "Software interrupt event register (EXTI_SWIER)"] - pub fn swier(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "Pending register (EXTI_PR)"] - pub fn pr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "Falling Trigger selection register (EXTI_FTSR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ftsr(pub u32); - impl Ftsr { - #[doc = "Falling trigger event configuration of line 0"] - pub fn tr(&self, n: usize) -> super::vals::Tr { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Tr(val as u8) - } - #[doc = "Falling trigger event configuration of line 0"] - pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Ftsr { - fn default() -> Ftsr { - Ftsr(0) - } - } - #[doc = "Event mask register (EXTI_EMR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Emr(pub u32); - impl Emr { - #[doc = "Event Mask on line 0"] - pub fn mr(&self, n: usize) -> super::vals::Mr { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Mr(val as u8) - } - #[doc = "Event Mask on line 0"] - pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Emr { - fn default() -> Emr { - Emr(0) - } - } - #[doc = "Pending register (EXTI_PR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pr(pub u32); - impl Pr { - #[doc = "Pending bit 0"] - pub fn pr(&self, n: usize) -> bool { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Pending bit 0"] - pub fn set_pr(&mut self, n: usize, val: bool) { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Pr { - fn default() -> Pr { - Pr(0) - } - } - #[doc = "Software interrupt event register (EXTI_SWIER)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Swier(pub u32); - impl Swier { - #[doc = "Software Interrupt on line 0"] - pub fn swier(&self, n: usize) -> bool { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Software Interrupt on line 0"] - pub fn set_swier(&mut self, n: usize, val: bool) { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Swier { - fn default() -> Swier { - Swier(0) - } - } - #[doc = "Interrupt mask register (EXTI_IMR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Imr(pub u32); - impl Imr { - #[doc = "Interrupt Mask on line 0"] - pub fn mr(&self, n: usize) -> super::vals::Mr { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Mr(val as u8) - } - #[doc = "Interrupt Mask on line 0"] - pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Imr { - fn default() -> Imr { - Imr(0) - } - } - #[doc = "Rising Trigger selection register (EXTI_RTSR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Rtsr(pub u32); - impl Rtsr { - #[doc = "Rising trigger event configuration of line 0"] - pub fn tr(&self, n: usize) -> super::vals::Tr { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Tr(val as u8) - } - #[doc = "Rising trigger event configuration of line 0"] - pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Rtsr { - fn default() -> Rtsr { - Rtsr(0) - } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Prr(pub u8); - impl Prr { - #[doc = "No trigger request occurred"] - pub const NOTPENDING: Self = Self(0); - #[doc = "Selected trigger request occurred"] - pub const PENDING: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Swierw(pub u8); - impl Swierw { - #[doc = "Generates an interrupt request"] - pub const PEND: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Tr(pub u8); - impl Tr { - #[doc = "Falling edge trigger is disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Falling edge trigger is enabled"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mr(pub u8); - impl Mr { - #[doc = "Interrupt request line is masked"] - pub const MASKED: Self = Self(0); - #[doc = "Interrupt request line is unmasked"] - pub const UNMASKED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Prw(pub u8); - impl Prw { - #[doc = "Clears pending bit"] - pub const CLEAR: Self = Self(0x01); - } } } pub mod dma_v2 { @@ -1622,25 +8096,12 @@ pub mod dma_v2 { use crate::generic::*; #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Burst(pub u8); - impl Burst { - #[doc = "Single transfer"] - pub const SINGLE: Self = Self(0); - #[doc = "Incremental burst of 4 beats"] - pub const INCR4: Self = Self(0x01); - #[doc = "Incremental burst of 8 beats"] - pub const INCR8: Self = Self(0x02); - #[doc = "Incremental burst of 16 beats"] - pub const INCR16: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pincos(pub u8); - impl Pincos { - #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] - pub const PSIZE: Self = Self(0); - #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] - pub const FIXED4: Self = Self(0x01); + pub struct Dmdis(pub u8); + impl Dmdis { + #[doc = "Direct mode is enabled"] + pub const ENABLED: Self = Self(0); + #[doc = "Direct mode is disabled"] + pub const DISABLED: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] @@ -1655,28 +8116,6 @@ pub mod dma_v2 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dmdis(pub u8); - impl Dmdis { - #[doc = "Direct mode is enabled"] - pub const ENABLED: Self = Self(0); - #[doc = "Direct mode is disabled"] - pub const DISABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Fth(pub u8); - impl Fth { - #[doc = "1/4 full FIFO"] - pub const QUARTER: Self = Self(0); - #[doc = "1/2 full FIFO"] - pub const HALF: Self = Self(0x01); - #[doc = "3/4 full FIFO"] - pub const THREEQUARTERS: Self = Self(0x02); - #[doc = "Full FIFO"] - pub const FULL: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Inc(pub u8); impl Inc { #[doc = "Address pointer is fixed"] @@ -1686,26 +8125,6 @@ pub mod dma_v2 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dir(pub u8); - impl Dir { - #[doc = "Peripheral-to-memory"] - pub const PERIPHERALTOMEMORY: Self = Self(0); - #[doc = "Memory-to-peripheral"] - pub const MEMORYTOPERIPHERAL: Self = Self(0x01); - #[doc = "Memory-to-memory"] - pub const MEMORYTOMEMORY: Self = Self(0x02); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dbm(pub u8); - impl Dbm { - #[doc = "No buffer switching at the end of transfer"] - pub const DISABLED: Self = Self(0); - #[doc = "Memory target switched at the end of the DMA transfer"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Pfctrl(pub u8); impl Pfctrl { #[doc = "The DMA is the flow controller"] @@ -1724,6 +8143,43 @@ pub mod dma_v2 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Burst(pub u8); + impl Burst { + #[doc = "Single transfer"] + pub const SINGLE: Self = Self(0); + #[doc = "Incremental burst of 4 beats"] + pub const INCR4: Self = Self(0x01); + #[doc = "Incremental burst of 8 beats"] + pub const INCR8: Self = Self(0x02); + #[doc = "Incremental burst of 16 beats"] + pub const INCR16: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Peripheral-to-memory"] + pub const PERIPHERALTOMEMORY: Self = Self(0); + #[doc = "Memory-to-peripheral"] + pub const MEMORYTOPERIPHERAL: Self = Self(0x01); + #[doc = "Memory-to-memory"] + pub const MEMORYTOMEMORY: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pl(pub u8); + impl Pl { + #[doc = "Low"] + pub const LOW: Self = Self(0); + #[doc = "Medium"] + pub const MEDIUM: Self = Self(0x01); + #[doc = "High"] + pub const HIGH: Self = Self(0x02); + #[doc = "Very high"] + pub const VERYHIGH: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Fs(pub u8); impl Fs { #[doc = "0 < fifo_level < 1/4"] @@ -1741,16 +8197,25 @@ pub mod dma_v2 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pl(pub u8); - impl Pl { - #[doc = "Low"] - pub const LOW: Self = Self(0); - #[doc = "Medium"] - pub const MEDIUM: Self = Self(0x01); - #[doc = "High"] - pub const HIGH: Self = Self(0x02); - #[doc = "Very high"] - pub const VERYHIGH: Self = Self(0x03); + pub struct Fth(pub u8); + impl Fth { + #[doc = "1/4 full FIFO"] + pub const QUARTER: Self = Self(0); + #[doc = "1/2 full FIFO"] + pub const HALF: Self = Self(0x01); + #[doc = "3/4 full FIFO"] + pub const THREEQUARTERS: Self = Self(0x02); + #[doc = "Full FIFO"] + pub const FULL: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pincos(pub u8); + impl Pincos { + #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] + pub const PSIZE: Self = Self(0); + #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] + pub const FIXED4: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] @@ -1761,3588 +8226,18 @@ pub mod dma_v2 { #[doc = "The current target memory is Memory 1"] pub const MEMORY1: Self = Self(0x01); } - } -} -pub mod timer_v1 { - use crate::generic::*; - #[doc = "Advanced-timers"] - #[derive(Copy, Clone)] - pub struct TimAdv(pub *mut u8); - unsafe impl Send for TimAdv {} - unsafe impl Sync for TimAdv {} - impl TimAdv { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "slave mode control register"] - pub fn smcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "DMA/Interrupt enable register"] - pub fn dier(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "event generation register"] - pub fn egr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "capture/compare mode register 1 (input mode)"] - pub fn ccmr_input(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare mode register 1 (output mode)"] - pub fn ccmr_output(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare enable register"] - pub fn ccer(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(32usize)) } - } - #[doc = "counter"] - pub fn cnt(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - #[doc = "prescaler"] - pub fn psc(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(40usize)) } - } - #[doc = "auto-reload register"] - pub fn arr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(44usize)) } - } - #[doc = "repetition counter register"] - pub fn rcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(48usize)) } - } - #[doc = "capture/compare register"] - pub fn ccr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } - } - #[doc = "break and dead-time register"] - pub fn bdtr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(68usize)) } - } - #[doc = "DMA control register"] - pub fn dcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(72usize)) } - } - #[doc = "DMA address for full transfer"] - pub fn dmar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(76usize)) } - } - } - #[doc = "General purpose 32-bit timer"] - #[derive(Copy, Clone)] - pub struct TimGp32(pub *mut u8); - unsafe impl Send for TimGp32 {} - unsafe impl Sync for TimGp32 {} - impl TimGp32 { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "slave mode control register"] - pub fn smcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "DMA/Interrupt enable register"] - pub fn dier(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "event generation register"] - pub fn egr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "capture/compare mode register 1 (input mode)"] - pub fn ccmr_input(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare mode register 1 (output mode)"] - pub fn ccmr_output(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare enable register"] - pub fn ccer(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(32usize)) } - } - #[doc = "counter"] - pub fn cnt(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - #[doc = "prescaler"] - pub fn psc(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(40usize)) } - } - #[doc = "auto-reload register"] - pub fn arr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(44usize)) } - } - #[doc = "capture/compare register"] - pub fn ccr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } - } - #[doc = "DMA control register"] - pub fn dcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(72usize)) } - } - #[doc = "DMA address for full transfer"] - pub fn dmar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(76usize)) } - } - } - #[doc = "General purpose 16-bit timer"] - #[derive(Copy, Clone)] - pub struct TimGp16(pub *mut u8); - unsafe impl Send for TimGp16 {} - unsafe impl Sync for TimGp16 {} - impl TimGp16 { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "slave mode control register"] - pub fn smcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "DMA/Interrupt enable register"] - pub fn dier(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "event generation register"] - pub fn egr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "capture/compare mode register 1 (input mode)"] - pub fn ccmr_input(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare mode register 1 (output mode)"] - pub fn ccmr_output(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare enable register"] - pub fn ccer(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(32usize)) } - } - #[doc = "counter"] - pub fn cnt(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - #[doc = "prescaler"] - pub fn psc(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(40usize)) } - } - #[doc = "auto-reload register"] - pub fn arr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(44usize)) } - } - #[doc = "capture/compare register"] - pub fn ccr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } - } - #[doc = "DMA control register"] - pub fn dcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(72usize)) } - } - #[doc = "DMA address for full transfer"] - pub fn dmar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(76usize)) } - } - } - #[doc = "Basic timer"] - #[derive(Copy, Clone)] - pub struct TimBasic(pub *mut u8); - unsafe impl Send for TimBasic {} - unsafe impl Sync for TimBasic {} - impl TimBasic { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "DMA/Interrupt enable register"] - pub fn dier(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "event generation register"] - pub fn egr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "counter"] - pub fn cnt(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - #[doc = "prescaler"] - pub fn psc(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(40usize)) } - } - #[doc = "auto-reload register"] - pub fn arr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(44usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "event generation register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct EgrBasic(pub u32); - impl EgrBasic { - #[doc = "Update generation"] - pub const fn ug(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update generation"] - pub fn set_ug(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for EgrBasic { - fn default() -> EgrBasic { - EgrBasic(0) - } - } - #[doc = "DMA address for full transfer"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dmar(pub u32); - impl Dmar { - #[doc = "DMA register for burst accesses"] - pub const fn dmab(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "DMA register for burst accesses"] - pub fn set_dmab(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Dmar { - fn default() -> Dmar { - Dmar(0) - } - } - #[doc = "event generation register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct EgrGp(pub u32); - impl EgrGp { - #[doc = "Update generation"] - pub const fn ug(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update generation"] - pub fn set_ug(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare 1 generation"] - pub fn ccg(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/compare 1 generation"] - pub fn set_ccg(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare control update generation"] - pub const fn comg(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Capture/Compare control update generation"] - pub fn set_comg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger generation"] - pub const fn tg(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger generation"] - pub fn set_tg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break generation"] - pub const fn bg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break generation"] - pub fn set_bg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - } - impl Default for EgrGp { - fn default() -> EgrGp { - EgrGp(0) - } - } - #[doc = "control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2Gp(pub u32); - impl Cr2Gp { - #[doc = "Capture/compare DMA selection"] - pub const fn ccds(&self) -> super::vals::Ccds { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Ccds(val as u8) - } - #[doc = "Capture/compare DMA selection"] - pub fn set_ccds(&mut self, val: super::vals::Ccds) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Master mode selection"] - pub const fn mms(&self) -> super::vals::Mms { - let val = (self.0 >> 4usize) & 0x07; - super::vals::Mms(val as u8) - } - #[doc = "Master mode selection"] - pub fn set_mms(&mut self, val: super::vals::Mms) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); - } - #[doc = "TI1 selection"] - pub const fn ti1s(&self) -> super::vals::Tis { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Tis(val as u8) - } - #[doc = "TI1 selection"] - pub fn set_ti1s(&mut self, val: super::vals::Tis) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - } - impl Default for Cr2Gp { - fn default() -> Cr2Gp { - Cr2Gp(0) - } - } - #[doc = "break and dead-time register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Bdtr(pub u32); - impl Bdtr { - #[doc = "Dead-time generator setup"] - pub const fn dtg(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Dead-time generator setup"] - pub fn set_dtg(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - #[doc = "Lock configuration"] - pub const fn lock(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x03; - val as u8 - } - #[doc = "Lock configuration"] - pub fn set_lock(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); - } - #[doc = "Off-state selection for Idle mode"] - pub const fn ossi(&self) -> super::vals::Ossi { - let val = (self.0 >> 10usize) & 0x01; - super::vals::Ossi(val as u8) - } - #[doc = "Off-state selection for Idle mode"] - pub fn set_ossi(&mut self, val: super::vals::Ossi) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); - } - #[doc = "Off-state selection for Run mode"] - pub const fn ossr(&self) -> super::vals::Ossr { - let val = (self.0 >> 11usize) & 0x01; - super::vals::Ossr(val as u8) - } - #[doc = "Off-state selection for Run mode"] - pub fn set_ossr(&mut self, val: super::vals::Ossr) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); - } - #[doc = "Break enable"] - pub const fn bke(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[doc = "Break enable"] - pub fn set_bke(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[doc = "Break polarity"] - pub const fn bkp(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "Break polarity"] - pub fn set_bkp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[doc = "Automatic output enable"] - pub const fn aoe(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Automatic output enable"] - pub fn set_aoe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[doc = "Main output enable"] - pub const fn moe(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[doc = "Main output enable"] - pub fn set_moe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } - } - impl Default for Bdtr { - fn default() -> Bdtr { - Bdtr(0) - } - } - #[doc = "repetition counter register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Rcr(pub u32); - impl Rcr { - #[doc = "Repetition counter value"] - pub const fn rep(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Repetition counter value"] - pub fn set_rep(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - } - impl Default for Rcr { - fn default() -> Rcr { - Rcr(0) - } - } - #[doc = "DMA/Interrupt enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct DierAdv(pub u32); - impl DierAdv { - #[doc = "Update interrupt enable"] - pub const fn uie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt enable"] - pub fn set_uie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/Compare 1 interrupt enable"] - pub fn ccie(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 interrupt enable"] - pub fn set_ccie(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "COM interrupt enable"] - pub const fn comie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "COM interrupt enable"] - pub fn set_comie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger interrupt enable"] - pub const fn tie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger interrupt enable"] - pub fn set_tie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break interrupt enable"] - pub const fn bie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break interrupt enable"] - pub fn set_bie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Update DMA request enable"] - pub const fn ude(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Update DMA request enable"] - pub fn set_ude(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Capture/Compare 1 DMA request enable"] - pub fn ccde(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 DMA request enable"] - pub fn set_ccde(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "COM DMA request enable"] - pub const fn comde(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "COM DMA request enable"] - pub fn set_comde(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[doc = "Trigger DMA request enable"] - pub const fn tde(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Trigger DMA request enable"] - pub fn set_tde(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - } - impl Default for DierAdv { - fn default() -> DierAdv { - DierAdv(0) - } - } - #[doc = "slave mode control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Smcr(pub u32); - impl Smcr { - #[doc = "Slave mode selection"] - pub const fn sms(&self) -> super::vals::Sms { - let val = (self.0 >> 0usize) & 0x07; - super::vals::Sms(val as u8) - } - #[doc = "Slave mode selection"] - pub fn set_sms(&mut self, val: super::vals::Sms) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize); - } - #[doc = "Trigger selection"] - pub const fn ts(&self) -> super::vals::Ts { - let val = (self.0 >> 4usize) & 0x07; - super::vals::Ts(val as u8) - } - #[doc = "Trigger selection"] - pub fn set_ts(&mut self, val: super::vals::Ts) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); - } - #[doc = "Master/Slave mode"] - pub const fn msm(&self) -> super::vals::Msm { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Msm(val as u8) - } - #[doc = "Master/Slave mode"] - pub fn set_msm(&mut self, val: super::vals::Msm) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "External trigger filter"] - pub const fn etf(&self) -> super::vals::Etf { - let val = (self.0 >> 8usize) & 0x0f; - super::vals::Etf(val as u8) - } - #[doc = "External trigger filter"] - pub fn set_etf(&mut self, val: super::vals::Etf) { - self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); - } - #[doc = "External trigger prescaler"] - pub const fn etps(&self) -> super::vals::Etps { - let val = (self.0 >> 12usize) & 0x03; - super::vals::Etps(val as u8) - } - #[doc = "External trigger prescaler"] - pub fn set_etps(&mut self, val: super::vals::Etps) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); - } - #[doc = "External clock enable"] - pub const fn ece(&self) -> super::vals::Ece { - let val = (self.0 >> 14usize) & 0x01; - super::vals::Ece(val as u8) - } - #[doc = "External clock enable"] - pub fn set_ece(&mut self, val: super::vals::Ece) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); - } - #[doc = "External trigger polarity"] - pub const fn etp(&self) -> super::vals::Etp { - let val = (self.0 >> 15usize) & 0x01; - super::vals::Etp(val as u8) - } - #[doc = "External trigger polarity"] - pub fn set_etp(&mut self, val: super::vals::Etp) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); - } - } - impl Default for Smcr { - fn default() -> Smcr { - Smcr(0) - } - } - #[doc = "capture/compare register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ccr32(pub u32); - impl Ccr32 { - #[doc = "Capture/Compare 1 value"] - pub const fn ccr(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Capture/Compare 1 value"] - pub fn set_ccr(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Ccr32 { - fn default() -> Ccr32 { - Ccr32(0) - } - } - #[doc = "control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2Basic(pub u32); - impl Cr2Basic { - #[doc = "Master mode selection"] - pub const fn mms(&self) -> super::vals::Mms { - let val = (self.0 >> 4usize) & 0x07; - super::vals::Mms(val as u8) - } - #[doc = "Master mode selection"] - pub fn set_mms(&mut self, val: super::vals::Mms) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); - } - } - impl Default for Cr2Basic { - fn default() -> Cr2Basic { - Cr2Basic(0) - } - } - #[doc = "counter"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cnt32(pub u32); - impl Cnt32 { - #[doc = "counter value"] - pub const fn cnt(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "counter value"] - pub fn set_cnt(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Cnt32 { - fn default() -> Cnt32 { - Cnt32(0) - } - } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct SrGp(pub u32); - impl SrGp { - #[doc = "Update interrupt flag"] - pub const fn uif(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt flag"] - pub fn set_uif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare 1 interrupt flag"] - pub fn ccif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/compare 1 interrupt flag"] - pub fn set_ccif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "COM interrupt flag"] - pub const fn comif(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "COM interrupt flag"] - pub fn set_comif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger interrupt flag"] - pub const fn tif(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger interrupt flag"] - pub fn set_tif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break interrupt flag"] - pub const fn bif(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break interrupt flag"] - pub fn set_bif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Capture/Compare 1 overcapture flag"] - pub fn ccof(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 overcapture flag"] - pub fn set_ccof(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for SrGp { - fn default() -> SrGp { - SrGp(0) - } - } - #[doc = "prescaler"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Psc(pub u32); - impl Psc { - #[doc = "Prescaler value"] - pub const fn psc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Prescaler value"] - pub fn set_psc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Psc { - fn default() -> Psc { - Psc(0) - } - } - #[doc = "DMA control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dcr(pub u32); - impl Dcr { - #[doc = "DMA base address"] - pub const fn dba(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x1f; - val as u8 - } - #[doc = "DMA base address"] - pub fn set_dba(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); - } - #[doc = "DMA burst length"] - pub const fn dbl(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x1f; - val as u8 - } - #[doc = "DMA burst length"] - pub fn set_dbl(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); - } - } - impl Default for Dcr { - fn default() -> Dcr { - Dcr(0) - } - } - #[doc = "capture/compare enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcerGp(pub u32); - impl CcerGp { - #[doc = "Capture/Compare 1 output enable"] - pub fn cce(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output enable"] - pub fn set_cce(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn ccp(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn set_ccp(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn ccnp(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 3usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn set_ccnp(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 3usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for CcerGp { - fn default() -> CcerGp { - CcerGp(0) - } - } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct SrAdv(pub u32); - impl SrAdv { - #[doc = "Update interrupt flag"] - pub const fn uif(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt flag"] - pub fn set_uif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare 1 interrupt flag"] - pub fn ccif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/compare 1 interrupt flag"] - pub fn set_ccif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "COM interrupt flag"] - pub const fn comif(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "COM interrupt flag"] - pub fn set_comif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger interrupt flag"] - pub const fn tif(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger interrupt flag"] - pub fn set_tif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break interrupt flag"] - pub const fn bif(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break interrupt flag"] - pub fn set_bif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Capture/Compare 1 overcapture flag"] - pub fn ccof(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 overcapture flag"] - pub fn set_ccof(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for SrAdv { - fn default() -> SrAdv { - SrAdv(0) - } - } - #[doc = "capture/compare register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ccr16(pub u32); - impl Ccr16 { - #[doc = "Capture/Compare 1 value"] - pub const fn ccr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Capture/Compare 1 value"] - pub fn set_ccr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Ccr16 { - fn default() -> Ccr16 { - Ccr16(0) - } - } - #[doc = "event generation register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct EgrAdv(pub u32); - impl EgrAdv { - #[doc = "Update generation"] - pub const fn ug(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update generation"] - pub fn set_ug(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare 1 generation"] - pub fn ccg(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/compare 1 generation"] - pub fn set_ccg(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare control update generation"] - pub const fn comg(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Capture/Compare control update generation"] - pub fn set_comg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger generation"] - pub const fn tg(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger generation"] - pub fn set_tg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break generation"] - pub const fn bg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break generation"] - pub fn set_bg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - } - impl Default for EgrAdv { - fn default() -> EgrAdv { - EgrAdv(0) - } - } - #[doc = "auto-reload register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Arr32(pub u32); - impl Arr32 { - #[doc = "Auto-reload value"] - pub const fn arr(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Auto-reload value"] - pub fn set_arr(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Arr32 { - fn default() -> Arr32 { - Arr32(0) - } - } - #[doc = "control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2Adv(pub u32); - impl Cr2Adv { - #[doc = "Capture/compare preloaded control"] - pub const fn ccpc(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Capture/compare preloaded control"] - pub fn set_ccpc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare control update selection"] - pub const fn ccus(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Capture/compare control update selection"] - pub fn set_ccus(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Capture/compare DMA selection"] - pub const fn ccds(&self) -> super::vals::Ccds { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Ccds(val as u8) - } - #[doc = "Capture/compare DMA selection"] - pub fn set_ccds(&mut self, val: super::vals::Ccds) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Master mode selection"] - pub const fn mms(&self) -> super::vals::Mms { - let val = (self.0 >> 4usize) & 0x07; - super::vals::Mms(val as u8) - } - #[doc = "Master mode selection"] - pub fn set_mms(&mut self, val: super::vals::Mms) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); - } - #[doc = "TI1 selection"] - pub const fn ti1s(&self) -> super::vals::Tis { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Tis(val as u8) - } - #[doc = "TI1 selection"] - pub fn set_ti1s(&mut self, val: super::vals::Tis) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Output Idle state 1"] - pub fn ois(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 8usize + n * 2usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Output Idle state 1"] - pub fn set_ois(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 8usize + n * 2usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Output Idle state 1"] - pub const fn ois1n(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Output Idle state 1"] - pub fn set_ois1n(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Output Idle state 2"] - pub const fn ois2n(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "Output Idle state 2"] - pub fn set_ois2n(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "Output Idle state 3"] - pub const fn ois3n(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "Output Idle state 3"] - pub fn set_ois3n(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - } - impl Default for Cr2Adv { - fn default() -> Cr2Adv { - Cr2Adv(0) - } - } - #[doc = "capture/compare mode register 2 (output mode)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcmrOutput(pub u32); - impl CcmrOutput { - #[doc = "Capture/Compare 3 selection"] - pub fn ccs(&self, n: usize) -> super::vals::CcmrOutputCcs { - assert!(n < 2usize); - let offs = 0usize + n * 8usize; - let val = (self.0 >> offs) & 0x03; - super::vals::CcmrOutputCcs(val as u8) - } - #[doc = "Capture/Compare 3 selection"] - pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrOutputCcs) { - assert!(n < 2usize); - let offs = 0usize + n * 8usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - #[doc = "Output compare 3 fast enable"] - pub fn ocfe(&self, n: usize) -> bool { - assert!(n < 2usize); - let offs = 2usize + n * 8usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Output compare 3 fast enable"] - pub fn set_ocfe(&mut self, n: usize, val: bool) { - assert!(n < 2usize); - let offs = 2usize + n * 8usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Output compare 3 preload enable"] - pub fn ocpe(&self, n: usize) -> super::vals::Ocpe { - assert!(n < 2usize); - let offs = 3usize + n * 8usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Ocpe(val as u8) - } - #[doc = "Output compare 3 preload enable"] - pub fn set_ocpe(&mut self, n: usize, val: super::vals::Ocpe) { - assert!(n < 2usize); - let offs = 3usize + n * 8usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - #[doc = "Output compare 3 mode"] - pub fn ocm(&self, n: usize) -> super::vals::Ocm { - assert!(n < 2usize); - let offs = 4usize + n * 8usize; - let val = (self.0 >> offs) & 0x07; - super::vals::Ocm(val as u8) - } - #[doc = "Output compare 3 mode"] - pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) { - assert!(n < 2usize); - let offs = 4usize + n * 8usize; - self.0 = (self.0 & !(0x07 << offs)) | (((val.0 as u32) & 0x07) << offs); - } - #[doc = "Output compare 3 clear enable"] - pub fn occe(&self, n: usize) -> bool { - assert!(n < 2usize); - let offs = 7usize + n * 8usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Output compare 3 clear enable"] - pub fn set_occe(&mut self, n: usize, val: bool) { - assert!(n < 2usize); - let offs = 7usize + n * 8usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for CcmrOutput { - fn default() -> CcmrOutput { - CcmrOutput(0) - } - } - #[doc = "control register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1Basic(pub u32); - impl Cr1Basic { - #[doc = "Counter enable"] - pub const fn cen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Counter enable"] - pub fn set_cen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Update disable"] - pub const fn udis(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Update disable"] - pub fn set_udis(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Update request source"] - pub const fn urs(&self) -> super::vals::Urs { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Urs(val as u8) - } - #[doc = "Update request source"] - pub fn set_urs(&mut self, val: super::vals::Urs) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "One-pulse mode"] - pub const fn opm(&self) -> super::vals::Opm { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Opm(val as u8) - } - #[doc = "One-pulse mode"] - pub fn set_opm(&mut self, val: super::vals::Opm) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Auto-reload preload enable"] - pub const fn arpe(&self) -> super::vals::Arpe { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Arpe(val as u8) - } - #[doc = "Auto-reload preload enable"] - pub fn set_arpe(&mut self, val: super::vals::Arpe) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - } - impl Default for Cr1Basic { - fn default() -> Cr1Basic { - Cr1Basic(0) - } - } - #[doc = "auto-reload register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Arr16(pub u32); - impl Arr16 { - #[doc = "Auto-reload value"] - pub const fn arr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Auto-reload value"] - pub fn set_arr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Arr16 { - fn default() -> Arr16 { - Arr16(0) - } - } - #[doc = "DMA/Interrupt enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct DierGp(pub u32); - impl DierGp { - #[doc = "Update interrupt enable"] - pub const fn uie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt enable"] - pub fn set_uie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/Compare 1 interrupt enable"] - pub fn ccie(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 interrupt enable"] - pub fn set_ccie(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Trigger interrupt enable"] - pub const fn tie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger interrupt enable"] - pub fn set_tie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Update DMA request enable"] - pub const fn ude(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Update DMA request enable"] - pub fn set_ude(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Capture/Compare 1 DMA request enable"] - pub fn ccde(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 DMA request enable"] - pub fn set_ccde(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Trigger DMA request enable"] - pub const fn tde(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Trigger DMA request enable"] - pub fn set_tde(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - } - impl Default for DierGp { - fn default() -> DierGp { - DierGp(0) - } - } - #[doc = "capture/compare mode register 1 (input mode)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcmrInput(pub u32); - impl CcmrInput { - #[doc = "Capture/Compare 1 selection"] - pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs { - assert!(n < 2usize); - let offs = 0usize + n * 8usize; - let val = (self.0 >> offs) & 0x03; - super::vals::CcmrInputCcs(val as u8) - } - #[doc = "Capture/Compare 1 selection"] - pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) { - assert!(n < 2usize); - let offs = 0usize + n * 8usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - #[doc = "Input capture 1 prescaler"] - pub fn icpsc(&self, n: usize) -> u8 { - assert!(n < 2usize); - let offs = 2usize + n * 8usize; - let val = (self.0 >> offs) & 0x03; - val as u8 - } - #[doc = "Input capture 1 prescaler"] - pub fn set_icpsc(&mut self, n: usize, val: u8) { - assert!(n < 2usize); - let offs = 2usize + n * 8usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs); - } - #[doc = "Input capture 1 filter"] - pub fn icf(&self, n: usize) -> super::vals::Icf { - assert!(n < 2usize); - let offs = 4usize + n * 8usize; - let val = (self.0 >> offs) & 0x0f; - super::vals::Icf(val as u8) - } - #[doc = "Input capture 1 filter"] - pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) { - assert!(n < 2usize); - let offs = 4usize + n * 8usize; - self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); - } - } - impl Default for CcmrInput { - fn default() -> CcmrInput { - CcmrInput(0) - } - } - #[doc = "DMA/Interrupt enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct DierBasic(pub u32); - impl DierBasic { - #[doc = "Update interrupt enable"] - pub const fn uie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt enable"] - pub fn set_uie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Update DMA request enable"] - pub const fn ude(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Update DMA request enable"] - pub fn set_ude(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for DierBasic { - fn default() -> DierBasic { - DierBasic(0) - } - } - #[doc = "capture/compare enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcerAdv(pub u32); - impl CcerAdv { - #[doc = "Capture/Compare 1 output enable"] - pub fn cce(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output enable"] - pub fn set_cce(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn ccp(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn set_ccp(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 complementary output enable"] - pub fn ccne(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 2usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 complementary output enable"] - pub fn set_ccne(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 2usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn ccnp(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 3usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn set_ccnp(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 3usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for CcerAdv { - fn default() -> CcerAdv { - CcerAdv(0) - } - } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct SrBasic(pub u32); - impl SrBasic { - #[doc = "Update interrupt flag"] - pub const fn uif(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt flag"] - pub fn set_uif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for SrBasic { - fn default() -> SrBasic { - SrBasic(0) - } - } - #[doc = "control register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1Gp(pub u32); - impl Cr1Gp { - #[doc = "Counter enable"] - pub const fn cen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Counter enable"] - pub fn set_cen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Update disable"] - pub const fn udis(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Update disable"] - pub fn set_udis(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Update request source"] - pub const fn urs(&self) -> super::vals::Urs { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Urs(val as u8) - } - #[doc = "Update request source"] - pub fn set_urs(&mut self, val: super::vals::Urs) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "One-pulse mode"] - pub const fn opm(&self) -> super::vals::Opm { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Opm(val as u8) - } - #[doc = "One-pulse mode"] - pub fn set_opm(&mut self, val: super::vals::Opm) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Direction"] - pub const fn dir(&self) -> super::vals::Dir { - let val = (self.0 >> 4usize) & 0x01; - super::vals::Dir(val as u8) - } - #[doc = "Direction"] - pub fn set_dir(&mut self, val: super::vals::Dir) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); - } - #[doc = "Center-aligned mode selection"] - pub const fn cms(&self) -> super::vals::Cms { - let val = (self.0 >> 5usize) & 0x03; - super::vals::Cms(val as u8) - } - #[doc = "Center-aligned mode selection"] - pub fn set_cms(&mut self, val: super::vals::Cms) { - self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize); - } - #[doc = "Auto-reload preload enable"] - pub const fn arpe(&self) -> super::vals::Arpe { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Arpe(val as u8) - } - #[doc = "Auto-reload preload enable"] - pub fn set_arpe(&mut self, val: super::vals::Arpe) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Clock division"] - pub const fn ckd(&self) -> super::vals::Ckd { - let val = (self.0 >> 8usize) & 0x03; - super::vals::Ckd(val as u8) - } - #[doc = "Clock division"] - pub fn set_ckd(&mut self, val: super::vals::Ckd) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); - } - } - impl Default for Cr1Gp { - fn default() -> Cr1Gp { - Cr1Gp(0) - } - } - #[doc = "counter"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cnt16(pub u32); - impl Cnt16 { - #[doc = "counter value"] - pub const fn cnt(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "counter value"] - pub fn set_cnt(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Cnt16 { - fn default() -> Cnt16 { - Cnt16(0) - } - } - } - pub mod vals { - use crate::generic::*; #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Etp(pub u8); - impl Etp { - #[doc = "ETR is noninverted, active at high level or rising edge"] - pub const NOTINVERTED: Self = Self(0); - #[doc = "ETR is inverted, active at low level or falling edge"] - pub const INVERTED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Opm(pub u8); - impl Opm { - #[doc = "Counter is not stopped at update event"] + pub struct Dbm(pub u8); + impl Dbm { + #[doc = "No buffer switching at the end of transfer"] pub const DISABLED: Self = Self(0); - #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"] + #[doc = "Memory target switched at the end of the DMA transfer"] pub const ENABLED: Self = Self(0x01); } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Arpe(pub u8); - impl Arpe { - #[doc = "TIMx_APRR register is not buffered"] - pub const DISABLED: Self = Self(0); - #[doc = "TIMx_APRR register is buffered"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Etf(pub u8); - impl Etf { - #[doc = "No filter, sampling is done at fDTS"] - pub const NOFILTER: Self = Self(0); - #[doc = "fSAMPLING=fCK_INT, N=2"] - pub const FCK_INT_N2: Self = Self(0x01); - #[doc = "fSAMPLING=fCK_INT, N=4"] - pub const FCK_INT_N4: Self = Self(0x02); - #[doc = "fSAMPLING=fCK_INT, N=8"] - pub const FCK_INT_N8: Self = Self(0x03); - #[doc = "fSAMPLING=fDTS/2, N=6"] - pub const FDTS_DIV2_N6: Self = Self(0x04); - #[doc = "fSAMPLING=fDTS/2, N=8"] - pub const FDTS_DIV2_N8: Self = Self(0x05); - #[doc = "fSAMPLING=fDTS/4, N=6"] - pub const FDTS_DIV4_N6: Self = Self(0x06); - #[doc = "fSAMPLING=fDTS/4, N=8"] - pub const FDTS_DIV4_N8: Self = Self(0x07); - #[doc = "fSAMPLING=fDTS/8, N=6"] - pub const FDTS_DIV8_N6: Self = Self(0x08); - #[doc = "fSAMPLING=fDTS/8, N=8"] - pub const FDTS_DIV8_N8: Self = Self(0x09); - #[doc = "fSAMPLING=fDTS/16, N=5"] - pub const FDTS_DIV16_N5: Self = Self(0x0a); - #[doc = "fSAMPLING=fDTS/16, N=6"] - pub const FDTS_DIV16_N6: Self = Self(0x0b); - #[doc = "fSAMPLING=fDTS/16, N=8"] - pub const FDTS_DIV16_N8: Self = Self(0x0c); - #[doc = "fSAMPLING=fDTS/32, N=5"] - pub const FDTS_DIV32_N5: Self = Self(0x0d); - #[doc = "fSAMPLING=fDTS/32, N=6"] - pub const FDTS_DIV32_N6: Self = Self(0x0e); - #[doc = "fSAMPLING=fDTS/32, N=8"] - pub const FDTS_DIV32_N8: Self = Self(0x0f); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ocm(pub u8); - impl Ocm { - #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] - pub const FROZEN: Self = Self(0); - #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] - pub const ACTIVEONMATCH: Self = Self(0x01); - #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] - pub const INACTIVEONMATCH: Self = Self(0x02); - #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] - pub const TOGGLE: Self = Self(0x03); - #[doc = "OCyREF is forced low"] - pub const FORCEINACTIVE: Self = Self(0x04); - #[doc = "OCyREF is forced high"] - pub const FORCEACTIVE: Self = Self(0x05); - #[doc = "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active"] - pub const PWMMODE1: Self = Self(0x06); - #[doc = "Inversely to PwmMode1"] - pub const PWMMODE2: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Urs(pub u8); - impl Urs { - #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"] - pub const ANYEVENT: Self = Self(0); - #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"] - pub const COUNTERONLY: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Icf(pub u8); - impl Icf { - #[doc = "No filter, sampling is done at fDTS"] - pub const NOFILTER: Self = Self(0); - #[doc = "fSAMPLING=fCK_INT, N=2"] - pub const FCK_INT_N2: Self = Self(0x01); - #[doc = "fSAMPLING=fCK_INT, N=4"] - pub const FCK_INT_N4: Self = Self(0x02); - #[doc = "fSAMPLING=fCK_INT, N=8"] - pub const FCK_INT_N8: Self = Self(0x03); - #[doc = "fSAMPLING=fDTS/2, N=6"] - pub const FDTS_DIV2_N6: Self = Self(0x04); - #[doc = "fSAMPLING=fDTS/2, N=8"] - pub const FDTS_DIV2_N8: Self = Self(0x05); - #[doc = "fSAMPLING=fDTS/4, N=6"] - pub const FDTS_DIV4_N6: Self = Self(0x06); - #[doc = "fSAMPLING=fDTS/4, N=8"] - pub const FDTS_DIV4_N8: Self = Self(0x07); - #[doc = "fSAMPLING=fDTS/8, N=6"] - pub const FDTS_DIV8_N6: Self = Self(0x08); - #[doc = "fSAMPLING=fDTS/8, N=8"] - pub const FDTS_DIV8_N8: Self = Self(0x09); - #[doc = "fSAMPLING=fDTS/16, N=5"] - pub const FDTS_DIV16_N5: Self = Self(0x0a); - #[doc = "fSAMPLING=fDTS/16, N=6"] - pub const FDTS_DIV16_N6: Self = Self(0x0b); - #[doc = "fSAMPLING=fDTS/16, N=8"] - pub const FDTS_DIV16_N8: Self = Self(0x0c); - #[doc = "fSAMPLING=fDTS/32, N=5"] - pub const FDTS_DIV32_N5: Self = Self(0x0d); - #[doc = "fSAMPLING=fDTS/32, N=6"] - pub const FDTS_DIV32_N6: Self = Self(0x0e); - #[doc = "fSAMPLING=fDTS/32, N=8"] - pub const FDTS_DIV32_N8: Self = Self(0x0f); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Msm(pub u8); - impl Msm { - #[doc = "No action"] - pub const NOSYNC: Self = Self(0); - #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."] - pub const SYNC: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ece(pub u8); - impl Ece { - #[doc = "External clock mode 2 disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Tis(pub u8); - impl Tis { - #[doc = "The TIMx_CH1 pin is connected to TI1 input"] - pub const NORMAL: Self = Self(0); - #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"] - pub const XOR: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ossr(pub u8); - impl Ossr { - #[doc = "When inactive, OC/OCN outputs are disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"] - pub const IDLELEVEL: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dir(pub u8); - impl Dir { - #[doc = "Counter used as upcounter"] - pub const UP: Self = Self(0); - #[doc = "Counter used as downcounter"] - pub const DOWN: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mms(pub u8); - impl Mms { - #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"] - pub const RESET: Self = Self(0); - #[doc = "The counter enable signal, CNT_EN, is used as trigger output"] - pub const ENABLE: Self = Self(0x01); - #[doc = "The update event is selected as trigger output"] - pub const UPDATE: Self = Self(0x02); - #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"] - pub const COMPAREPULSE: Self = Self(0x03); - #[doc = "OC1REF signal is used as trigger output"] - pub const COMPAREOC1: Self = Self(0x04); - #[doc = "OC2REF signal is used as trigger output"] - pub const COMPAREOC2: Self = Self(0x05); - #[doc = "OC3REF signal is used as trigger output"] - pub const COMPAREOC3: Self = Self(0x06); - #[doc = "OC4REF signal is used as trigger output"] - pub const COMPAREOC4: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ckd(pub u8); - impl Ckd { - #[doc = "t_DTS = t_CK_INT"] - pub const DIV1: Self = Self(0); - #[doc = "t_DTS = 2 × t_CK_INT"] - pub const DIV2: Self = Self(0x01); - #[doc = "t_DTS = 4 × t_CK_INT"] - pub const DIV4: Self = Self(0x02); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ocpe(pub u8); - impl Ocpe { - #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"] - pub const DISABLED: Self = Self(0); - #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ossi(pub u8); - impl Ossi { - #[doc = "When inactive, OC/OCN outputs are disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "When inactive, OC/OCN outputs are forced to idle level"] - pub const IDLELEVEL: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Etps(pub u8); - impl Etps { - #[doc = "Prescaler OFF"] - pub const DIV1: Self = Self(0); - #[doc = "ETRP frequency divided by 2"] - pub const DIV2: Self = Self(0x01); - #[doc = "ETRP frequency divided by 4"] - pub const DIV4: Self = Self(0x02); - #[doc = "ETRP frequency divided by 8"] - pub const DIV8: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct CcmrInputCcs(pub u8); - impl CcmrInputCcs { - #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"] - pub const TI4: Self = Self(0x01); - #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"] - pub const TI3: Self = Self(0x02); - #[doc = "CCx channel is configured as input, ICx is mapped on TRC"] - pub const TRC: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cms(pub u8); - impl Cms { - #[doc = "The counter counts up or down depending on the direction bit"] - pub const EDGEALIGNED: Self = Self(0); - #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] - pub const CENTERALIGNED1: Self = Self(0x01); - #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] - pub const CENTERALIGNED2: Self = Self(0x02); - #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] - pub const CENTERALIGNED3: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ts(pub u8); - impl Ts { - #[doc = "Internal Trigger 0 (ITR0)"] - pub const ITR0: Self = Self(0); - #[doc = "Internal Trigger 1 (ITR1)"] - pub const ITR1: Self = Self(0x01); - #[doc = "Internal Trigger 2 (ITR2)"] - pub const ITR2: Self = Self(0x02); - #[doc = "TI1 Edge Detector (TI1F_ED)"] - pub const TI1F_ED: Self = Self(0x04); - #[doc = "Filtered Timer Input 1 (TI1FP1)"] - pub const TI1FP1: Self = Self(0x05); - #[doc = "Filtered Timer Input 2 (TI2FP2)"] - pub const TI2FP2: Self = Self(0x06); - #[doc = "External Trigger input (ETRF)"] - pub const ETRF: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Sms(pub u8); - impl Sms { - #[doc = "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] - pub const DISABLED: Self = Self(0); - #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."] - pub const ENCODER_MODE_1: Self = Self(0x01); - #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."] - pub const ENCODER_MODE_2: Self = Self(0x02); - #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."] - pub const ENCODER_MODE_3: Self = Self(0x03); - #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."] - pub const RESET_MODE: Self = Self(0x04); - #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."] - pub const GATED_MODE: Self = Self(0x05); - #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."] - pub const TRIGGER_MODE: Self = Self(0x06); - #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."] - pub const EXT_CLOCK_MODE: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ccds(pub u8); - impl Ccds { - #[doc = "CCx DMA request sent when CCx event occurs"] - pub const ONCOMPARE: Self = Self(0); - #[doc = "CCx DMA request sent when update event occurs"] - pub const ONUPDATE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct CcmrOutputCcs(pub u8); - impl CcmrOutputCcs { - #[doc = "CCx channel is configured as output"] - pub const OUTPUT: Self = Self(0); - } } } -pub mod spi_v2 { - use crate::generic::*; - #[doc = "Serial peripheral interface"] - #[derive(Copy, Clone)] - pub struct Spi(pub *mut u8); - unsafe impl Send for Spi {} - unsafe impl Sync for Spi {} - impl Spi { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "data register"] - pub fn dr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "CRC polynomial register"] - pub fn crcpr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "RX CRC register"] - pub fn rxcrcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "TX CRC register"] - pub fn txcrcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mstr(pub u8); - impl Mstr { - #[doc = "Slave configuration"] - pub const SLAVE: Self = Self(0); - #[doc = "Master configuration"] - pub const MASTER: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frxth(pub u8); - impl Frxth { - #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"] - pub const HALF: Self = Self(0); - #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"] - pub const QUARTER: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpol(pub u8); - impl Cpol { - #[doc = "CK to 0 when idle"] - pub const IDLELOW: Self = Self(0); - #[doc = "CK to 1 when idle"] - pub const IDLEHIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct LdmaTx(pub u8); - impl LdmaTx { - #[doc = "Number of data to transfer for transmit is even"] - pub const EVEN: Self = Self(0); - #[doc = "Number of data to transfer for transmit is odd"] - pub const ODD: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lsbfirst(pub u8); - impl Lsbfirst { - #[doc = "Data is transmitted/received with the MSB first"] - pub const MSBFIRST: Self = Self(0); - #[doc = "Data is transmitted/received with the LSB first"] - pub const LSBFIRST: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Rxonly(pub u8); - impl Rxonly { - #[doc = "Full duplex (Transmit and receive)"] - pub const FULLDUPLEX: Self = Self(0); - #[doc = "Output disabled (Receive-only mode)"] - pub const OUTPUTDISABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct LdmaRx(pub u8); - impl LdmaRx { - #[doc = "Number of data to transfer for receive is even"] - pub const EVEN: Self = Self(0); - #[doc = "Number of data to transfer for receive is odd"] - pub const ODD: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frer(pub u8); - impl Frer { - #[doc = "No frame format error"] - pub const NOERROR: Self = Self(0); - #[doc = "A frame format error occurred"] - pub const ERROR: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frf(pub u8); - impl Frf { - #[doc = "SPI Motorola mode"] - pub const MOTOROLA: Self = Self(0); - #[doc = "SPI TI mode"] - pub const TI: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Crcnext(pub u8); - impl Crcnext { - #[doc = "Next transmit value is from Tx buffer"] - pub const TXBUFFER: Self = Self(0); - #[doc = "Next transmit value is from Tx CRC register"] - pub const CRC: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Crcl(pub u8); - impl Crcl { - #[doc = "8-bit CRC length"] - pub const EIGHTBIT: Self = Self(0); - #[doc = "16-bit CRC length"] - pub const SIXTEENBIT: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ds(pub u8); - impl Ds { - #[doc = "4-bit"] - pub const FOURBIT: Self = Self(0x03); - #[doc = "5-bit"] - pub const FIVEBIT: Self = Self(0x04); - #[doc = "6-bit"] - pub const SIXBIT: Self = Self(0x05); - #[doc = "7-bit"] - pub const SEVENBIT: Self = Self(0x06); - #[doc = "8-bit"] - pub const EIGHTBIT: Self = Self(0x07); - #[doc = "9-bit"] - pub const NINEBIT: Self = Self(0x08); - #[doc = "10-bit"] - pub const TENBIT: Self = Self(0x09); - #[doc = "11-bit"] - pub const ELEVENBIT: Self = Self(0x0a); - #[doc = "12-bit"] - pub const TWELVEBIT: Self = Self(0x0b); - #[doc = "13-bit"] - pub const THIRTEENBIT: Self = Self(0x0c); - #[doc = "14-bit"] - pub const FOURTEENBIT: Self = Self(0x0d); - #[doc = "15-bit"] - pub const FIFTEENBIT: Self = Self(0x0e); - #[doc = "16-bit"] - pub const SIXTEENBIT: Self = Self(0x0f); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bidioe(pub u8); - impl Bidioe { - #[doc = "Output disabled (receive-only mode)"] - pub const OUTPUTDISABLED: Self = Self(0); - #[doc = "Output enabled (transmit-only mode)"] - pub const OUTPUTENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Br(pub u8); - impl Br { - #[doc = "f_PCLK / 2"] - pub const DIV2: Self = Self(0); - #[doc = "f_PCLK / 4"] - pub const DIV4: Self = Self(0x01); - #[doc = "f_PCLK / 8"] - pub const DIV8: Self = Self(0x02); - #[doc = "f_PCLK / 16"] - pub const DIV16: Self = Self(0x03); - #[doc = "f_PCLK / 32"] - pub const DIV32: Self = Self(0x04); - #[doc = "f_PCLK / 64"] - pub const DIV64: Self = Self(0x05); - #[doc = "f_PCLK / 128"] - pub const DIV128: Self = Self(0x06); - #[doc = "f_PCLK / 256"] - pub const DIV256: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpha(pub u8); - impl Cpha { - #[doc = "The first clock transition is the first data capture edge"] - pub const FIRSTEDGE: Self = Self(0); - #[doc = "The second clock transition is the first data capture edge"] - pub const SECONDEDGE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frlvlr(pub u8); - impl Frlvlr { - #[doc = "Rx FIFO Empty"] - pub const EMPTY: Self = Self(0); - #[doc = "Rx 1/4 FIFO"] - pub const QUARTER: Self = Self(0x01); - #[doc = "Rx 1/2 FIFO"] - pub const HALF: Self = Self(0x02); - #[doc = "Rx FIFO full"] - pub const FULL: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bidimode(pub u8); - impl Bidimode { - #[doc = "2-line unidirectional data mode selected"] - pub const UNIDIRECTIONAL: Self = Self(0); - #[doc = "1-line bidirectional data mode selected"] - pub const BIDIRECTIONAL: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ftlvlr(pub u8); - impl Ftlvlr { - #[doc = "Tx FIFO Empty"] - pub const EMPTY: Self = Self(0); - #[doc = "Tx 1/4 FIFO"] - pub const QUARTER: Self = Self(0x01); - #[doc = "Tx 1/2 FIFO"] - pub const HALF: Self = Self(0x02); - #[doc = "Tx FIFO full"] - pub const FULL: Self = Self(0x03); - } - } - pub mod regs { - use crate::generic::*; - #[doc = "control register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1(pub u32); - impl Cr1 { - #[doc = "Clock phase"] - pub const fn cpha(&self) -> super::vals::Cpha { - let val = (self.0 >> 0usize) & 0x01; - super::vals::Cpha(val as u8) - } - #[doc = "Clock phase"] - pub fn set_cpha(&mut self, val: super::vals::Cpha) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); - } - #[doc = "Clock polarity"] - pub const fn cpol(&self) -> super::vals::Cpol { - let val = (self.0 >> 1usize) & 0x01; - super::vals::Cpol(val as u8) - } - #[doc = "Clock polarity"] - pub fn set_cpol(&mut self, val: super::vals::Cpol) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); - } - #[doc = "Master selection"] - pub const fn mstr(&self) -> super::vals::Mstr { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Mstr(val as u8) - } - #[doc = "Master selection"] - pub fn set_mstr(&mut self, val: super::vals::Mstr) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "Baud rate control"] - pub const fn br(&self) -> super::vals::Br { - let val = (self.0 >> 3usize) & 0x07; - super::vals::Br(val as u8) - } - #[doc = "Baud rate control"] - pub fn set_br(&mut self, val: super::vals::Br) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); - } - #[doc = "SPI enable"] - pub const fn spe(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "SPI enable"] - pub fn set_spe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Frame format"] - pub const fn lsbfirst(&self) -> super::vals::Lsbfirst { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Lsbfirst(val as u8) - } - #[doc = "Frame format"] - pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Internal slave select"] - pub const fn ssi(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Internal slave select"] - pub fn set_ssi(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Software slave management"] - pub const fn ssm(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Software slave management"] - pub fn set_ssm(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Receive only"] - pub const fn rxonly(&self) -> super::vals::Rxonly { - let val = (self.0 >> 10usize) & 0x01; - super::vals::Rxonly(val as u8) - } - #[doc = "Receive only"] - pub fn set_rxonly(&mut self, val: super::vals::Rxonly) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); - } - #[doc = "CRC length"] - pub const fn crcl(&self) -> super::vals::Crcl { - let val = (self.0 >> 11usize) & 0x01; - super::vals::Crcl(val as u8) - } - #[doc = "CRC length"] - pub fn set_crcl(&mut self, val: super::vals::Crcl) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); - } - #[doc = "CRC transfer next"] - pub const fn crcnext(&self) -> super::vals::Crcnext { - let val = (self.0 >> 12usize) & 0x01; - super::vals::Crcnext(val as u8) - } - #[doc = "CRC transfer next"] - pub fn set_crcnext(&mut self, val: super::vals::Crcnext) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); - } - #[doc = "Hardware CRC calculation enable"] - pub const fn crcen(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "Hardware CRC calculation enable"] - pub fn set_crcen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[doc = "Output enable in bidirectional mode"] - pub const fn bidioe(&self) -> super::vals::Bidioe { - let val = (self.0 >> 14usize) & 0x01; - super::vals::Bidioe(val as u8) - } - #[doc = "Output enable in bidirectional mode"] - pub fn set_bidioe(&mut self, val: super::vals::Bidioe) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); - } - #[doc = "Bidirectional data mode enable"] - pub const fn bidimode(&self) -> super::vals::Bidimode { - let val = (self.0 >> 15usize) & 0x01; - super::vals::Bidimode(val as u8) - } - #[doc = "Bidirectional data mode enable"] - pub fn set_bidimode(&mut self, val: super::vals::Bidimode) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); - } - } - impl Default for Cr1 { - fn default() -> Cr1 { - Cr1(0) - } - } - #[doc = "RX CRC register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Rxcrcr(pub u32); - impl Rxcrcr { - #[doc = "Rx CRC register"] - pub const fn rx_crc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Rx CRC register"] - pub fn set_rx_crc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Rxcrcr { - fn default() -> Rxcrcr { - Rxcrcr(0) - } - } - #[doc = "CRC polynomial register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Crcpr(pub u32); - impl Crcpr { - #[doc = "CRC polynomial register"] - pub const fn crcpoly(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "CRC polynomial register"] - pub fn set_crcpoly(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Crcpr { - fn default() -> Crcpr { - Crcpr(0) - } - } - #[doc = "control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2(pub u32); - impl Cr2 { - #[doc = "Rx buffer DMA enable"] - pub const fn rxdmaen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Rx buffer DMA enable"] - pub fn set_rxdmaen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Tx buffer DMA enable"] - pub const fn txdmaen(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Tx buffer DMA enable"] - pub fn set_txdmaen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "SS output enable"] - pub const fn ssoe(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "SS output enable"] - pub fn set_ssoe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "NSS pulse management"] - pub const fn nssp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "NSS pulse management"] - pub fn set_nssp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Frame format"] - pub const fn frf(&self) -> super::vals::Frf { - let val = (self.0 >> 4usize) & 0x01; - super::vals::Frf(val as u8) - } - #[doc = "Frame format"] - pub fn set_frf(&mut self, val: super::vals::Frf) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); - } - #[doc = "Error interrupt enable"] - pub const fn errie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Error interrupt enable"] - pub fn set_errie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "RX buffer not empty interrupt enable"] - pub const fn rxneie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "RX buffer not empty interrupt enable"] - pub fn set_rxneie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Tx buffer empty interrupt enable"] - pub const fn txeie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Tx buffer empty interrupt enable"] - pub fn set_txeie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Data size"] - pub const fn ds(&self) -> super::vals::Ds { - let val = (self.0 >> 8usize) & 0x0f; - super::vals::Ds(val as u8) - } - #[doc = "Data size"] - pub fn set_ds(&mut self, val: super::vals::Ds) { - self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); - } - #[doc = "FIFO reception threshold"] - pub const fn frxth(&self) -> super::vals::Frxth { - let val = (self.0 >> 12usize) & 0x01; - super::vals::Frxth(val as u8) - } - #[doc = "FIFO reception threshold"] - pub fn set_frxth(&mut self, val: super::vals::Frxth) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); - } - #[doc = "Last DMA transfer for reception"] - pub const fn ldma_rx(&self) -> super::vals::LdmaRx { - let val = (self.0 >> 13usize) & 0x01; - super::vals::LdmaRx(val as u8) - } - #[doc = "Last DMA transfer for reception"] - pub fn set_ldma_rx(&mut self, val: super::vals::LdmaRx) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val.0 as u32) & 0x01) << 13usize); - } - #[doc = "Last DMA transfer for transmission"] - pub const fn ldma_tx(&self) -> super::vals::LdmaTx { - let val = (self.0 >> 14usize) & 0x01; - super::vals::LdmaTx(val as u8) - } - #[doc = "Last DMA transfer for transmission"] - pub fn set_ldma_tx(&mut self, val: super::vals::LdmaTx) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); - } - } - impl Default for Cr2 { - fn default() -> Cr2 { - Cr2(0) - } - } - #[doc = "data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dr(pub u32); - impl Dr { - #[doc = "Data register"] - pub const fn dr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Data register"] - pub fn set_dr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Dr { - fn default() -> Dr { - Dr(0) - } - } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Sr(pub u32); - impl Sr { - #[doc = "Receive buffer not empty"] - pub const fn rxne(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Receive buffer not empty"] - pub fn set_rxne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Transmit buffer empty"] - pub const fn txe(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Transmit buffer empty"] - pub fn set_txe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "CRC error flag"] - pub const fn crcerr(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "CRC error flag"] - pub fn set_crcerr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Mode fault"] - pub const fn modf(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Mode fault"] - pub fn set_modf(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Overrun flag"] - pub const fn ovr(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Overrun flag"] - pub fn set_ovr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Busy flag"] - pub const fn bsy(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Busy flag"] - pub fn set_bsy(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Frame format error"] - pub const fn fre(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Frame format error"] - pub fn set_fre(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "FIFO reception level"] - pub const fn frlvl(&self) -> u8 { - let val = (self.0 >> 9usize) & 0x03; - val as u8 - } - #[doc = "FIFO reception level"] - pub fn set_frlvl(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 9usize)) | (((val as u32) & 0x03) << 9usize); - } - #[doc = "FIFO Transmission Level"] - pub const fn ftlvl(&self) -> u8 { - let val = (self.0 >> 11usize) & 0x03; - val as u8 - } - #[doc = "FIFO Transmission Level"] - pub fn set_ftlvl(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 11usize)) | (((val as u32) & 0x03) << 11usize); - } - } - impl Default for Sr { - fn default() -> Sr { - Sr(0) - } - } - #[doc = "TX CRC register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Txcrcr(pub u32); - impl Txcrcr { - #[doc = "Tx CRC register"] - pub const fn tx_crc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Tx CRC register"] - pub fn set_tx_crc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Txcrcr { - fn default() -> Txcrcr { - Txcrcr(0) - } - } - } -} -pub mod usart_v1 { - use crate::generic::*; - #[doc = "Universal synchronous asynchronous receiver transmitter"] - #[derive(Copy, Clone)] - pub struct Usart(pub *mut u8); - unsafe impl Send for Usart {} - unsafe impl Sync for Usart {} - impl Usart { - #[doc = "Status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "Data register"] - pub fn dr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "Baud rate register"] - pub fn brr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "Control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "Control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "Control register 3"] - pub fn cr3(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "Guard time and prescaler register"] - pub fn gtpr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } - } - } - #[doc = "Universal asynchronous receiver transmitter"] - #[derive(Copy, Clone)] - pub struct Uart(pub *mut u8); - unsafe impl Send for Uart {} - unsafe impl Sync for Uart {} - impl Uart { - #[doc = "Status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "Data register"] - pub fn dr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "Baud rate register"] - pub fn brr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "Control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "Control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "Control register 3"] - pub fn cr3(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ps(pub u8); - impl Ps { - #[doc = "Even parity"] - pub const EVEN: Self = Self(0); - #[doc = "Odd parity"] - pub const ODD: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Irlp(pub u8); - impl Irlp { - #[doc = "Normal mode"] - pub const NORMAL: Self = Self(0); - #[doc = "Low-power mode"] - pub const LOWPOWER: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Hdsel(pub u8); - impl Hdsel { - #[doc = "Half duplex mode is not selected"] - pub const FULLDUPLEX: Self = Self(0); - #[doc = "Half duplex mode is selected"] - pub const HALFDUPLEX: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpol(pub u8); - impl Cpol { - #[doc = "Steady low value on CK pin outside transmission window"] - pub const LOW: Self = Self(0); - #[doc = "Steady high value on CK pin outside transmission window"] - pub const HIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Wake(pub u8); - impl Wake { - #[doc = "USART wakeup on idle line"] - pub const IDLELINE: Self = Self(0); - #[doc = "USART wakeup on address mark"] - pub const ADDRESSMARK: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Sbk(pub u8); - impl Sbk { - #[doc = "No break character is transmitted"] - pub const NOBREAK: Self = Self(0); - #[doc = "Break character transmitted"] - pub const BREAK: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct M(pub u8); - impl M { - #[doc = "8 data bits"] - pub const M8: Self = Self(0); - #[doc = "9 data bits"] - pub const M9: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpha(pub u8); - impl Cpha { - #[doc = "The first clock transition is the first data capture edge"] - pub const FIRST: Self = Self(0); - #[doc = "The second clock transition is the first data capture edge"] - pub const SECOND: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Rwu(pub u8); - impl Rwu { - #[doc = "Receiver in active mode"] - pub const ACTIVE: Self = Self(0); - #[doc = "Receiver in mute mode"] - pub const MUTE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lbdl(pub u8); - impl Lbdl { - #[doc = "10-bit break detection"] - pub const LBDL10: Self = Self(0); - #[doc = "11-bit break detection"] - pub const LBDL11: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Stop(pub u8); - impl Stop { - #[doc = "1 stop bit"] - pub const STOP1: Self = Self(0); - #[doc = "0.5 stop bits"] - pub const STOP0P5: Self = Self(0x01); - #[doc = "2 stop bits"] - pub const STOP2: Self = Self(0x02); - #[doc = "1.5 stop bits"] - pub const STOP1P5: Self = Self(0x03); - } - } - pub mod regs { - use crate::generic::*; - #[doc = "Guard time and prescaler register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Gtpr(pub u32); - impl Gtpr { - #[doc = "Prescaler value"] - pub const fn psc(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Prescaler value"] - pub fn set_psc(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - #[doc = "Guard time value"] - pub const fn gt(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Guard time value"] - pub fn set_gt(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - } - impl Default for Gtpr { - fn default() -> Gtpr { - Gtpr(0) - } - } - #[doc = "Control register 3"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr3Usart(pub u32); - impl Cr3Usart { - #[doc = "Error interrupt enable"] - pub const fn eie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Error interrupt enable"] - pub fn set_eie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "IrDA mode enable"] - pub const fn iren(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "IrDA mode enable"] - pub fn set_iren(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "IrDA low-power"] - pub const fn irlp(&self) -> super::vals::Irlp { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Irlp(val as u8) - } - #[doc = "IrDA low-power"] - pub fn set_irlp(&mut self, val: super::vals::Irlp) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "Half-duplex selection"] - pub const fn hdsel(&self) -> super::vals::Hdsel { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Hdsel(val as u8) - } - #[doc = "Half-duplex selection"] - pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Smartcard NACK enable"] - pub const fn nack(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "Smartcard NACK enable"] - pub fn set_nack(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Smartcard mode enable"] - pub const fn scen(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Smartcard mode enable"] - pub fn set_scen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "DMA enable receiver"] - pub const fn dmar(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "DMA enable receiver"] - pub fn set_dmar(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "DMA enable transmitter"] - pub const fn dmat(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "DMA enable transmitter"] - pub fn set_dmat(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "RTS enable"] - pub const fn rtse(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "RTS enable"] - pub fn set_rtse(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "CTS enable"] - pub const fn ctse(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "CTS enable"] - pub fn set_ctse(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "CTS interrupt enable"] - pub const fn ctsie(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "CTS interrupt enable"] - pub fn set_ctsie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - } - impl Default for Cr3Usart { - fn default() -> Cr3Usart { - Cr3Usart(0) - } - } - #[doc = "Control register 3"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr3(pub u32); - impl Cr3 { - #[doc = "Error interrupt enable"] - pub const fn eie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Error interrupt enable"] - pub fn set_eie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "IrDA mode enable"] - pub const fn iren(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "IrDA mode enable"] - pub fn set_iren(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "IrDA low-power"] - pub const fn irlp(&self) -> super::vals::Irlp { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Irlp(val as u8) - } - #[doc = "IrDA low-power"] - pub fn set_irlp(&mut self, val: super::vals::Irlp) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "Half-duplex selection"] - pub const fn hdsel(&self) -> super::vals::Hdsel { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Hdsel(val as u8) - } - #[doc = "Half-duplex selection"] - pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "DMA enable receiver"] - pub const fn dmar(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "DMA enable receiver"] - pub fn set_dmar(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "DMA enable transmitter"] - pub const fn dmat(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "DMA enable transmitter"] - pub fn set_dmat(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - } - impl Default for Cr3 { - fn default() -> Cr3 { - Cr3(0) - } - } - #[doc = "Control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2(pub u32); - impl Cr2 { - #[doc = "Address of the USART node"] - pub const fn add(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Address of the USART node"] - pub fn set_add(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "lin break detection length"] - pub const fn lbdl(&self) -> super::vals::Lbdl { - let val = (self.0 >> 5usize) & 0x01; - super::vals::Lbdl(val as u8) - } - #[doc = "lin break detection length"] - pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); - } - #[doc = "LIN break detection interrupt enable"] - pub const fn lbdie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "LIN break detection interrupt enable"] - pub fn set_lbdie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "STOP bits"] - pub const fn stop(&self) -> super::vals::Stop { - let val = (self.0 >> 12usize) & 0x03; - super::vals::Stop(val as u8) - } - #[doc = "STOP bits"] - pub fn set_stop(&mut self, val: super::vals::Stop) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); - } - #[doc = "LIN mode enable"] - pub const fn linen(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "LIN mode enable"] - pub fn set_linen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - } - impl Default for Cr2 { - fn default() -> Cr2 { - Cr2(0) - } - } - #[doc = "Control register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1(pub u32); - impl Cr1 { - #[doc = "Send break"] - pub const fn sbk(&self) -> super::vals::Sbk { - let val = (self.0 >> 0usize) & 0x01; - super::vals::Sbk(val as u8) - } - #[doc = "Send break"] - pub fn set_sbk(&mut self, val: super::vals::Sbk) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); - } - #[doc = "Receiver wakeup"] - pub const fn rwu(&self) -> super::vals::Rwu { - let val = (self.0 >> 1usize) & 0x01; - super::vals::Rwu(val as u8) - } - #[doc = "Receiver wakeup"] - pub fn set_rwu(&mut self, val: super::vals::Rwu) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); - } - #[doc = "Receiver enable"] - pub const fn re(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Receiver enable"] - pub fn set_re(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Transmitter enable"] - pub const fn te(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Transmitter enable"] - pub fn set_te(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "IDLE interrupt enable"] - pub const fn idleie(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "IDLE interrupt enable"] - pub fn set_idleie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "RXNE interrupt enable"] - pub const fn rxneie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "RXNE interrupt enable"] - pub fn set_rxneie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Transmission complete interrupt enable"] - pub const fn tcie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Transmission complete interrupt enable"] - pub fn set_tcie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "TXE interrupt enable"] - pub const fn txeie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "TXE interrupt enable"] - pub fn set_txeie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "PE interrupt enable"] - pub const fn peie(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "PE interrupt enable"] - pub fn set_peie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Parity selection"] - pub const fn ps(&self) -> super::vals::Ps { - let val = (self.0 >> 9usize) & 0x01; - super::vals::Ps(val as u8) - } - #[doc = "Parity selection"] - pub fn set_ps(&mut self, val: super::vals::Ps) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); - } - #[doc = "Parity control enable"] - pub const fn pce(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "Parity control enable"] - pub fn set_pce(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "Wakeup method"] - pub const fn wake(&self) -> super::vals::Wake { - let val = (self.0 >> 11usize) & 0x01; - super::vals::Wake(val as u8) - } - #[doc = "Wakeup method"] - pub fn set_wake(&mut self, val: super::vals::Wake) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); - } - #[doc = "Word length"] - pub const fn m(&self) -> super::vals::M { - let val = (self.0 >> 12usize) & 0x01; - super::vals::M(val as u8) - } - #[doc = "Word length"] - pub fn set_m(&mut self, val: super::vals::M) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); - } - #[doc = "USART enable"] - pub const fn ue(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "USART enable"] - pub fn set_ue(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - } - impl Default for Cr1 { - fn default() -> Cr1 { - Cr1(0) - } - } - #[doc = "Baud rate register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Brr(pub u32); - impl Brr { - #[doc = "fraction of USARTDIV"] - pub const fn div_fraction(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "fraction of USARTDIV"] - pub fn set_div_fraction(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "mantissa of USARTDIV"] - pub const fn div_mantissa(&self) -> u16 { - let val = (self.0 >> 4usize) & 0x0fff; - val as u16 - } - #[doc = "mantissa of USARTDIV"] - pub fn set_div_mantissa(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize); - } - } - impl Default for Brr { - fn default() -> Brr { - Brr(0) - } - } - #[doc = "Status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Sr(pub u32); - impl Sr { - #[doc = "Parity error"] - pub const fn pe(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Parity error"] - pub fn set_pe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Framing error"] - pub const fn fe(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Framing error"] - pub fn set_fe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Noise error flag"] - pub const fn ne(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Noise error flag"] - pub fn set_ne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Overrun error"] - pub const fn ore(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Overrun error"] - pub fn set_ore(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "IDLE line detected"] - pub const fn idle(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "IDLE line detected"] - pub fn set_idle(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Read data register not empty"] - pub const fn rxne(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Read data register not empty"] - pub fn set_rxne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Transmission complete"] - pub const fn tc(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Transmission complete"] - pub fn set_tc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Transmit data register empty"] - pub const fn txe(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Transmit data register empty"] - pub fn set_txe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "LIN break detection flag"] - pub const fn lbd(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "LIN break detection flag"] - pub fn set_lbd(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for Sr { - fn default() -> Sr { - Sr(0) - } - } - #[doc = "Status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct SrUsart(pub u32); - impl SrUsart { - #[doc = "Parity error"] - pub const fn pe(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Parity error"] - pub fn set_pe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Framing error"] - pub const fn fe(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Framing error"] - pub fn set_fe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Noise error flag"] - pub const fn ne(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Noise error flag"] - pub fn set_ne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Overrun error"] - pub const fn ore(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Overrun error"] - pub fn set_ore(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "IDLE line detected"] - pub const fn idle(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "IDLE line detected"] - pub fn set_idle(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Read data register not empty"] - pub const fn rxne(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Read data register not empty"] - pub fn set_rxne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Transmission complete"] - pub const fn tc(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Transmission complete"] - pub fn set_tc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Transmit data register empty"] - pub const fn txe(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Transmit data register empty"] - pub fn set_txe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "LIN break detection flag"] - pub const fn lbd(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "LIN break detection flag"] - pub fn set_lbd(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "CTS flag"] - pub const fn cts(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "CTS flag"] - pub fn set_cts(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - } - impl Default for SrUsart { - fn default() -> SrUsart { - SrUsart(0) - } - } - #[doc = "Data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dr(pub u32); - impl Dr { - #[doc = "Data value"] - pub const fn dr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x01ff; - val as u16 - } - #[doc = "Data value"] - pub fn set_dr(&mut self, val: u16) { - self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize); - } - } - impl Default for Dr { - fn default() -> Dr { - Dr(0) - } - } - #[doc = "Control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2Usart(pub u32); - impl Cr2Usart { - #[doc = "Address of the USART node"] - pub const fn add(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Address of the USART node"] - pub fn set_add(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "lin break detection length"] - pub const fn lbdl(&self) -> super::vals::Lbdl { - let val = (self.0 >> 5usize) & 0x01; - super::vals::Lbdl(val as u8) - } - #[doc = "lin break detection length"] - pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); - } - #[doc = "LIN break detection interrupt enable"] - pub const fn lbdie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "LIN break detection interrupt enable"] - pub fn set_lbdie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Last bit clock pulse"] - pub const fn lbcl(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Last bit clock pulse"] - pub fn set_lbcl(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Clock phase"] - pub const fn cpha(&self) -> super::vals::Cpha { - let val = (self.0 >> 9usize) & 0x01; - super::vals::Cpha(val as u8) - } - #[doc = "Clock phase"] - pub fn set_cpha(&mut self, val: super::vals::Cpha) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); - } - #[doc = "Clock polarity"] - pub const fn cpol(&self) -> super::vals::Cpol { - let val = (self.0 >> 10usize) & 0x01; - super::vals::Cpol(val as u8) - } - #[doc = "Clock polarity"] - pub fn set_cpol(&mut self, val: super::vals::Cpol) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); - } - #[doc = "Clock enable"] - pub const fn clken(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "Clock enable"] - pub fn set_clken(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "STOP bits"] - pub const fn stop(&self) -> super::vals::Stop { - let val = (self.0 >> 12usize) & 0x03; - super::vals::Stop(val as u8) - } - #[doc = "STOP bits"] - pub fn set_stop(&mut self, val: super::vals::Stop) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); - } - #[doc = "LIN mode enable"] - pub const fn linen(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "LIN mode enable"] - pub fn set_linen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - } - impl Default for Cr2Usart { - fn default() -> Cr2Usart { - Cr2Usart(0) - } - } - } -} -pub mod syscfg_f4 { +pub mod syscfg_h7 { use crate::generic::*; #[doc = "System configuration controller"] #[derive(Copy, Clone)] @@ -5350,3327 +8245,8 @@ pub mod syscfg_f4 { unsafe impl Send for Syscfg {} unsafe impl Sync for Syscfg {} impl Syscfg { - #[doc = "memory remap register"] - pub fn memrm(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } #[doc = "peripheral mode configuration register"] - pub fn pmc(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "external interrupt configuration register"] - pub fn exticr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } - } - #[doc = "Compensation cell control register"] - pub fn cmpcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(32usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "memory remap register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Memrm(pub u32); - impl Memrm { - #[doc = "Memory mapping selection"] - pub const fn mem_mode(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Memory mapping selection"] - pub fn set_mem_mode(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Flash bank mode selection"] - pub const fn fb_mode(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Flash bank mode selection"] - pub fn set_fb_mode(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "FMC memory mapping swap"] - pub const fn swp_fmc(&self) -> u8 { - let val = (self.0 >> 10usize) & 0x03; - val as u8 - } - #[doc = "FMC memory mapping swap"] - pub fn set_swp_fmc(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize); - } - } - impl Default for Memrm { - fn default() -> Memrm { - Memrm(0) - } - } - #[doc = "Compensation cell control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cmpcr(pub u32); - impl Cmpcr { - #[doc = "Compensation cell power-down"] - pub const fn cmp_pd(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Compensation cell power-down"] - pub fn set_cmp_pd(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "READY"] - pub const fn ready(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "READY"] - pub fn set_ready(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for Cmpcr { - fn default() -> Cmpcr { - Cmpcr(0) - } - } - #[doc = "external interrupt configuration register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Exticr(pub u32); - impl Exticr { - #[doc = "EXTI x configuration"] - pub fn exti(&self, n: usize) -> u8 { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x0f; - val as u8 - } - #[doc = "EXTI x configuration"] - pub fn set_exti(&mut self, n: usize, val: u8) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); - } - } - impl Default for Exticr { - fn default() -> Exticr { - Exticr(0) - } - } - #[doc = "peripheral mode configuration register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pmc(pub u32); - impl Pmc { - #[doc = "ADC1DC2"] - pub const fn adc1dc2(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "ADC1DC2"] - pub fn set_adc1dc2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "ADC2DC2"] - pub const fn adc2dc2(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "ADC2DC2"] - pub fn set_adc2dc2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[doc = "ADC3DC2"] - pub const fn adc3dc2(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[doc = "ADC3DC2"] - pub fn set_adc3dc2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[doc = "Ethernet PHY interface selection"] - pub const fn mii_rmii_sel(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[doc = "Ethernet PHY interface selection"] - pub fn set_mii_rmii_sel(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - } - impl Default for Pmc { - fn default() -> Pmc { - Pmc(0) - } - } - } -} -pub mod sdmmc_v2 { - use crate::generic::*; - #[doc = "SDMMC"] - #[derive(Copy, Clone)] - pub struct Sdmmc(pub *mut u8); - unsafe impl Send for Sdmmc {} - unsafe impl Sync for Sdmmc {} - impl Sdmmc { - #[doc = "SDMMC power control register"] - pub fn power(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."] - pub fn clkcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."] - pub fn argr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."] - pub fn cmdr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "SDMMC command response register"] - pub fn respcmdr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] - pub fn respr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(20usize + n * 4usize)) } - } - #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."] - pub fn dtimer(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."] - pub fn dlenr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(40usize)) } - } - #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."] - pub fn dctrl(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(44usize)) } - } - #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."] - pub fn dcntr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(48usize)) } - } - #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"] - pub fn star(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(52usize)) } - } - #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."] - pub fn icr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(56usize)) } - } - #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."] - pub fn maskr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(60usize)) } - } - #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."] - pub fn acktimer(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(64usize)) } - } - #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."] - pub fn idmactrlr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(80usize)) } - } - #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."] - pub fn idmabsizer(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(84usize)) } - } - #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."] - pub fn idmabase0r(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(88usize)) } - } - #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."] - pub fn idmabase1r(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(92usize)) } - } - #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."] - pub fn fifor(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(128usize)) } - } - #[doc = "SDMMC IP version register"] - pub fn ver(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(1012usize)) } - } - #[doc = "SDMMC IP identification register"] - pub fn id(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(1016usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Star(pub u32); - impl Star { - #[doc = "Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn ccrcfail(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_ccrcfail(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn dcrcfail(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_dcrcfail(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods."] - pub const fn ctimeout(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods."] - pub fn set_ctimeout(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn dtimeout(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_dtimeout(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn txunderr(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_txunderr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn rxoverr(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_rxoverr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn cmdrend(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_cmdrend(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn cmdsent(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_cmdsent(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn dataend(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_dataend(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn dhold(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_dhold(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn dbckend(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_dbckend(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn dabort(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_dabort(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt."] - pub const fn dpsmact(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[doc = "Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt."] - pub fn set_dpsmact(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[doc = "Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt."] - pub const fn cpsmact(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt."] - pub fn set_cpsmact(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[doc = "Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full."] - pub const fn txfifohe(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full."] - pub fn set_txfifohe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[doc = "Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty."] - pub const fn rxfifohf(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[doc = "Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty."] - pub fn set_rxfifohf(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } - #[doc = "Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty."] - pub const fn txfifof(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty."] - pub fn set_txfifof(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "Receive FIFO full This bit is cleared when one FIFO location becomes empty."] - pub const fn rxfifof(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Receive FIFO full This bit is cleared when one FIFO location becomes empty."] - pub fn set_rxfifof(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[doc = "Transmit FIFO empty This bit is cleared when one FIFO location becomes full."] - pub const fn txfifoe(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[doc = "Transmit FIFO empty This bit is cleared when one FIFO location becomes full."] - pub fn set_txfifoe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[doc = "Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full."] - pub const fn rxfifoe(&self) -> bool { - let val = (self.0 >> 19usize) & 0x01; - val != 0 - } - #[doc = "Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full."] - pub fn set_rxfifoe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); - } - #[doc = "Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt."] - pub const fn busyd0(&self) -> bool { - let val = (self.0 >> 20usize) & 0x01; - val != 0 - } - #[doc = "Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt."] - pub fn set_busyd0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); - } - #[doc = "end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn busyd0end(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[doc = "end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_busyd0end(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[doc = "SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn sdioit(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[doc = "SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_sdioit(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[doc = "Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn ackfail(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[doc = "Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_ackfail(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - #[doc = "Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn acktimeout(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[doc = "Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_acktimeout(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[doc = "Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn vswend(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[doc = "Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_vswend(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[doc = "SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn ckstop(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[doc = "SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_ckstop(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[doc = "IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn idmate(&self) -> bool { - let val = (self.0 >> 27usize) & 0x01; - val != 0 - } - #[doc = "IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_idmate(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); - } - #[doc = "IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub const fn idmabtc(&self) -> bool { - let val = (self.0 >> 28usize) & 0x01; - val != 0 - } - #[doc = "IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] - pub fn set_idmabtc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); - } - } - impl Default for Star { - fn default() -> Star { - Star(0) - } - } - #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Icr(pub u32); - impl Icr { - #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] - pub const fn ccrcfailc(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] - pub fn set_ccrcfailc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] - pub const fn dcrcfailc(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] - pub fn set_dcrcfailc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] - pub const fn ctimeoutc(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] - pub fn set_ctimeoutc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] - pub const fn dtimeoutc(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] - pub fn set_dtimeoutc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] - pub const fn txunderrc(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] - pub fn set_txunderrc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] - pub const fn rxoverrc(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] - pub fn set_rxoverrc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] - pub const fn cmdrendc(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] - pub fn set_cmdrendc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] - pub const fn cmdsentc(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] - pub fn set_cmdsentc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] - pub const fn dataendc(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] - pub fn set_dataendc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] - pub const fn dholdc(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] - pub fn set_dholdc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] - pub const fn dbckendc(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] - pub fn set_dbckendc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] - pub const fn dabortc(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] - pub fn set_dabortc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] - pub const fn busyd0endc(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] - pub fn set_busyd0endc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] - pub const fn sdioitc(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] - pub fn set_sdioitc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] - pub const fn ackfailc(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] - pub fn set_ackfailc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] - pub const fn acktimeoutc(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] - pub fn set_acktimeoutc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] - pub const fn vswendc(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] - pub fn set_vswendc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] - pub const fn ckstopc(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] - pub fn set_ckstopc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] - pub const fn idmatec(&self) -> bool { - let val = (self.0 >> 27usize) & 0x01; - val != 0 - } - #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] - pub fn set_idmatec(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); - } - #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] - pub const fn idmabtcc(&self) -> bool { - let val = (self.0 >> 28usize) & 0x01; - val != 0 - } - #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] - pub fn set_idmabtcc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); - } - } - impl Default for Icr { - fn default() -> Icr { - Icr(0) - } - } - #[doc = "SDMMC command response register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Respcmdr(pub u32); - impl Respcmdr { - #[doc = "Response command index"] - pub const fn respcmd(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; - val as u8 - } - #[doc = "Response command index"] - pub fn set_respcmd(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); - } - } - impl Default for Respcmdr { - fn default() -> Respcmdr { - Respcmdr(0) - } - } - #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Maskr(pub u32); - impl Maskr { - #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."] - pub const fn ccrcfailie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."] - pub fn set_ccrcfailie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."] - pub const fn dcrcfailie(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."] - pub fn set_dcrcfailie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."] - pub const fn ctimeoutie(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."] - pub fn set_ctimeoutie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."] - pub const fn dtimeoutie(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."] - pub fn set_dtimeoutie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."] - pub const fn txunderrie(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."] - pub fn set_txunderrie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."] - pub const fn rxoverrie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."] - pub fn set_rxoverrie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."] - pub const fn cmdrendie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."] - pub fn set_cmdrendie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."] - pub const fn cmdsentie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."] - pub fn set_cmdsentie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."] - pub const fn dataendie(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."] - pub fn set_dataendie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."] - pub const fn dholdie(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."] - pub fn set_dholdie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."] - pub const fn dbckendie(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."] - pub fn set_dbckendie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."] - pub const fn dabortie(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."] - pub fn set_dabortie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."] - pub const fn txfifoheie(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."] - pub fn set_txfifoheie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."] - pub const fn rxfifohfie(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."] - pub fn set_rxfifohfie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } - #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."] - pub const fn rxfifofie(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."] - pub fn set_rxfifofie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."] - pub const fn txfifoeie(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."] - pub fn set_txfifoeie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."] - pub const fn busyd0endie(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."] - pub fn set_busyd0endie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."] - pub const fn sdioitie(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."] - pub fn set_sdioitie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."] - pub const fn ackfailie(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."] - pub fn set_ackfailie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."] - pub const fn acktimeoutie(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."] - pub fn set_acktimeoutie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."] - pub const fn vswendie(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."] - pub fn set_vswendie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."] - pub const fn ckstopie(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."] - pub fn set_ckstopie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."] - pub const fn idmabtcie(&self) -> bool { - let val = (self.0 >> 28usize) & 0x01; - val != 0 - } - #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."] - pub fn set_idmabtcie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); - } - } - impl Default for Maskr { - fn default() -> Maskr { - Maskr(0) - } - } - #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cmdr(pub u32); - impl Cmdr { - #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."] - pub const fn cmdindex(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; - val as u8 - } - #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."] - pub fn set_cmdindex(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); - } - #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."] - pub const fn cmdtrans(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."] - pub fn set_cmdtrans(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."] - pub const fn cmdstop(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."] - pub fn set_cmdstop(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."] - pub const fn waitresp(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x03; - val as u8 - } - #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."] - pub fn set_waitresp(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); - } - #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."] - pub const fn waitint(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."] - pub fn set_waitint(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."] - pub const fn waitpend(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."] - pub fn set_waitpend(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."] - pub const fn cpsmen(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."] - pub fn set_cpsmen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."] - pub const fn dthold(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."] - pub fn set_dthold(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"] - pub const fn bootmode(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"] - pub fn set_bootmode(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[doc = "Enable boot mode procedure."] - pub const fn booten(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[doc = "Enable boot mode procedure."] - pub fn set_booten(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } - #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."] - pub const fn cmdsuspend(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."] - pub fn set_cmdsuspend(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Cmdr { - fn default() -> Cmdr { - Cmdr(0) - } - } - #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idmabsizer(pub u32); - impl Idmabsizer { - #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn idmabndt(&self) -> u8 { - let val = (self.0 >> 5usize) & 0xff; - val as u8 - } - #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_idmabndt(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 5usize)) | (((val as u32) & 0xff) << 5usize); - } - } - impl Default for Idmabsizer { - fn default() -> Idmabsizer { - Idmabsizer(0) - } - } - #[doc = "SDMMC power control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Power(pub u32); - impl Power { - #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."] - pub const fn pwrctrl(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x03; - val as u8 - } - #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."] - pub fn set_pwrctrl(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); - } - #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"] - pub const fn vswitch(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"] - pub fn set_vswitch(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"] - pub const fn vswitchen(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"] - pub fn set_vswitchen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."] - pub const fn dirpol(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."] - pub fn set_dirpol(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - } - impl Default for Power { - fn default() -> Power { - Power(0) - } - } - #[doc = "SDMMC IP identification register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Id(pub u32); - impl Id { - #[doc = "SDMMC IP identification."] - pub const fn ip_id(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "SDMMC IP identification."] - pub fn set_ip_id(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Id { - fn default() -> Id { - Id(0) - } - } - #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dtimer(pub u32); - impl Dtimer { - #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] - pub const fn datatime(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] - pub fn set_datatime(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Dtimer { - fn default() -> Dtimer { - Dtimer(0) - } - } - #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Resp1r(pub u32); - impl Resp1r { - #[doc = "see Table 432"] - pub const fn cardstatus1(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "see Table 432"] - pub fn set_cardstatus1(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Resp1r { - fn default() -> Resp1r { - Resp1r(0) - } - } - #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dctrl(pub u32); - impl Dctrl { - #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."] - pub const fn dten(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."] - pub fn set_dten(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn dtdir(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_dtdir(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn dtmode(&self) -> u8 { - let val = (self.0 >> 2usize) & 0x03; - val as u8 - } - #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_dtmode(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize); - } - #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"] - pub const fn dblocksize(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 - } - #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"] - pub fn set_dblocksize(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); - } - #[doc = "Read wait start. If this bit is set, read wait operation starts."] - pub const fn rwstart(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Read wait start. If this bit is set, read wait operation starts."] - pub fn set_rwstart(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."] - pub const fn rwstop(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."] - pub fn set_rwstop(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn rwmod(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_rwmod(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."] - pub const fn sdioen(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."] - pub fn set_sdioen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn bootacken(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_bootacken(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."] - pub const fn fiforst(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."] - pub fn set_fiforst(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - } - impl Default for Dctrl { - fn default() -> Dctrl { - Dctrl(0) - } - } - #[doc = "SDMMC IP version register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ver(pub u32); - impl Ver { - #[doc = "IP minor revision number."] - pub const fn minrev(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "IP minor revision number."] - pub fn set_minrev(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "IP major revision number."] - pub const fn majrev(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 - } - #[doc = "IP major revision number."] - pub fn set_majrev(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); - } - } - impl Default for Ver { - fn default() -> Ver { - Ver(0) - } - } - #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dcntr(pub u32); - impl Dcntr { - #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] - pub const fn datacount(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x01ff_ffff; - val as u32 - } - #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] - pub fn set_datacount(&mut self, val: u32) { - self.0 = - (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); - } - } - impl Default for Dcntr { - fn default() -> Dcntr { - Dcntr(0) - } - } - #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Resp3r(pub u32); - impl Resp3r { - #[doc = "see Table404."] - pub const fn cardstatus3(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "see Table404."] - pub fn set_cardstatus3(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Resp3r { - fn default() -> Resp3r { - Resp3r(0) - } - } - #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Resp2r(pub u32); - impl Resp2r { - #[doc = "see Table404."] - pub const fn cardstatus2(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "see Table404."] - pub fn set_cardstatus2(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Resp2r { - fn default() -> Resp2r { - Resp2r(0) - } - } - #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Acktimer(pub u32); - impl Acktimer { - #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] - pub const fn acktime(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x01ff_ffff; - val as u32 - } - #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] - pub fn set_acktime(&mut self, val: u32) { - self.0 = - (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); - } - } - impl Default for Acktimer { - fn default() -> Acktimer { - Acktimer(0) - } - } - #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dlenr(pub u32); - impl Dlenr { - #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."] - pub const fn datalength(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x01ff_ffff; - val as u32 - } - #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."] - pub fn set_datalength(&mut self, val: u32) { - self.0 = - (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); - } - } - impl Default for Dlenr { - fn default() -> Dlenr { - Dlenr(0) - } - } - #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idmactrlr(pub u32); - impl Idmactrlr { - #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn idmaen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_idmaen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn idmabmode(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_idmabmode(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."] - pub const fn idmabact(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."] - pub fn set_idmabact(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - } - impl Default for Idmactrlr { - fn default() -> Idmactrlr { - Idmactrlr(0) - } - } - #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Argr(pub u32); - impl Argr { - #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] - pub const fn cmdarg(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] - pub fn set_cmdarg(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Argr { - fn default() -> Argr { - Argr(0) - } - } - #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Resp4r(pub u32); - impl Resp4r { - #[doc = "see Table404."] - pub const fn cardstatus4(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "see Table404."] - pub fn set_cardstatus4(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Resp4r { - fn default() -> Resp4r { - Resp4r(0) - } - } - #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idmabase1r(pub u32); - impl Idmabase1r { - #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] -are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] - pub const fn idmabase1(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] -are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] - pub fn set_idmabase1(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Idmabase1r { - fn default() -> Idmabase1r { - Idmabase1r(0) - } - } - #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Fifor(pub u32); - impl Fifor { - #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] - pub const fn fifodata(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] - pub fn set_fifodata(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Fifor { - fn default() -> Fifor { - Fifor(0) - } - } - #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idmabase0r(pub u32); - impl Idmabase0r { - #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] -are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."] - pub const fn idmabase0(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] -are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."] - pub fn set_idmabase0(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Idmabase0r { - fn default() -> Idmabase0r { - Idmabase0r(0) - } - } - #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Clkcr(pub u32); - impl Clkcr { - #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] - pub const fn clkdiv(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x03ff; - val as u16 - } - #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] - pub fn set_clkdiv(&mut self, val: u16) { - self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize); - } - #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] - pub const fn pwrsav(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] - pub fn set_pwrsav(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub const fn widbus(&self) -> u8 { - let val = (self.0 >> 14usize) & 0x03; - val as u8 - } - #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub fn set_widbus(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize); - } - #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] - pub const fn negedge(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] - pub fn set_negedge(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] - pub const fn hwfc_en(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] - pub fn set_hwfc_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] - pub const fn ddr(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] - pub fn set_ddr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub const fn busspeed(&self) -> bool { - let val = (self.0 >> 19usize) & 0x01; - val != 0 - } - #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub fn set_busspeed(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); - } - #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub const fn selclkrx(&self) -> u8 { - let val = (self.0 >> 20usize) & 0x03; - val as u8 - } - #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub fn set_selclkrx(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize); - } - } - impl Default for Clkcr { - fn default() -> Clkcr { - Clkcr(0) - } - } - } -} -pub mod gpio_v2 { - use crate::generic::*; - #[doc = "General-purpose I/Os"] - #[derive(Copy, Clone)] - pub struct Gpio(pub *mut u8); - unsafe impl Send for Gpio {} - unsafe impl Sync for Gpio {} - impl Gpio { - #[doc = "GPIO port mode register"] - pub fn moder(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "GPIO port output type register"] - pub fn otyper(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "GPIO port output speed register"] - pub fn ospeedr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "GPIO port pull-up/pull-down register"] - pub fn pupdr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "GPIO port input data register"] - pub fn idr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "GPIO port output data register"] - pub fn odr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "GPIO port bit set/reset register"] - pub fn bsrr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } - } - #[doc = "GPIO port configuration lock register"] - pub fn lckr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(28usize)) } - } - #[doc = "GPIO alternate function register (low, high)"] - pub fn afr(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(32usize + n * 4usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "GPIO port output type register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Otyper(pub u32); - impl Otyper { - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn ot(&self, n: usize) -> super::vals::Ot { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Ot(val as u8) - } - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn set_ot(&mut self, n: usize, val: super::vals::Ot) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Otyper { - fn default() -> Otyper { - Otyper(0) - } - } - #[doc = "GPIO port pull-up/pull-down register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pupdr(pub u32); - impl Pupdr { - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn pupdr(&self, n: usize) -> super::vals::Pupdr { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Pupdr(val as u8) - } - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn set_pupdr(&mut self, n: usize, val: super::vals::Pupdr) { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - } - impl Default for Pupdr { - fn default() -> Pupdr { - Pupdr(0) - } - } - #[doc = "GPIO port output speed register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ospeedr(pub u32); - impl Ospeedr { - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Ospeedr(val as u8) - } - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - } - impl Default for Ospeedr { - fn default() -> Ospeedr { - Ospeedr(0) - } - } - #[doc = "GPIO port bit set/reset register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Bsrr(pub u32); - impl Bsrr { - #[doc = "Port x set bit y (y= 0..15)"] - pub fn bs(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Port x set bit y (y= 0..15)"] - pub fn set_bs(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Port x set bit y (y= 0..15)"] - pub fn br(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 16usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Port x set bit y (y= 0..15)"] - pub fn set_br(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 16usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Bsrr { - fn default() -> Bsrr { - Bsrr(0) - } - } - #[doc = "GPIO alternate function register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Afr(pub u32); - impl Afr { - #[doc = "Alternate function selection for port x bit y (y = 0..15)"] - pub fn afr(&self, n: usize) -> super::vals::Afr { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x0f; - super::vals::Afr(val as u8) - } - #[doc = "Alternate function selection for port x bit y (y = 0..15)"] - pub fn set_afr(&mut self, n: usize, val: super::vals::Afr) { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); - } - } - impl Default for Afr { - fn default() -> Afr { - Afr(0) - } - } - #[doc = "GPIO port output data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Odr(pub u32); - impl Odr { - #[doc = "Port output data (y = 0..15)"] - pub fn odr(&self, n: usize) -> super::vals::Odr { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Odr(val as u8) - } - #[doc = "Port output data (y = 0..15)"] - pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Odr { - fn default() -> Odr { - Odr(0) - } - } - #[doc = "GPIO port mode register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Moder(pub u32); - impl Moder { - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn moder(&self, n: usize) -> super::vals::Moder { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Moder(val as u8) - } - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - } - impl Default for Moder { - fn default() -> Moder { - Moder(0) - } - } - #[doc = "GPIO port input data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idr(pub u32); - impl Idr { - #[doc = "Port input data (y = 0..15)"] - pub fn idr(&self, n: usize) -> super::vals::Idr { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Idr(val as u8) - } - #[doc = "Port input data (y = 0..15)"] - pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Idr { - fn default() -> Idr { - Idr(0) - } - } - #[doc = "GPIO port configuration lock register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Lckr(pub u32); - impl Lckr { - #[doc = "Port x lock bit y (y= 0..15)"] - pub fn lck(&self, n: usize) -> super::vals::Lck { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Lck(val as u8) - } - #[doc = "Port x lock bit y (y= 0..15)"] - pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - #[doc = "Port x lock bit y (y= 0..15)"] - pub const fn lckk(&self) -> super::vals::Lckk { - let val = (self.0 >> 16usize) & 0x01; - super::vals::Lckk(val as u8) - } - #[doc = "Port x lock bit y (y= 0..15)"] - pub fn set_lckk(&mut self, val: super::vals::Lckk) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); - } - } - impl Default for Lckr { - fn default() -> Lckr { - Lckr(0) - } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lck(pub u8); - impl Lck { - #[doc = "Port configuration not locked"] - pub const UNLOCKED: Self = Self(0); - #[doc = "Port configuration locked"] - pub const LOCKED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pupdr(pub u8); - impl Pupdr { - #[doc = "No pull-up, pull-down"] - pub const FLOATING: Self = Self(0); - #[doc = "Pull-up"] - pub const PULLUP: Self = Self(0x01); - #[doc = "Pull-down"] - pub const PULLDOWN: Self = Self(0x02); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Idr(pub u8); - impl Idr { - #[doc = "Input is logic low"] - pub const LOW: Self = Self(0); - #[doc = "Input is logic high"] - pub const HIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ot(pub u8); - impl Ot { - #[doc = "Output push-pull (reset state)"] - pub const PUSHPULL: Self = Self(0); - #[doc = "Output open-drain"] - pub const OPENDRAIN: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ospeedr(pub u8); - impl Ospeedr { - #[doc = "Low speed"] - pub const LOWSPEED: Self = Self(0); - #[doc = "Medium speed"] - pub const MEDIUMSPEED: Self = Self(0x01); - #[doc = "High speed"] - pub const HIGHSPEED: Self = Self(0x02); - #[doc = "Very high speed"] - pub const VERYHIGHSPEED: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bsw(pub u8); - impl Bsw { - #[doc = "Sets the corresponding ODRx bit"] - pub const SET: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lckk(pub u8); - impl Lckk { - #[doc = "Port configuration lock key not active"] - pub const NOTACTIVE: Self = Self(0); - #[doc = "Port configuration lock key active"] - pub const ACTIVE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Moder(pub u8); - impl Moder { - #[doc = "Input mode (reset state)"] - pub const INPUT: Self = Self(0); - #[doc = "General purpose output mode"] - pub const OUTPUT: Self = Self(0x01); - #[doc = "Alternate function mode"] - pub const ALTERNATE: Self = Self(0x02); - #[doc = "Analog mode"] - pub const ANALOG: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Brw(pub u8); - impl Brw { - #[doc = "Resets the corresponding ODRx bit"] - pub const RESET: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Afr(pub u8); - impl Afr { - #[doc = "AF0"] - pub const AF0: Self = Self(0); - #[doc = "AF1"] - pub const AF1: Self = Self(0x01); - #[doc = "AF2"] - pub const AF2: Self = Self(0x02); - #[doc = "AF3"] - pub const AF3: Self = Self(0x03); - #[doc = "AF4"] - pub const AF4: Self = Self(0x04); - #[doc = "AF5"] - pub const AF5: Self = Self(0x05); - #[doc = "AF6"] - pub const AF6: Self = Self(0x06); - #[doc = "AF7"] - pub const AF7: Self = Self(0x07); - #[doc = "AF8"] - pub const AF8: Self = Self(0x08); - #[doc = "AF9"] - pub const AF9: Self = Self(0x09); - #[doc = "AF10"] - pub const AF10: Self = Self(0x0a); - #[doc = "AF11"] - pub const AF11: Self = Self(0x0b); - #[doc = "AF12"] - pub const AF12: Self = Self(0x0c); - #[doc = "AF13"] - pub const AF13: Self = Self(0x0d); - #[doc = "AF14"] - pub const AF14: Self = Self(0x0e); - #[doc = "AF15"] - pub const AF15: Self = Self(0x0f); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Odr(pub u8); - impl Odr { - #[doc = "Set output to logic low"] - pub const LOW: Self = Self(0); - #[doc = "Set output to logic high"] - pub const HIGH: Self = Self(0x01); - } - } -} -pub mod spi_v1 { - use crate::generic::*; - #[doc = "Serial peripheral interface"] - #[derive(Copy, Clone)] - pub struct Spi(pub *mut u8); - unsafe impl Send for Spi {} - unsafe impl Sync for Spi {} - impl Spi { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "data register"] - pub fn dr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "CRC polynomial register"] - pub fn crcpr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "RX CRC register"] - pub fn rxcrcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "TX CRC register"] - pub fn txcrcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "TX CRC register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Txcrcr(pub u32); - impl Txcrcr { - #[doc = "Tx CRC register"] - pub const fn tx_crc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Tx CRC register"] - pub fn set_tx_crc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Txcrcr { - fn default() -> Txcrcr { - Txcrcr(0) - } - } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Sr(pub u32); - impl Sr { - #[doc = "Receive buffer not empty"] - pub const fn rxne(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Receive buffer not empty"] - pub fn set_rxne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Transmit buffer empty"] - pub const fn txe(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Transmit buffer empty"] - pub fn set_txe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "CRC error flag"] - pub const fn crcerr(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "CRC error flag"] - pub fn set_crcerr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Mode fault"] - pub const fn modf(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Mode fault"] - pub fn set_modf(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Overrun flag"] - pub const fn ovr(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Overrun flag"] - pub fn set_ovr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Busy flag"] - pub const fn bsy(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Busy flag"] - pub fn set_bsy(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "TI frame format error"] - pub const fn fre(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "TI frame format error"] - pub fn set_fre(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for Sr { - fn default() -> Sr { - Sr(0) - } - } - #[doc = "CRC polynomial register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Crcpr(pub u32); - impl Crcpr { - #[doc = "CRC polynomial register"] - pub const fn crcpoly(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "CRC polynomial register"] - pub fn set_crcpoly(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Crcpr { - fn default() -> Crcpr { - Crcpr(0) - } - } - #[doc = "RX CRC register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Rxcrcr(pub u32); - impl Rxcrcr { - #[doc = "Rx CRC register"] - pub const fn rx_crc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Rx CRC register"] - pub fn set_rx_crc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Rxcrcr { - fn default() -> Rxcrcr { - Rxcrcr(0) - } - } - #[doc = "data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dr(pub u32); - impl Dr { - #[doc = "Data register"] - pub const fn dr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Data register"] - pub fn set_dr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Dr { - fn default() -> Dr { - Dr(0) - } - } - #[doc = "control register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1(pub u32); - impl Cr1 { - #[doc = "Clock phase"] - pub const fn cpha(&self) -> super::vals::Cpha { - let val = (self.0 >> 0usize) & 0x01; - super::vals::Cpha(val as u8) - } - #[doc = "Clock phase"] - pub fn set_cpha(&mut self, val: super::vals::Cpha) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); - } - #[doc = "Clock polarity"] - pub const fn cpol(&self) -> super::vals::Cpol { - let val = (self.0 >> 1usize) & 0x01; - super::vals::Cpol(val as u8) - } - #[doc = "Clock polarity"] - pub fn set_cpol(&mut self, val: super::vals::Cpol) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); - } - #[doc = "Master selection"] - pub const fn mstr(&self) -> super::vals::Mstr { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Mstr(val as u8) - } - #[doc = "Master selection"] - pub fn set_mstr(&mut self, val: super::vals::Mstr) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "Baud rate control"] - pub const fn br(&self) -> super::vals::Br { - let val = (self.0 >> 3usize) & 0x07; - super::vals::Br(val as u8) - } - #[doc = "Baud rate control"] - pub fn set_br(&mut self, val: super::vals::Br) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); - } - #[doc = "SPI enable"] - pub const fn spe(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "SPI enable"] - pub fn set_spe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Frame format"] - pub const fn lsbfirst(&self) -> super::vals::Lsbfirst { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Lsbfirst(val as u8) - } - #[doc = "Frame format"] - pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Internal slave select"] - pub const fn ssi(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Internal slave select"] - pub fn set_ssi(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Software slave management"] - pub const fn ssm(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Software slave management"] - pub fn set_ssm(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Receive only"] - pub const fn rxonly(&self) -> super::vals::Rxonly { - let val = (self.0 >> 10usize) & 0x01; - super::vals::Rxonly(val as u8) - } - #[doc = "Receive only"] - pub fn set_rxonly(&mut self, val: super::vals::Rxonly) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); - } - #[doc = "Data frame format"] - pub const fn dff(&self) -> super::vals::Dff { - let val = (self.0 >> 11usize) & 0x01; - super::vals::Dff(val as u8) - } - #[doc = "Data frame format"] - pub fn set_dff(&mut self, val: super::vals::Dff) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); - } - #[doc = "CRC transfer next"] - pub const fn crcnext(&self) -> super::vals::Crcnext { - let val = (self.0 >> 12usize) & 0x01; - super::vals::Crcnext(val as u8) - } - #[doc = "CRC transfer next"] - pub fn set_crcnext(&mut self, val: super::vals::Crcnext) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); - } - #[doc = "Hardware CRC calculation enable"] - pub const fn crcen(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "Hardware CRC calculation enable"] - pub fn set_crcen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[doc = "Output enable in bidirectional mode"] - pub const fn bidioe(&self) -> super::vals::Bidioe { - let val = (self.0 >> 14usize) & 0x01; - super::vals::Bidioe(val as u8) - } - #[doc = "Output enable in bidirectional mode"] - pub fn set_bidioe(&mut self, val: super::vals::Bidioe) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); - } - #[doc = "Bidirectional data mode enable"] - pub const fn bidimode(&self) -> super::vals::Bidimode { - let val = (self.0 >> 15usize) & 0x01; - super::vals::Bidimode(val as u8) - } - #[doc = "Bidirectional data mode enable"] - pub fn set_bidimode(&mut self, val: super::vals::Bidimode) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); - } - } - impl Default for Cr1 { - fn default() -> Cr1 { - Cr1(0) - } - } - #[doc = "control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2(pub u32); - impl Cr2 { - #[doc = "Rx buffer DMA enable"] - pub const fn rxdmaen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Rx buffer DMA enable"] - pub fn set_rxdmaen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Tx buffer DMA enable"] - pub const fn txdmaen(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Tx buffer DMA enable"] - pub fn set_txdmaen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "SS output enable"] - pub const fn ssoe(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "SS output enable"] - pub fn set_ssoe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Frame format"] - pub const fn frf(&self) -> super::vals::Frf { - let val = (self.0 >> 4usize) & 0x01; - super::vals::Frf(val as u8) - } - #[doc = "Frame format"] - pub fn set_frf(&mut self, val: super::vals::Frf) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); - } - #[doc = "Error interrupt enable"] - pub const fn errie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Error interrupt enable"] - pub fn set_errie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "RX buffer not empty interrupt enable"] - pub const fn rxneie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "RX buffer not empty interrupt enable"] - pub fn set_rxneie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Tx buffer empty interrupt enable"] - pub const fn txeie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Tx buffer empty interrupt enable"] - pub fn set_txeie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - } - impl Default for Cr2 { - fn default() -> Cr2 { - Cr2(0) - } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Crcnext(pub u8); - impl Crcnext { - #[doc = "Next transmit value is from Tx buffer"] - pub const TXBUFFER: Self = Self(0); - #[doc = "Next transmit value is from Tx CRC register"] - pub const CRC: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpha(pub u8); - impl Cpha { - #[doc = "The first clock transition is the first data capture edge"] - pub const FIRSTEDGE: Self = Self(0); - #[doc = "The second clock transition is the first data capture edge"] - pub const SECONDEDGE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Iscfg(pub u8); - impl Iscfg { - #[doc = "Slave - transmit"] - pub const SLAVETX: Self = Self(0); - #[doc = "Slave - receive"] - pub const SLAVERX: Self = Self(0x01); - #[doc = "Master - transmit"] - pub const MASTERTX: Self = Self(0x02); - #[doc = "Master - receive"] - pub const MASTERRX: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Br(pub u8); - impl Br { - #[doc = "f_PCLK / 2"] - pub const DIV2: Self = Self(0); - #[doc = "f_PCLK / 4"] - pub const DIV4: Self = Self(0x01); - #[doc = "f_PCLK / 8"] - pub const DIV8: Self = Self(0x02); - #[doc = "f_PCLK / 16"] - pub const DIV16: Self = Self(0x03); - #[doc = "f_PCLK / 32"] - pub const DIV32: Self = Self(0x04); - #[doc = "f_PCLK / 64"] - pub const DIV64: Self = Self(0x05); - #[doc = "f_PCLK / 128"] - pub const DIV128: Self = Self(0x06); - #[doc = "f_PCLK / 256"] - pub const DIV256: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bidimode(pub u8); - impl Bidimode { - #[doc = "2-line unidirectional data mode selected"] - pub const UNIDIRECTIONAL: Self = Self(0); - #[doc = "1-line bidirectional data mode selected"] - pub const BIDIRECTIONAL: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Rxonly(pub u8); - impl Rxonly { - #[doc = "Full duplex (Transmit and receive)"] - pub const FULLDUPLEX: Self = Self(0); - #[doc = "Output disabled (Receive-only mode)"] - pub const OUTPUTDISABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpol(pub u8); - impl Cpol { - #[doc = "CK to 0 when idle"] - pub const IDLELOW: Self = Self(0); - #[doc = "CK to 1 when idle"] - pub const IDLEHIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lsbfirst(pub u8); - impl Lsbfirst { - #[doc = "Data is transmitted/received with the MSB first"] - pub const MSBFIRST: Self = Self(0); - #[doc = "Data is transmitted/received with the LSB first"] - pub const LSBFIRST: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dff(pub u8); - impl Dff { - #[doc = "8-bit data frame format is selected for transmission/reception"] - pub const EIGHTBIT: Self = Self(0); - #[doc = "16-bit data frame format is selected for transmission/reception"] - pub const SIXTEENBIT: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bidioe(pub u8); - impl Bidioe { - #[doc = "Output disabled (receive-only mode)"] - pub const OUTPUTDISABLED: Self = Self(0); - #[doc = "Output enabled (transmit-only mode)"] - pub const OUTPUTENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frer(pub u8); - impl Frer { - #[doc = "No frame format error"] - pub const NOERROR: Self = Self(0); - #[doc = "A frame format error occurred"] - pub const ERROR: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mstr(pub u8); - impl Mstr { - #[doc = "Slave configuration"] - pub const SLAVE: Self = Self(0); - #[doc = "Master configuration"] - pub const MASTER: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frf(pub u8); - impl Frf { - #[doc = "SPI Motorola mode"] - pub const MOTOROLA: Self = Self(0); - #[doc = "SPI TI mode"] - pub const TI: Self = Self(0x01); - } - } -} -pub mod dma_v1 { - use crate::generic::*; - #[doc = "DMA controller"] - #[derive(Copy, Clone)] - pub struct Dma(pub *mut u8); - unsafe impl Send for Dma {} - unsafe impl Sync for Dma {} - impl Dma { - #[doc = "DMA interrupt status register (DMA_ISR)"] - pub fn isr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] - pub fn ifcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] - pub fn ch(self, n: usize) -> Ch { - assert!(n < 7usize); - unsafe { Ch(self.0.add(8usize + n * 20usize)) } - } - } - #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] - #[derive(Copy, Clone)] - pub struct Ch(pub *mut u8); - unsafe impl Send for Ch {} - unsafe impl Sync for Ch {} - impl Ch { - #[doc = "DMA channel configuration register (DMA_CCR)"] - pub fn cr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "DMA channel 1 number of data register"] - pub fn ndtr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "DMA channel 1 peripheral address register"] - pub fn par(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "DMA channel 1 memory address register"] - pub fn mar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ifcr(pub u32); - impl Ifcr { - #[doc = "Channel 1 Global interrupt clear"] - pub fn cgif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Global interrupt clear"] - pub fn set_cgif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Transfer Complete clear"] - pub fn ctcif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 1usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Transfer Complete clear"] - pub fn set_ctcif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 1usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Half Transfer clear"] - pub fn chtif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 2usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Half Transfer clear"] - pub fn set_chtif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 2usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Transfer Error clear"] - pub fn cteif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 3usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Transfer Error clear"] - pub fn set_cteif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 3usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Ifcr { - fn default() -> Ifcr { - Ifcr(0) - } - } - #[doc = "DMA interrupt status register (DMA_ISR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Isr(pub u32); - impl Isr { - #[doc = "Channel 1 Global interrupt flag"] - pub fn gif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Global interrupt flag"] - pub fn set_gif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Transfer Complete flag"] - pub fn tcif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 1usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Transfer Complete flag"] - pub fn set_tcif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 1usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Half Transfer Complete flag"] - pub fn htif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 2usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Half Transfer Complete flag"] - pub fn set_htif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 2usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Transfer Error flag"] - pub fn teif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 3usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Transfer Error flag"] - pub fn set_teif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 3usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Isr { - fn default() -> Isr { - Isr(0) - } - } - #[doc = "DMA channel configuration register (DMA_CCR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr(pub u32); - impl Cr { - #[doc = "Channel enable"] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Channel enable"] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Transfer complete interrupt enable"] - pub const fn tcie(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Transfer complete interrupt enable"] - pub fn set_tcie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Half Transfer interrupt enable"] - pub const fn htie(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Half Transfer interrupt enable"] - pub fn set_htie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Transfer error interrupt enable"] - pub const fn teie(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Transfer error interrupt enable"] - pub fn set_teie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Data transfer direction"] - pub const fn dir(&self) -> super::vals::Dir { - let val = (self.0 >> 4usize) & 0x01; - super::vals::Dir(val as u8) - } - #[doc = "Data transfer direction"] - pub fn set_dir(&mut self, val: super::vals::Dir) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); - } - #[doc = "Circular mode"] - pub const fn circ(&self) -> super::vals::Circ { - let val = (self.0 >> 5usize) & 0x01; - super::vals::Circ(val as u8) - } - #[doc = "Circular mode"] - pub fn set_circ(&mut self, val: super::vals::Circ) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); - } - #[doc = "Peripheral increment mode"] - pub const fn pinc(&self) -> super::vals::Inc { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Inc(val as u8) - } - #[doc = "Peripheral increment mode"] - pub fn set_pinc(&mut self, val: super::vals::Inc) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize); - } - #[doc = "Memory increment mode"] - pub const fn minc(&self) -> super::vals::Inc { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Inc(val as u8) - } - #[doc = "Memory increment mode"] - pub fn set_minc(&mut self, val: super::vals::Inc) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Peripheral size"] - pub const fn psize(&self) -> super::vals::Size { - let val = (self.0 >> 8usize) & 0x03; - super::vals::Size(val as u8) - } - #[doc = "Peripheral size"] - pub fn set_psize(&mut self, val: super::vals::Size) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); - } - #[doc = "Memory size"] - pub const fn msize(&self) -> super::vals::Size { - let val = (self.0 >> 10usize) & 0x03; - super::vals::Size(val as u8) - } - #[doc = "Memory size"] - pub fn set_msize(&mut self, val: super::vals::Size) { - self.0 = (self.0 & !(0x03 << 10usize)) | (((val.0 as u32) & 0x03) << 10usize); - } - #[doc = "Channel Priority level"] - pub const fn pl(&self) -> super::vals::Pl { - let val = (self.0 >> 12usize) & 0x03; - super::vals::Pl(val as u8) - } - #[doc = "Channel Priority level"] - pub fn set_pl(&mut self, val: super::vals::Pl) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); - } - #[doc = "Memory to memory mode"] - pub const fn mem2mem(&self) -> super::vals::Memmem { - let val = (self.0 >> 14usize) & 0x01; - super::vals::Memmem(val as u8) - } - #[doc = "Memory to memory mode"] - pub fn set_mem2mem(&mut self, val: super::vals::Memmem) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); - } - } - impl Default for Cr { - fn default() -> Cr { - Cr(0) - } - } - #[doc = "DMA channel 1 number of data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ndtr(pub u32); - impl Ndtr { - #[doc = "Number of data to transfer"] - pub const fn ndt(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Number of data to transfer"] - pub fn set_ndt(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Ndtr { - fn default() -> Ndtr { - Ndtr(0) - } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dir(pub u8); - impl Dir { - #[doc = "Read from peripheral"] - pub const FROMPERIPHERAL: Self = Self(0); - #[doc = "Read from memory"] - pub const FROMMEMORY: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Circ(pub u8); - impl Circ { - #[doc = "Circular buffer disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Circular buffer enabled"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pl(pub u8); - impl Pl { - #[doc = "Low priority"] - pub const LOW: Self = Self(0); - #[doc = "Medium priority"] - pub const MEDIUM: Self = Self(0x01); - #[doc = "High priority"] - pub const HIGH: Self = Self(0x02); - #[doc = "Very high priority"] - pub const VERYHIGH: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Inc(pub u8); - impl Inc { - #[doc = "Increment mode disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Increment mode enabled"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Size(pub u8); - impl Size { - #[doc = "8-bit size"] - pub const BITS8: Self = Self(0); - #[doc = "16-bit size"] - pub const BITS16: Self = Self(0x01); - #[doc = "32-bit size"] - pub const BITS32: Self = Self(0x02); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Memmem(pub u8); - impl Memmem { - #[doc = "Memory to memory mode disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Memory to memory mode enabled"] - pub const ENABLED: Self = Self(0x01); - } - } -} -pub mod gpio_v1 { - use crate::generic::*; - #[doc = "General purpose I/O"] - #[derive(Copy, Clone)] - pub struct Gpio(pub *mut u8); - unsafe impl Send for Gpio {} - unsafe impl Sync for Gpio {} - impl Gpio { - #[doc = "Port configuration register low (GPIOn_CRL)"] - pub fn cr(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) } - } - #[doc = "Port input data register (GPIOn_IDR)"] - pub fn idr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "Port output data register (GPIOn_ODR)"] - pub fn odr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "Port bit set/reset register (GPIOn_BSRR)"] - pub fn bsrr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "Port bit reset register (GPIOn_BRR)"] - pub fn brr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "Port configuration lock register"] - pub fn lckr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "Port input data register (GPIOn_IDR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idr(pub u32); - impl Idr { - #[doc = "Port input data"] - pub fn idr(&self, n: usize) -> super::vals::Idr { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Idr(val as u8) - } - #[doc = "Port input data"] - pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Idr { - fn default() -> Idr { - Idr(0) - } - } - #[doc = "Port bit reset register (GPIOn_BRR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Brr(pub u32); - impl Brr { - #[doc = "Reset bit"] - pub fn br(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Reset bit"] - pub fn set_br(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Brr { - fn default() -> Brr { - Brr(0) - } - } - #[doc = "Port output data register (GPIOn_ODR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Odr(pub u32); - impl Odr { - #[doc = "Port output data"] - pub fn odr(&self, n: usize) -> super::vals::Odr { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Odr(val as u8) - } - #[doc = "Port output data"] - pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Odr { - fn default() -> Odr { - Odr(0) - } - } - #[doc = "Port configuration register (GPIOn_CRx)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr(pub u32); - impl Cr { - #[doc = "Port n mode bits"] - pub fn mode(&self, n: usize) -> super::vals::Mode { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Mode(val as u8) - } - #[doc = "Port n mode bits"] - pub fn set_mode(&mut self, n: usize, val: super::vals::Mode) { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - #[doc = "Port n configuration bits"] - pub fn cnf(&self, n: usize) -> super::vals::Cnf { - assert!(n < 8usize); - let offs = 2usize + n * 4usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Cnf(val as u8) - } - #[doc = "Port n configuration bits"] - pub fn set_cnf(&mut self, n: usize, val: super::vals::Cnf) { - assert!(n < 8usize); - let offs = 2usize + n * 4usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - } - impl Default for Cr { - fn default() -> Cr { - Cr(0) - } - } - #[doc = "Port bit set/reset register (GPIOn_BSRR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Bsrr(pub u32); - impl Bsrr { - #[doc = "Set bit"] - pub fn bs(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Set bit"] - pub fn set_bs(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Reset bit"] - pub fn br(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 16usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Reset bit"] - pub fn set_br(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 16usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Bsrr { - fn default() -> Bsrr { - Bsrr(0) - } - } - #[doc = "Port configuration lock register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Lckr(pub u32); - impl Lckr { - #[doc = "Port A Lock bit"] - pub fn lck(&self, n: usize) -> super::vals::Lck { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Lck(val as u8) - } - #[doc = "Port A Lock bit"] - pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - #[doc = "Lock key"] - pub const fn lckk(&self) -> super::vals::Lckk { - let val = (self.0 >> 16usize) & 0x01; - super::vals::Lckk(val as u8) - } - #[doc = "Lock key"] - pub fn set_lckk(&mut self, val: super::vals::Lckk) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); - } - } - impl Default for Lckr { - fn default() -> Lckr { - Lckr(0) - } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cnf(pub u8); - impl Cnf { - #[doc = "Analog mode / Push-Pull mode"] - pub const PUSHPULL: Self = Self(0); - #[doc = "Floating input (reset state) / Open Drain-Mode"] - pub const OPENDRAIN: Self = Self(0x01); - #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"] - pub const ALTPUSHPULL: Self = Self(0x02); - #[doc = "Alternate Function Open-Drain Mode"] - pub const ALTOPENDRAIN: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lck(pub u8); - impl Lck { - #[doc = "Port configuration not locked"] - pub const UNLOCKED: Self = Self(0); - #[doc = "Port configuration locked"] - pub const LOCKED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Odr(pub u8); - impl Odr { - #[doc = "Set output to logic low"] - pub const LOW: Self = Self(0); - #[doc = "Set output to logic high"] - pub const HIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mode(pub u8); - impl Mode { - #[doc = "Input mode (reset state)"] - pub const INPUT: Self = Self(0); - #[doc = "Output mode 10 MHz"] - pub const OUTPUT: Self = Self(0x01); - #[doc = "Output mode 2 MHz"] - pub const OUTPUT2: Self = Self(0x02); - #[doc = "Output mode 50 MHz"] - pub const OUTPUT50: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Idr(pub u8); - impl Idr { - #[doc = "Input is logic low"] - pub const LOW: Self = Self(0); - #[doc = "Input is logic high"] - pub const HIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Brw(pub u8); - impl Brw { - #[doc = "No action on the corresponding ODx bit"] - pub const NOACTION: Self = Self(0); - #[doc = "Reset the ODx bit"] - pub const RESET: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lckk(pub u8); - impl Lckk { - #[doc = "Port configuration lock key not active"] - pub const NOTACTIVE: Self = Self(0); - #[doc = "Port configuration lock key active"] - pub const ACTIVE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bsw(pub u8); - impl Bsw { - #[doc = "No action on the corresponding ODx bit"] - pub const NOACTION: Self = Self(0); - #[doc = "Sets the corresponding ODRx bit"] - pub const SET: Self = Self(0x01); - } - } -} -pub mod syscfg_l4 { - use crate::generic::*; - #[doc = "System configuration controller"] - #[derive(Copy, Clone)] - pub struct Syscfg(pub *mut u8); - unsafe impl Send for Syscfg {} - unsafe impl Sync for Syscfg {} - impl Syscfg { - #[doc = "memory remap register"] - pub fn memrmp(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "configuration register 1"] - pub fn cfgr1(self) -> Reg { + pub fn pmcr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(4usize)) } } #[doc = "external interrupt configuration register 1"] @@ -8678,58 +8254,791 @@ pub mod syscfg_l4 { assert!(n < 4usize); unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } } - #[doc = "SCSR"] - pub fn scsr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } - } - #[doc = "CFGR2"] - pub fn cfgr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(28usize)) } - } - #[doc = "SWPR"] - pub fn swpr(self) -> Reg { + #[doc = "compensation cell control/status register"] + pub fn cccsr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(32usize)) } } - #[doc = "SKR"] - pub fn skr(self) -> Reg { + #[doc = "SYSCFG compensation cell value register"] + pub fn ccvr(self) -> Reg { unsafe { Reg::from_ptr(self.0.add(36usize)) } } + #[doc = "SYSCFG compensation cell code register"] + pub fn cccr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "SYSCFG power control register"] + pub fn pwrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "SYSCFG package register"] + pub fn pkgr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(292usize)) } + } + #[doc = "SYSCFG user register 0"] + pub fn ur0(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(768usize)) } + } + #[doc = "SYSCFG user register 2"] + pub fn ur2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(776usize)) } + } + #[doc = "SYSCFG user register 3"] + pub fn ur3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(780usize)) } + } + #[doc = "SYSCFG user register 4"] + pub fn ur4(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(784usize)) } + } + #[doc = "SYSCFG user register 5"] + pub fn ur5(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(788usize)) } + } + #[doc = "SYSCFG user register 6"] + pub fn ur6(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(792usize)) } + } + #[doc = "SYSCFG user register 7"] + pub fn ur7(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(796usize)) } + } + #[doc = "SYSCFG user register 8"] + pub fn ur8(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(800usize)) } + } + #[doc = "SYSCFG user register 9"] + pub fn ur9(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(804usize)) } + } + #[doc = "SYSCFG user register 10"] + pub fn ur10(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(808usize)) } + } + #[doc = "SYSCFG user register 11"] + pub fn ur11(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(812usize)) } + } + #[doc = "SYSCFG user register 12"] + pub fn ur12(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(816usize)) } + } + #[doc = "SYSCFG user register 13"] + pub fn ur13(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(820usize)) } + } + #[doc = "SYSCFG user register 14"] + pub fn ur14(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(824usize)) } + } + #[doc = "SYSCFG user register 15"] + pub fn ur15(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(828usize)) } + } + #[doc = "SYSCFG user register 16"] + pub fn ur16(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(832usize)) } + } + #[doc = "SYSCFG user register 17"] + pub fn ur17(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(836usize)) } + } } pub mod regs { use crate::generic::*; - #[doc = "SKR"] + #[doc = "SYSCFG user register 16"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Skr(pub u32); - impl Skr { - #[doc = "SRAM2 write protection key for software erase"] - pub const fn key(&self) -> u8 { + pub struct Ur16(pub u32); + impl Ur16 { + #[doc = "Freeze independent watchdog in Stop mode"] + pub const fn fziwdgstp(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Freeze independent watchdog in Stop mode"] + pub fn set_fziwdgstp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Private key programmed"] + pub const fn pkp(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Private key programmed"] + pub fn set_pkp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur16 { + fn default() -> Ur16 { + Ur16(0) + } + } + #[doc = "SYSCFG user register 0"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur0(pub u32); + impl Ur0 { + #[doc = "Bank Swap"] + pub const fn bks(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Bank Swap"] + pub fn set_bks(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Readout protection"] + pub const fn rdp(&self) -> u8 { + let val = (self.0 >> 16usize) & 0xff; + val as u8 + } + #[doc = "Readout protection"] + pub fn set_rdp(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); + } + } + impl Default for Ur0 { + fn default() -> Ur0 { + Ur0(0) + } + } + #[doc = "SYSCFG compensation cell value register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccvr(pub u32); + impl Ccvr { + #[doc = "NMOS compensation value"] + pub const fn ncv(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "NMOS compensation value"] + pub fn set_ncv(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "PMOS compensation value"] + pub const fn pcv(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "PMOS compensation value"] + pub fn set_pcv(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + } + impl Default for Ccvr { + fn default() -> Ccvr { + Ccvr(0) + } + } + #[doc = "SYSCFG user register 7"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur7(pub u32); + impl Ur7 { + #[doc = "Secured area start address for bank 1"] + pub const fn sa_beg_1(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area start address for bank 1"] + pub fn set_sa_beg_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Secured area end address for bank 1"] + pub const fn sa_end_1(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area end address for bank 1"] + pub fn set_sa_end_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur7 { + fn default() -> Ur7 { + Ur7(0) + } + } + #[doc = "SYSCFG user register 13"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur13(pub u32); + impl Ur13 { + #[doc = "Secured DTCM RAM Size"] + pub const fn sdrs(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x03; + val as u8 + } + #[doc = "Secured DTCM RAM Size"] + pub fn set_sdrs(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); + } + #[doc = "D1 Standby reset"] + pub const fn d1sbrst(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "D1 Standby reset"] + pub fn set_d1sbrst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur13 { + fn default() -> Ur13 { + Ur13(0) + } + } + #[doc = "SYSCFG user register 4"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur4(pub u32); + impl Ur4 { + #[doc = "Mass Erase Protected Area Disabled for bank 1"] + pub const fn mepad_1(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Mass Erase Protected Area Disabled for bank 1"] + pub fn set_mepad_1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur4 { + fn default() -> Ur4 { + Ur4(0) + } + } + #[doc = "SYSCFG user register 10"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur10(pub u32); + impl Ur10 { + #[doc = "Protected area end address for bank 2"] + pub const fn pa_end_2(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area end address for bank 2"] + pub fn set_pa_end_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Secured area start address for bank 2"] + pub const fn sa_beg_2(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area start address for bank 2"] + pub fn set_sa_beg_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur10 { + fn default() -> Ur10 { + Ur10(0) + } + } + #[doc = "SYSCFG user register 9"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur9(pub u32); + impl Ur9 { + #[doc = "Write protection for flash bank 2"] + pub const fn wrpn_2(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "SRAM2 write protection key for software erase"] - pub fn set_key(&mut self, val: u8) { + #[doc = "Write protection for flash bank 2"] + pub fn set_wrpn_2(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); } - } - impl Default for Skr { - fn default() -> Skr { - Skr(0) + #[doc = "Protected area start address for bank 2"] + pub const fn pa_beg_2(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area start address for bank 2"] + pub fn set_pa_beg_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); } } - #[doc = "external interrupt configuration register 4"] + impl Default for Ur9 { + fn default() -> Ur9 { + Ur9(0) + } + } + #[doc = "SYSCFG user register 12"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur12(pub u32); + impl Ur12 { + #[doc = "Secure mode"] + pub const fn secure(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Secure mode"] + pub fn set_secure(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur12 { + fn default() -> Ur12 { + Ur12(0) + } + } + #[doc = "peripheral mode configuration register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pmcr(pub u32); + impl Pmcr { + #[doc = "I2C1 Fm+"] + pub const fn i2c1fmp(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "I2C1 Fm+"] + pub fn set_i2c1fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "I2C2 Fm+"] + pub const fn i2c2fmp(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "I2C2 Fm+"] + pub fn set_i2c2fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "I2C3 Fm+"] + pub const fn i2c3fmp(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "I2C3 Fm+"] + pub fn set_i2c3fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "I2C4 Fm+"] + pub const fn i2c4fmp(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "I2C4 Fm+"] + pub fn set_i2c4fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "PB(6) Fm+"] + pub const fn pb6fmp(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "PB(6) Fm+"] + pub fn set_pb6fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "PB(7) Fast Mode Plus"] + pub const fn pb7fmp(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "PB(7) Fast Mode Plus"] + pub fn set_pb7fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "PB(8) Fast Mode Plus"] + pub const fn pb8fmp(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "PB(8) Fast Mode Plus"] + pub fn set_pb8fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "PB(9) Fm+"] + pub const fn pb9fmp(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "PB(9) Fm+"] + pub fn set_pb9fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Booster Enable"] + pub const fn booste(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Booster Enable"] + pub fn set_booste(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Analog switch supply voltage selection"] + pub const fn boostvddsel(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Analog switch supply voltage selection"] + pub fn set_boostvddsel(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Ethernet PHY Interface Selection"] + pub const fn epis(&self) -> u8 { + let val = (self.0 >> 21usize) & 0x07; + val as u8 + } + #[doc = "Ethernet PHY Interface Selection"] + pub fn set_epis(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 21usize)) | (((val as u32) & 0x07) << 21usize); + } + #[doc = "PA0 Switch Open"] + pub const fn pa0so(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "PA0 Switch Open"] + pub fn set_pa0so(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "PA1 Switch Open"] + pub const fn pa1so(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "PA1 Switch Open"] + pub fn set_pa1so(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "PC2 Switch Open"] + pub const fn pc2so(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "PC2 Switch Open"] + pub fn set_pc2so(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "PC3 Switch Open"] + pub const fn pc3so(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "PC3 Switch Open"] + pub fn set_pc3so(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + } + impl Default for Pmcr { + fn default() -> Pmcr { + Pmcr(0) + } + } + #[doc = "SYSCFG user register 6"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur6(pub u32); + impl Ur6 { + #[doc = "Protected area start address for bank 1"] + pub const fn pa_beg_1(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area start address for bank 1"] + pub fn set_pa_beg_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Protected area end address for bank 1"] + pub const fn pa_end_1(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area end address for bank 1"] + pub fn set_pa_end_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur6 { + fn default() -> Ur6 { + Ur6(0) + } + } + #[doc = "compensation cell control/status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cccsr(pub u32); + impl Cccsr { + #[doc = "enable"] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "enable"] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Code selection"] + pub const fn cs(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Code selection"] + pub fn set_cs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Compensation cell ready flag"] + pub const fn ready(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Compensation cell ready flag"] + pub fn set_ready(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "High-speed at low-voltage"] + pub const fn hslv(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "High-speed at low-voltage"] + pub fn set_hslv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Cccsr { + fn default() -> Cccsr { + Cccsr(0) + } + } + #[doc = "SYSCFG user register 5"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur5(pub u32); + impl Ur5 { + #[doc = "Mass erase secured area disabled for bank 1"] + pub const fn mesad_1(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Mass erase secured area disabled for bank 1"] + pub fn set_mesad_1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Write protection for flash bank 1"] + pub const fn wrpn_1(&self) -> u8 { + let val = (self.0 >> 16usize) & 0xff; + val as u8 + } + #[doc = "Write protection for flash bank 1"] + pub fn set_wrpn_1(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); + } + } + impl Default for Ur5 { + fn default() -> Ur5 { + Ur5(0) + } + } + #[doc = "SYSCFG user register 14"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur14(pub u32); + impl Ur14 { + #[doc = "D1 Stop Reset"] + pub const fn d1stprst(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "D1 Stop Reset"] + pub fn set_d1stprst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for Ur14 { + fn default() -> Ur14 { + Ur14(0) + } + } + #[doc = "SYSCFG power control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pwrcr(pub u32); + impl Pwrcr { + #[doc = "Overdrive enable"] + pub const fn oden(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Overdrive enable"] + pub fn set_oden(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + } + impl Default for Pwrcr { + fn default() -> Pwrcr { + Pwrcr(0) + } + } + #[doc = "SYSCFG package register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pkgr(pub u32); + impl Pkgr { + #[doc = "Package"] + pub const fn pkg(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Package"] + pub fn set_pkg(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + } + impl Default for Pkgr { + fn default() -> Pkgr { + Pkgr(0) + } + } + #[doc = "SYSCFG user register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur3(pub u32); + impl Ur3 { + #[doc = "Boot Address 1"] + pub const fn boot_add1(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "Boot Address 1"] + pub fn set_boot_add1(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + } + } + impl Default for Ur3 { + fn default() -> Ur3 { + Ur3(0) + } + } + #[doc = "SYSCFG user register 11"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur11(pub u32); + impl Ur11 { + #[doc = "Secured area end address for bank 2"] + pub const fn sa_end_2(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area end address for bank 2"] + pub fn set_sa_end_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Independent Watchdog 1 mode"] + pub const fn iwdg1m(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Independent Watchdog 1 mode"] + pub fn set_iwdg1m(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur11 { + fn default() -> Ur11 { + Ur11(0) + } + } + #[doc = "SYSCFG compensation cell code register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cccr(pub u32); + impl Cccr { + #[doc = "NMOS compensation code"] + pub const fn ncc(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "NMOS compensation code"] + pub fn set_ncc(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "PMOS compensation code"] + pub const fn pcc(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "PMOS compensation code"] + pub fn set_pcc(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + } + impl Default for Cccr { + fn default() -> Cccr { + Cccr(0) + } + } + #[doc = "SYSCFG user register 15"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur15(pub u32); + impl Ur15 { + #[doc = "Freeze independent watchdog in Standby mode"] + pub const fn fziwdgstb(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Freeze independent watchdog in Standby mode"] + pub fn set_fziwdgstb(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur15 { + fn default() -> Ur15 { + Ur15(0) + } + } + #[doc = "SYSCFG user register 8"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur8(pub u32); + impl Ur8 { + #[doc = "Mass erase protected area disabled for bank 2"] + pub const fn mepad_2(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Mass erase protected area disabled for bank 2"] + pub fn set_mepad_2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Mass erase secured area disabled for bank 2"] + pub const fn mesad_2(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Mass erase secured area disabled for bank 2"] + pub fn set_mesad_2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur8 { + fn default() -> Ur8 { + Ur8(0) + } + } + #[doc = "external interrupt configuration register 2"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Exticr(pub u32); impl Exticr { - #[doc = "EXTI12 configuration bits"] + #[doc = "EXTI x configuration (x = 4 to 7)"] pub fn exti(&self, n: usize) -> u8 { assert!(n < 4usize); let offs = 0usize + n * 4usize; let val = (self.0 >> offs) & 0x0f; val as u8 } - #[doc = "EXTI12 configuration bits"] + #[doc = "EXTI x configuration (x = 4 to 7)"] pub fn set_exti(&mut self, n: usize, val: u8) { assert!(n < 4usize); let offs = 0usize + n * 4usize; @@ -8741,362 +9050,53 @@ pub mod syscfg_l4 { Exticr(0) } } - #[doc = "SCSR"] + #[doc = "SYSCFG user register 2"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Scsr(pub u32); - impl Scsr { - #[doc = "SRAM2 Erase"] - pub const fn sram2er(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "SRAM2 Erase"] - pub fn set_sram2er(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "SRAM2 busy by erase operation"] - pub const fn sram2bsy(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "SRAM2 busy by erase operation"] - pub fn set_sram2bsy(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - } - impl Default for Scsr { - fn default() -> Scsr { - Scsr(0) - } - } - #[doc = "CFGR2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cfgr2(pub u32); - impl Cfgr2 { - #[doc = "Cortex LOCKUP (Hardfault) output enable bit"] - pub const fn cll(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Cortex LOCKUP (Hardfault) output enable bit"] - pub fn set_cll(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "SRAM2 parity lock bit"] - pub const fn spl(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "SRAM2 parity lock bit"] - pub fn set_spl(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "PVD lock enable bit"] - pub const fn pvdl(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "PVD lock enable bit"] - pub fn set_pvdl(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "ECC Lock"] - pub const fn eccl(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "ECC Lock"] - pub fn set_eccl(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "SRAM2 parity error flag"] - pub const fn spf(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "SRAM2 parity error flag"] - pub fn set_spf(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for Cfgr2 { - fn default() -> Cfgr2 { - Cfgr2(0) - } - } - #[doc = "SWPR"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Swpr(pub u32); - impl Swpr { - #[doc = "SRAWM2 write protection."] - pub fn pwp(&self, n: usize) -> bool { - assert!(n < 32usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "SRAWM2 write protection."] - pub fn set_pwp(&mut self, n: usize, val: bool) { - assert!(n < 32usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Swpr { - fn default() -> Swpr { - Swpr(0) - } - } - #[doc = "configuration register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cfgr1(pub u32); - impl Cfgr1 { - #[doc = "Firewall disable"] - pub const fn fwdis(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Firewall disable"] - pub fn set_fwdis(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "I/O analog switch voltage booster enable"] - pub const fn boosten(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "I/O analog switch voltage booster enable"] - pub fn set_boosten(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"] - pub const fn i2c_pb6_fmp(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"] - pub fn set_i2c_pb6_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"] - pub const fn i2c_pb7_fmp(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"] - pub fn set_i2c_pb7_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"] - pub const fn i2c_pb8_fmp(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"] - pub fn set_i2c_pb8_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"] - pub const fn i2c_pb9_fmp(&self) -> bool { - let val = (self.0 >> 19usize) & 0x01; - val != 0 - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"] - pub fn set_i2c_pb9_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); - } - #[doc = "I2C1 Fast-mode Plus driving capability activation"] - pub const fn i2c1_fmp(&self) -> bool { - let val = (self.0 >> 20usize) & 0x01; - val != 0 - } - #[doc = "I2C1 Fast-mode Plus driving capability activation"] - pub fn set_i2c1_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); - } - #[doc = "I2C2 Fast-mode Plus driving capability activation"] - pub const fn i2c2_fmp(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[doc = "I2C2 Fast-mode Plus driving capability activation"] - pub fn set_i2c2_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[doc = "I2C3 Fast-mode Plus driving capability activation"] - pub const fn i2c3_fmp(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[doc = "I2C3 Fast-mode Plus driving capability activation"] - pub fn set_i2c3_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[doc = "Floating Point Unit interrupts enable bits"] - pub const fn fpu_ie(&self) -> u8 { - let val = (self.0 >> 26usize) & 0x3f; + pub struct Ur2(pub u32); + impl Ur2 { + #[doc = "BOR_LVL Brownout Reset Threshold Level"] + pub const fn borh(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x03; val as u8 } - #[doc = "Floating Point Unit interrupts enable bits"] - pub fn set_fpu_ie(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 26usize)) | (((val as u32) & 0x3f) << 26usize); + #[doc = "BOR_LVL Brownout Reset Threshold Level"] + pub fn set_borh(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); + } + #[doc = "Boot Address 0"] + pub const fn boot_add0(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "Boot Address 0"] + pub fn set_boot_add0(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); } } - impl Default for Cfgr1 { - fn default() -> Cfgr1 { - Cfgr1(0) + impl Default for Ur2 { + fn default() -> Ur2 { + Ur2(0) } } - #[doc = "memory remap register"] + #[doc = "SYSCFG user register 17"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Memrmp(pub u32); - impl Memrmp { - #[doc = "Memory mapping selection"] - pub const fn mem_mode(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Memory mapping selection"] - pub fn set_mem_mode(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "QUADSPI memory mapping swap"] - pub const fn qfs(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub struct Ur17(pub u32); + impl Ur17 { + #[doc = "I/O high speed / low voltage"] + pub const fn io_hslv(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "QUADSPI memory mapping swap"] - pub fn set_qfs(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Flash Bank mode selection"] - pub const fn fb_mode(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Flash Bank mode selection"] - pub fn set_fb_mode(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + #[doc = "I/O high speed / low voltage"] + pub fn set_io_hslv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } } - impl Default for Memrmp { - fn default() -> Memrmp { - Memrmp(0) - } - } - } -} -pub mod rng_v1 { - use crate::generic::*; - #[doc = "Random number generator"] - #[derive(Copy, Clone)] - pub struct Rng(pub *mut u8); - unsafe impl Send for Rng {} - unsafe impl Sync for Rng {} - impl Rng { - #[doc = "control register"] - pub fn cr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "data register"] - pub fn dr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Sr(pub u32); - impl Sr { - #[doc = "Data ready"] - pub const fn drdy(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Data ready"] - pub fn set_drdy(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Clock error current status"] - pub const fn cecs(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Clock error current status"] - pub fn set_cecs(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Seed error current status"] - pub const fn secs(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Seed error current status"] - pub fn set_secs(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Clock error interrupt status"] - pub const fn ceis(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Clock error interrupt status"] - pub fn set_ceis(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Seed error interrupt status"] - pub const fn seis(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Seed error interrupt status"] - pub fn set_seis(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - } - impl Default for Sr { - fn default() -> Sr { - Sr(0) - } - } - #[doc = "control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr(pub u32); - impl Cr { - #[doc = "Random number generator enable"] - pub const fn rngen(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Random number generator enable"] - pub fn set_rngen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Interrupt enable"] - pub const fn ie(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Interrupt enable"] - pub fn set_ie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - } - impl Default for Cr { - fn default() -> Cr { - Cr(0) + impl Default for Ur17 { + fn default() -> Ur17 { + Ur17(0) } } } diff --git a/embassy-stm32/src/pac/stm32f401cb.rs b/embassy-stm32/src/pac/stm32f401cb.rs index fe69202d..13e60e2e 100644 --- a/embassy-stm32/src/pac/stm32f401cb.rs +++ b/embassy-stm32/src/pac/stm32f401cb.rs @@ -126,6 +126,32 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -158,6 +184,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -172,7 +199,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f401cc.rs b/embassy-stm32/src/pac/stm32f401cc.rs index fe69202d..13e60e2e 100644 --- a/embassy-stm32/src/pac/stm32f401cc.rs +++ b/embassy-stm32/src/pac/stm32f401cc.rs @@ -126,6 +126,32 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -158,6 +184,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -172,7 +199,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f401cd.rs b/embassy-stm32/src/pac/stm32f401cd.rs index fe69202d..13e60e2e 100644 --- a/embassy-stm32/src/pac/stm32f401cd.rs +++ b/embassy-stm32/src/pac/stm32f401cd.rs @@ -126,6 +126,32 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -158,6 +184,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -172,7 +199,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f401ce.rs b/embassy-stm32/src/pac/stm32f401ce.rs index fe69202d..13e60e2e 100644 --- a/embassy-stm32/src/pac/stm32f401ce.rs +++ b/embassy-stm32/src/pac/stm32f401ce.rs @@ -126,6 +126,32 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -158,6 +184,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -172,7 +199,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f401rb.rs b/embassy-stm32/src/pac/stm32f401rb.rs index fe69202d..13e60e2e 100644 --- a/embassy-stm32/src/pac/stm32f401rb.rs +++ b/embassy-stm32/src/pac/stm32f401rb.rs @@ -126,6 +126,32 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -158,6 +184,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -172,7 +199,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f401rc.rs b/embassy-stm32/src/pac/stm32f401rc.rs index fe69202d..13e60e2e 100644 --- a/embassy-stm32/src/pac/stm32f401rc.rs +++ b/embassy-stm32/src/pac/stm32f401rc.rs @@ -126,6 +126,32 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -158,6 +184,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -172,7 +199,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f401rd.rs b/embassy-stm32/src/pac/stm32f401rd.rs index fe69202d..13e60e2e 100644 --- a/embassy-stm32/src/pac/stm32f401rd.rs +++ b/embassy-stm32/src/pac/stm32f401rd.rs @@ -126,6 +126,32 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -158,6 +184,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -172,7 +199,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f401re.rs b/embassy-stm32/src/pac/stm32f401re.rs index fe69202d..13e60e2e 100644 --- a/embassy-stm32/src/pac/stm32f401re.rs +++ b/embassy-stm32/src/pac/stm32f401re.rs @@ -126,6 +126,32 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -158,6 +184,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -172,7 +199,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f401vb.rs b/embassy-stm32/src/pac/stm32f401vb.rs index fe69202d..91263ba4 100644 --- a/embassy-stm32/src/pac/stm32f401vb.rs +++ b/embassy-stm32/src/pac/stm32f401vb.rs @@ -126,6 +126,40 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -158,6 +192,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -172,7 +207,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f401vc.rs b/embassy-stm32/src/pac/stm32f401vc.rs index fe69202d..91263ba4 100644 --- a/embassy-stm32/src/pac/stm32f401vc.rs +++ b/embassy-stm32/src/pac/stm32f401vc.rs @@ -126,6 +126,40 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -158,6 +192,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -172,7 +207,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f401vd.rs b/embassy-stm32/src/pac/stm32f401vd.rs index fe69202d..91263ba4 100644 --- a/embassy-stm32/src/pac/stm32f401vd.rs +++ b/embassy-stm32/src/pac/stm32f401vd.rs @@ -126,6 +126,40 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -158,6 +192,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -172,7 +207,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f401ve.rs b/embassy-stm32/src/pac/stm32f401ve.rs index fe69202d..91263ba4 100644 --- a/embassy-stm32/src/pac/stm32f401ve.rs +++ b/embassy-stm32/src/pac/stm32f401ve.rs @@ -126,6 +126,40 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -158,6 +192,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -172,7 +207,7 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f405oe.rs b/embassy-stm32/src/pac/stm32f405oe.rs index ef281f87..f8ee073f 100644 --- a/embassy-stm32/src/pac/stm32f405oe.rs +++ b/embassy-stm32/src/pac/stm32f405oe.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f405og.rs b/embassy-stm32/src/pac/stm32f405og.rs index ef281f87..f8ee073f 100644 --- a/embassy-stm32/src/pac/stm32f405og.rs +++ b/embassy-stm32/src/pac/stm32f405og.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f405rg.rs b/embassy-stm32/src/pac/stm32f405rg.rs index ef281f87..f8ee073f 100644 --- a/embassy-stm32/src/pac/stm32f405rg.rs +++ b/embassy-stm32/src/pac/stm32f405rg.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f405vg.rs b/embassy-stm32/src/pac/stm32f405vg.rs index ef281f87..f8ee073f 100644 --- a/embassy-stm32/src/pac/stm32f405vg.rs +++ b/embassy-stm32/src/pac/stm32f405vg.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f405zg.rs b/embassy-stm32/src/pac/stm32f405zg.rs index ef281f87..f8ee073f 100644 --- a/embassy-stm32/src/pac/stm32f405zg.rs +++ b/embassy-stm32/src/pac/stm32f405zg.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f407ie.rs b/embassy-stm32/src/pac/stm32f407ie.rs index e331efc8..7c839139 100644 --- a/embassy-stm32/src/pac/stm32f407ie.rs +++ b/embassy-stm32/src/pac/stm32f407ie.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f407ig.rs b/embassy-stm32/src/pac/stm32f407ig.rs index e331efc8..7c839139 100644 --- a/embassy-stm32/src/pac/stm32f407ig.rs +++ b/embassy-stm32/src/pac/stm32f407ig.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f407ve.rs b/embassy-stm32/src/pac/stm32f407ve.rs index e331efc8..7c839139 100644 --- a/embassy-stm32/src/pac/stm32f407ve.rs +++ b/embassy-stm32/src/pac/stm32f407ve.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f407vg.rs b/embassy-stm32/src/pac/stm32f407vg.rs index e331efc8..7c839139 100644 --- a/embassy-stm32/src/pac/stm32f407vg.rs +++ b/embassy-stm32/src/pac/stm32f407vg.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f407ze.rs b/embassy-stm32/src/pac/stm32f407ze.rs index e331efc8..7c839139 100644 --- a/embassy-stm32/src/pac/stm32f407ze.rs +++ b/embassy-stm32/src/pac/stm32f407ze.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f407zg.rs b/embassy-stm32/src/pac/stm32f407zg.rs index e331efc8..7c839139 100644 --- a/embassy-stm32/src/pac/stm32f407zg.rs +++ b/embassy-stm32/src/pac/stm32f407zg.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f410c8.rs b/embassy-stm32/src/pac/stm32f410c8.rs index 0ade08ef..938c0c05 100644 --- a/embassy-stm32/src/pac/stm32f410c8.rs +++ b/embassy-stm32/src/pac/stm32f410c8.rs @@ -93,7 +93,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f410cb.rs b/embassy-stm32/src/pac/stm32f410cb.rs index 0ade08ef..938c0c05 100644 --- a/embassy-stm32/src/pac/stm32f410cb.rs +++ b/embassy-stm32/src/pac/stm32f410cb.rs @@ -93,7 +93,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f410r8.rs b/embassy-stm32/src/pac/stm32f410r8.rs index 0ade08ef..938c0c05 100644 --- a/embassy-stm32/src/pac/stm32f410r8.rs +++ b/embassy-stm32/src/pac/stm32f410r8.rs @@ -93,7 +93,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f410rb.rs b/embassy-stm32/src/pac/stm32f410rb.rs index 0ade08ef..938c0c05 100644 --- a/embassy-stm32/src/pac/stm32f410rb.rs +++ b/embassy-stm32/src/pac/stm32f410rb.rs @@ -93,7 +93,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f410t8.rs b/embassy-stm32/src/pac/stm32f410t8.rs index 01c93845..74d238a1 100644 --- a/embassy-stm32/src/pac/stm32f410t8.rs +++ b/embassy-stm32/src/pac/stm32f410t8.rs @@ -93,7 +93,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f410tb.rs b/embassy-stm32/src/pac/stm32f410tb.rs index 01c93845..74d238a1 100644 --- a/embassy-stm32/src/pac/stm32f410tb.rs +++ b/embassy-stm32/src/pac/stm32f410tb.rs @@ -93,7 +93,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f411cc.rs b/embassy-stm32/src/pac/stm32f411cc.rs index 1e54e97c..325aee85 100644 --- a/embassy-stm32/src/pac/stm32f411cc.rs +++ b/embassy-stm32/src/pac/stm32f411cc.rs @@ -126,6 +126,57 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -160,6 +211,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -174,7 +226,8 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f411ce.rs b/embassy-stm32/src/pac/stm32f411ce.rs index 1e54e97c..325aee85 100644 --- a/embassy-stm32/src/pac/stm32f411ce.rs +++ b/embassy-stm32/src/pac/stm32f411ce.rs @@ -126,6 +126,57 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -160,6 +211,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -174,7 +226,8 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f411rc.rs b/embassy-stm32/src/pac/stm32f411rc.rs index 1e54e97c..325aee85 100644 --- a/embassy-stm32/src/pac/stm32f411rc.rs +++ b/embassy-stm32/src/pac/stm32f411rc.rs @@ -126,6 +126,57 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -160,6 +211,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -174,7 +226,8 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f411re.rs b/embassy-stm32/src/pac/stm32f411re.rs index 1e54e97c..325aee85 100644 --- a/embassy-stm32/src/pac/stm32f411re.rs +++ b/embassy-stm32/src/pac/stm32f411re.rs @@ -126,6 +126,57 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -160,6 +211,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -174,7 +226,8 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f411vc.rs b/embassy-stm32/src/pac/stm32f411vc.rs index 1e54e97c..325aee85 100644 --- a/embassy-stm32/src/pac/stm32f411vc.rs +++ b/embassy-stm32/src/pac/stm32f411vc.rs @@ -126,6 +126,57 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -160,6 +211,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -174,7 +226,8 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f411ve.rs b/embassy-stm32/src/pac/stm32f411ve.rs index 1e54e97c..325aee85 100644 --- a/embassy-stm32/src/pac/stm32f411ve.rs +++ b/embassy-stm32/src/pac/stm32f411ve.rs @@ -126,6 +126,57 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -160,6 +211,7 @@ impl_usart_pin!(USART6, CkPin, PC8, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -174,7 +226,8 @@ peripherals!( PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART6 + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f412ce.rs b/embassy-stm32/src/pac/stm32f412ce.rs index 9f734f6e..ae976e69 100644 --- a/embassy-stm32/src/pac/stm32f412ce.rs +++ b/embassy-stm32/src/pac/stm32f412ce.rs @@ -93,7 +93,44 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -135,6 +172,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -147,8 +185,8 @@ peripherals!( PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, - PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, - USART6 + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, + SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f412cg.rs b/embassy-stm32/src/pac/stm32f412cg.rs index 9f734f6e..ae976e69 100644 --- a/embassy-stm32/src/pac/stm32f412cg.rs +++ b/embassy-stm32/src/pac/stm32f412cg.rs @@ -93,7 +93,44 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -135,6 +172,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -147,8 +185,8 @@ peripherals!( PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, - PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, - USART6 + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, + SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f412re.rs b/embassy-stm32/src/pac/stm32f412re.rs index faee6650..819f0c06 100644 --- a/embassy-stm32/src/pac/stm32f412re.rs +++ b/embassy-stm32/src/pac/stm32f412re.rs @@ -110,7 +110,46 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -162,6 +201,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -175,7 +215,8 @@ peripherals!( PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, - PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, + USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f412rg.rs b/embassy-stm32/src/pac/stm32f412rg.rs index faee6650..819f0c06 100644 --- a/embassy-stm32/src/pac/stm32f412rg.rs +++ b/embassy-stm32/src/pac/stm32f412rg.rs @@ -110,7 +110,46 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -162,6 +201,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -175,7 +215,8 @@ peripherals!( PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, - PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, + USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f412ve.rs b/embassy-stm32/src/pac/stm32f412ve.rs index 035b44f2..9e109b61 100644 --- a/embassy-stm32/src/pac/stm32f412ve.rs +++ b/embassy-stm32/src/pac/stm32f412ve.rs @@ -161,7 +161,58 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -220,6 +271,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -236,7 +288,8 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f412vg.rs b/embassy-stm32/src/pac/stm32f412vg.rs index 035b44f2..9e109b61 100644 --- a/embassy-stm32/src/pac/stm32f412vg.rs +++ b/embassy-stm32/src/pac/stm32f412vg.rs @@ -161,7 +161,58 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -220,6 +271,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -236,7 +288,8 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f412ze.rs b/embassy-stm32/src/pac/stm32f412ze.rs index 035b44f2..9e109b61 100644 --- a/embassy-stm32/src/pac/stm32f412ze.rs +++ b/embassy-stm32/src/pac/stm32f412ze.rs @@ -161,7 +161,58 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -220,6 +271,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -236,7 +288,8 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f412zg.rs b/embassy-stm32/src/pac/stm32f412zg.rs index 035b44f2..9e109b61 100644 --- a/embassy-stm32/src/pac/stm32f412zg.rs +++ b/embassy-stm32/src/pac/stm32f412zg.rs @@ -161,7 +161,58 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -220,6 +271,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -236,7 +288,8 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f413cg.rs b/embassy-stm32/src/pac/stm32f413cg.rs index b2b2c30d..f74b0f40 100644 --- a/embassy-stm32/src/pac/stm32f413cg.rs +++ b/embassy-stm32/src/pac/stm32f413cg.rs @@ -161,7 +161,61 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Mosi, PA10, 5); +impl_spi_pin!(SPI2, Miso, PA12, 5); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -204,6 +258,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -220,7 +275,7 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f413ch.rs b/embassy-stm32/src/pac/stm32f413ch.rs index b2b2c30d..f74b0f40 100644 --- a/embassy-stm32/src/pac/stm32f413ch.rs +++ b/embassy-stm32/src/pac/stm32f413ch.rs @@ -161,7 +161,61 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Mosi, PA10, 5); +impl_spi_pin!(SPI2, Miso, PA12, 5); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -204,6 +258,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -220,7 +275,7 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f413mg.rs b/embassy-stm32/src/pac/stm32f413mg.rs index e653d0cb..f2cd2b65 100644 --- a/embassy-stm32/src/pac/stm32f413mg.rs +++ b/embassy-stm32/src/pac/stm32f413mg.rs @@ -161,7 +161,61 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Mosi, PA10, 5); +impl_spi_pin!(SPI2, Miso, PA12, 5); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -220,6 +274,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -236,7 +291,8 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f413mh.rs b/embassy-stm32/src/pac/stm32f413mh.rs index e653d0cb..f2cd2b65 100644 --- a/embassy-stm32/src/pac/stm32f413mh.rs +++ b/embassy-stm32/src/pac/stm32f413mh.rs @@ -161,7 +161,61 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Mosi, PA10, 5); +impl_spi_pin!(SPI2, Miso, PA12, 5); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -220,6 +274,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -236,7 +291,8 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f413rg.rs b/embassy-stm32/src/pac/stm32f413rg.rs index e653d0cb..f2cd2b65 100644 --- a/embassy-stm32/src/pac/stm32f413rg.rs +++ b/embassy-stm32/src/pac/stm32f413rg.rs @@ -161,7 +161,61 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Mosi, PA10, 5); +impl_spi_pin!(SPI2, Miso, PA12, 5); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -220,6 +274,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -236,7 +291,8 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f413rh.rs b/embassy-stm32/src/pac/stm32f413rh.rs index e653d0cb..f2cd2b65 100644 --- a/embassy-stm32/src/pac/stm32f413rh.rs +++ b/embassy-stm32/src/pac/stm32f413rh.rs @@ -161,7 +161,61 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Mosi, PA10, 5); +impl_spi_pin!(SPI2, Miso, PA12, 5); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -220,6 +274,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -236,7 +291,8 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f413vg.rs b/embassy-stm32/src/pac/stm32f413vg.rs index e653d0cb..f2cd2b65 100644 --- a/embassy-stm32/src/pac/stm32f413vg.rs +++ b/embassy-stm32/src/pac/stm32f413vg.rs @@ -161,7 +161,61 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Mosi, PA10, 5); +impl_spi_pin!(SPI2, Miso, PA12, 5); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -220,6 +274,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -236,7 +291,8 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f413vh.rs b/embassy-stm32/src/pac/stm32f413vh.rs index e653d0cb..f2cd2b65 100644 --- a/embassy-stm32/src/pac/stm32f413vh.rs +++ b/embassy-stm32/src/pac/stm32f413vh.rs @@ -161,7 +161,61 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Mosi, PA10, 5); +impl_spi_pin!(SPI2, Miso, PA12, 5); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -220,6 +274,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -236,7 +291,8 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f413zg.rs b/embassy-stm32/src/pac/stm32f413zg.rs index e653d0cb..f2cd2b65 100644 --- a/embassy-stm32/src/pac/stm32f413zg.rs +++ b/embassy-stm32/src/pac/stm32f413zg.rs @@ -161,7 +161,61 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Mosi, PA10, 5); +impl_spi_pin!(SPI2, Miso, PA12, 5); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -220,6 +274,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -236,7 +291,8 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f413zh.rs b/embassy-stm32/src/pac/stm32f413zh.rs index e653d0cb..f2cd2b65 100644 --- a/embassy-stm32/src/pac/stm32f413zh.rs +++ b/embassy-stm32/src/pac/stm32f413zh.rs @@ -161,7 +161,61 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Mosi, PA10, 5); +impl_spi_pin!(SPI2, Miso, PA12, 5); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -220,6 +274,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -236,7 +291,8 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f415og.rs b/embassy-stm32/src/pac/stm32f415og.rs index 46f5b252..490a8c54 100644 --- a/embassy-stm32/src/pac/stm32f415og.rs +++ b/embassy-stm32/src/pac/stm32f415og.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f415rg.rs b/embassy-stm32/src/pac/stm32f415rg.rs index 46f5b252..490a8c54 100644 --- a/embassy-stm32/src/pac/stm32f415rg.rs +++ b/embassy-stm32/src/pac/stm32f415rg.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f415vg.rs b/embassy-stm32/src/pac/stm32f415vg.rs index 46f5b252..490a8c54 100644 --- a/embassy-stm32/src/pac/stm32f415vg.rs +++ b/embassy-stm32/src/pac/stm32f415vg.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f415zg.rs b/embassy-stm32/src/pac/stm32f415zg.rs index 46f5b252..490a8c54 100644 --- a/embassy-stm32/src/pac/stm32f415zg.rs +++ b/embassy-stm32/src/pac/stm32f415zg.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f417ie.rs b/embassy-stm32/src/pac/stm32f417ie.rs index 1a528a3c..04a3e952 100644 --- a/embassy-stm32/src/pac/stm32f417ie.rs +++ b/embassy-stm32/src/pac/stm32f417ie.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f417ig.rs b/embassy-stm32/src/pac/stm32f417ig.rs index 1a528a3c..04a3e952 100644 --- a/embassy-stm32/src/pac/stm32f417ig.rs +++ b/embassy-stm32/src/pac/stm32f417ig.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f417ve.rs b/embassy-stm32/src/pac/stm32f417ve.rs index 1a528a3c..04a3e952 100644 --- a/embassy-stm32/src/pac/stm32f417ve.rs +++ b/embassy-stm32/src/pac/stm32f417ve.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f417vg.rs b/embassy-stm32/src/pac/stm32f417vg.rs index 1a528a3c..04a3e952 100644 --- a/embassy-stm32/src/pac/stm32f417vg.rs +++ b/embassy-stm32/src/pac/stm32f417vg.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f417ze.rs b/embassy-stm32/src/pac/stm32f417ze.rs index 1a528a3c..04a3e952 100644 --- a/embassy-stm32/src/pac/stm32f417ze.rs +++ b/embassy-stm32/src/pac/stm32f417ze.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f417zg.rs b/embassy-stm32/src/pac/stm32f417zg.rs index 1a528a3c..04a3e952 100644 --- a/embassy-stm32/src/pac/stm32f417zg.rs +++ b/embassy-stm32/src/pac/stm32f417zg.rs @@ -178,7 +178,34 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -232,6 +259,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -249,7 +277,7 @@ peripherals!( PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f423ch.rs b/embassy-stm32/src/pac/stm32f423ch.rs index 887aa712..239676a6 100644 --- a/embassy-stm32/src/pac/stm32f423ch.rs +++ b/embassy-stm32/src/pac/stm32f423ch.rs @@ -161,7 +161,61 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Mosi, PA10, 5); +impl_spi_pin!(SPI2, Miso, PA12, 5); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -204,6 +258,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -220,7 +275,7 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f423mh.rs b/embassy-stm32/src/pac/stm32f423mh.rs index 00c927ce..0708def5 100644 --- a/embassy-stm32/src/pac/stm32f423mh.rs +++ b/embassy-stm32/src/pac/stm32f423mh.rs @@ -161,7 +161,61 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Mosi, PA10, 5); +impl_spi_pin!(SPI2, Miso, PA12, 5); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -220,6 +274,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -236,7 +291,8 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f423rh.rs b/embassy-stm32/src/pac/stm32f423rh.rs index 00c927ce..0708def5 100644 --- a/embassy-stm32/src/pac/stm32f423rh.rs +++ b/embassy-stm32/src/pac/stm32f423rh.rs @@ -161,7 +161,61 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Mosi, PA10, 5); +impl_spi_pin!(SPI2, Miso, PA12, 5); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -220,6 +274,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -236,7 +291,8 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f423vh.rs b/embassy-stm32/src/pac/stm32f423vh.rs index 00c927ce..0708def5 100644 --- a/embassy-stm32/src/pac/stm32f423vh.rs +++ b/embassy-stm32/src/pac/stm32f423vh.rs @@ -161,7 +161,61 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Mosi, PA10, 5); +impl_spi_pin!(SPI2, Miso, PA12, 5); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -220,6 +274,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -236,7 +291,8 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f423zh.rs b/embassy-stm32/src/pac/stm32f423zh.rs index 00c927ce..0708def5 100644 --- a/embassy-stm32/src/pac/stm32f423zh.rs +++ b/embassy-stm32/src/pac/stm32f423zh.rs @@ -161,7 +161,61 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Mosi, PA10, 5); +impl_spi_pin!(SPI2, Miso, PA12, 5); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB12, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Mosi, PA1, 5); +impl_spi_pin!(SPI4, Miso, PA11, 6); +impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PA10, 6); +impl_spi_pin!(SPI5, Miso, PA12, 6); +impl_spi_pin!(SPI5, Sck, PB0, 6); +impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, Sck, PE12, 6); +impl_spi_pin!(SPI5, Miso, PE13, 6); +impl_spi_pin!(SPI5, Mosi, PE14, 6); +impl_spi_pin!(SPI5, Sck, PE2, 6); +impl_spi_pin!(SPI5, Miso, PE5, 6); +impl_spi_pin!(SPI5, Mosi, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -220,6 +274,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -236,7 +291,8 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f427ag.rs b/embassy-stm32/src/pac/stm32f427ag.rs index 61acdfec..bd166eb9 100644 --- a/embassy-stm32/src/pac/stm32f427ag.rs +++ b/embassy-stm32/src/pac/stm32f427ag.rs @@ -212,7 +212,52 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +311,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +331,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f427ai.rs b/embassy-stm32/src/pac/stm32f427ai.rs index 61acdfec..bd166eb9 100644 --- a/embassy-stm32/src/pac/stm32f427ai.rs +++ b/embassy-stm32/src/pac/stm32f427ai.rs @@ -212,7 +212,52 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +311,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +331,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f427ig.rs b/embassy-stm32/src/pac/stm32f427ig.rs index 61acdfec..6d811e91 100644 --- a/embassy-stm32/src/pac/stm32f427ig.rs +++ b/embassy-stm32/src/pac/stm32f427ig.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f427ii.rs b/embassy-stm32/src/pac/stm32f427ii.rs index 61acdfec..6d811e91 100644 --- a/embassy-stm32/src/pac/stm32f427ii.rs +++ b/embassy-stm32/src/pac/stm32f427ii.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f427vg.rs b/embassy-stm32/src/pac/stm32f427vg.rs index 61acdfec..a3481b09 100644 --- a/embassy-stm32/src/pac/stm32f427vg.rs +++ b/embassy-stm32/src/pac/stm32f427vg.rs @@ -212,7 +212,44 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +303,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +323,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f427vi.rs b/embassy-stm32/src/pac/stm32f427vi.rs index 61acdfec..a3481b09 100644 --- a/embassy-stm32/src/pac/stm32f427vi.rs +++ b/embassy-stm32/src/pac/stm32f427vi.rs @@ -212,7 +212,44 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +303,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +323,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f427zg.rs b/embassy-stm32/src/pac/stm32f427zg.rs index 61acdfec..6d811e91 100644 --- a/embassy-stm32/src/pac/stm32f427zg.rs +++ b/embassy-stm32/src/pac/stm32f427zg.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f427zi.rs b/embassy-stm32/src/pac/stm32f427zi.rs index 61acdfec..6d811e91 100644 --- a/embassy-stm32/src/pac/stm32f427zi.rs +++ b/embassy-stm32/src/pac/stm32f427zi.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429ag.rs b/embassy-stm32/src/pac/stm32f429ag.rs index a1a3ab42..7b973e44 100644 --- a/embassy-stm32/src/pac/stm32f429ag.rs +++ b/embassy-stm32/src/pac/stm32f429ag.rs @@ -212,7 +212,52 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +311,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +331,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429ai.rs b/embassy-stm32/src/pac/stm32f429ai.rs index a1a3ab42..7b973e44 100644 --- a/embassy-stm32/src/pac/stm32f429ai.rs +++ b/embassy-stm32/src/pac/stm32f429ai.rs @@ -212,7 +212,52 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +311,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +331,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429be.rs b/embassy-stm32/src/pac/stm32f429be.rs index a1a3ab42..9a4d45b1 100644 --- a/embassy-stm32/src/pac/stm32f429be.rs +++ b/embassy-stm32/src/pac/stm32f429be.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429bg.rs b/embassy-stm32/src/pac/stm32f429bg.rs index a1a3ab42..9a4d45b1 100644 --- a/embassy-stm32/src/pac/stm32f429bg.rs +++ b/embassy-stm32/src/pac/stm32f429bg.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429bi.rs b/embassy-stm32/src/pac/stm32f429bi.rs index a1a3ab42..9a4d45b1 100644 --- a/embassy-stm32/src/pac/stm32f429bi.rs +++ b/embassy-stm32/src/pac/stm32f429bi.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429ie.rs b/embassy-stm32/src/pac/stm32f429ie.rs index a1a3ab42..9a4d45b1 100644 --- a/embassy-stm32/src/pac/stm32f429ie.rs +++ b/embassy-stm32/src/pac/stm32f429ie.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429ig.rs b/embassy-stm32/src/pac/stm32f429ig.rs index a1a3ab42..9a4d45b1 100644 --- a/embassy-stm32/src/pac/stm32f429ig.rs +++ b/embassy-stm32/src/pac/stm32f429ig.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429ii.rs b/embassy-stm32/src/pac/stm32f429ii.rs index a1a3ab42..9a4d45b1 100644 --- a/embassy-stm32/src/pac/stm32f429ii.rs +++ b/embassy-stm32/src/pac/stm32f429ii.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429ne.rs b/embassy-stm32/src/pac/stm32f429ne.rs index a1a3ab42..9a4d45b1 100644 --- a/embassy-stm32/src/pac/stm32f429ne.rs +++ b/embassy-stm32/src/pac/stm32f429ne.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429ng.rs b/embassy-stm32/src/pac/stm32f429ng.rs index a1a3ab42..9a4d45b1 100644 --- a/embassy-stm32/src/pac/stm32f429ng.rs +++ b/embassy-stm32/src/pac/stm32f429ng.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429ni.rs b/embassy-stm32/src/pac/stm32f429ni.rs index a1a3ab42..9a4d45b1 100644 --- a/embassy-stm32/src/pac/stm32f429ni.rs +++ b/embassy-stm32/src/pac/stm32f429ni.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429ve.rs b/embassy-stm32/src/pac/stm32f429ve.rs index a1a3ab42..bc50d0d0 100644 --- a/embassy-stm32/src/pac/stm32f429ve.rs +++ b/embassy-stm32/src/pac/stm32f429ve.rs @@ -212,7 +212,44 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +303,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +323,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429vg.rs b/embassy-stm32/src/pac/stm32f429vg.rs index a1a3ab42..bc50d0d0 100644 --- a/embassy-stm32/src/pac/stm32f429vg.rs +++ b/embassy-stm32/src/pac/stm32f429vg.rs @@ -212,7 +212,44 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +303,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +323,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429vi.rs b/embassy-stm32/src/pac/stm32f429vi.rs index a1a3ab42..bc50d0d0 100644 --- a/embassy-stm32/src/pac/stm32f429vi.rs +++ b/embassy-stm32/src/pac/stm32f429vi.rs @@ -212,7 +212,44 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +303,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +323,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429ze.rs b/embassy-stm32/src/pac/stm32f429ze.rs index a1a3ab42..9a4d45b1 100644 --- a/embassy-stm32/src/pac/stm32f429ze.rs +++ b/embassy-stm32/src/pac/stm32f429ze.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429zg.rs b/embassy-stm32/src/pac/stm32f429zg.rs index a1a3ab42..9a4d45b1 100644 --- a/embassy-stm32/src/pac/stm32f429zg.rs +++ b/embassy-stm32/src/pac/stm32f429zg.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f429zi.rs b/embassy-stm32/src/pac/stm32f429zi.rs index a1a3ab42..9a4d45b1 100644 --- a/embassy-stm32/src/pac/stm32f429zi.rs +++ b/embassy-stm32/src/pac/stm32f429zi.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f437ai.rs b/embassy-stm32/src/pac/stm32f437ai.rs index 3c30eec9..83748a01 100644 --- a/embassy-stm32/src/pac/stm32f437ai.rs +++ b/embassy-stm32/src/pac/stm32f437ai.rs @@ -212,7 +212,52 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +311,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +331,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f437ig.rs b/embassy-stm32/src/pac/stm32f437ig.rs index 3c30eec9..30c8712e 100644 --- a/embassy-stm32/src/pac/stm32f437ig.rs +++ b/embassy-stm32/src/pac/stm32f437ig.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f437ii.rs b/embassy-stm32/src/pac/stm32f437ii.rs index 3c30eec9..30c8712e 100644 --- a/embassy-stm32/src/pac/stm32f437ii.rs +++ b/embassy-stm32/src/pac/stm32f437ii.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f437vg.rs b/embassy-stm32/src/pac/stm32f437vg.rs index 3c30eec9..f7059b8a 100644 --- a/embassy-stm32/src/pac/stm32f437vg.rs +++ b/embassy-stm32/src/pac/stm32f437vg.rs @@ -212,7 +212,44 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +303,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +323,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f437vi.rs b/embassy-stm32/src/pac/stm32f437vi.rs index 3c30eec9..f7059b8a 100644 --- a/embassy-stm32/src/pac/stm32f437vi.rs +++ b/embassy-stm32/src/pac/stm32f437vi.rs @@ -212,7 +212,44 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +303,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +323,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f437zg.rs b/embassy-stm32/src/pac/stm32f437zg.rs index 3c30eec9..30c8712e 100644 --- a/embassy-stm32/src/pac/stm32f437zg.rs +++ b/embassy-stm32/src/pac/stm32f437zg.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f437zi.rs b/embassy-stm32/src/pac/stm32f437zi.rs index 3c30eec9..30c8712e 100644 --- a/embassy-stm32/src/pac/stm32f437zi.rs +++ b/embassy-stm32/src/pac/stm32f437zi.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f439ai.rs b/embassy-stm32/src/pac/stm32f439ai.rs index 379a3d70..128ffc57 100644 --- a/embassy-stm32/src/pac/stm32f439ai.rs +++ b/embassy-stm32/src/pac/stm32f439ai.rs @@ -212,7 +212,52 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +311,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +331,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f439bg.rs b/embassy-stm32/src/pac/stm32f439bg.rs index 379a3d70..34ffaac9 100644 --- a/embassy-stm32/src/pac/stm32f439bg.rs +++ b/embassy-stm32/src/pac/stm32f439bg.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f439bi.rs b/embassy-stm32/src/pac/stm32f439bi.rs index 379a3d70..34ffaac9 100644 --- a/embassy-stm32/src/pac/stm32f439bi.rs +++ b/embassy-stm32/src/pac/stm32f439bi.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f439ig.rs b/embassy-stm32/src/pac/stm32f439ig.rs index 379a3d70..34ffaac9 100644 --- a/embassy-stm32/src/pac/stm32f439ig.rs +++ b/embassy-stm32/src/pac/stm32f439ig.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f439ii.rs b/embassy-stm32/src/pac/stm32f439ii.rs index 379a3d70..34ffaac9 100644 --- a/embassy-stm32/src/pac/stm32f439ii.rs +++ b/embassy-stm32/src/pac/stm32f439ii.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f439ng.rs b/embassy-stm32/src/pac/stm32f439ng.rs index 379a3d70..34ffaac9 100644 --- a/embassy-stm32/src/pac/stm32f439ng.rs +++ b/embassy-stm32/src/pac/stm32f439ng.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f439ni.rs b/embassy-stm32/src/pac/stm32f439ni.rs index 379a3d70..34ffaac9 100644 --- a/embassy-stm32/src/pac/stm32f439ni.rs +++ b/embassy-stm32/src/pac/stm32f439ni.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f439vg.rs b/embassy-stm32/src/pac/stm32f439vg.rs index 379a3d70..3228bc47 100644 --- a/embassy-stm32/src/pac/stm32f439vg.rs +++ b/embassy-stm32/src/pac/stm32f439vg.rs @@ -212,7 +212,44 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +303,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +323,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f439vi.rs b/embassy-stm32/src/pac/stm32f439vi.rs index 379a3d70..3228bc47 100644 --- a/embassy-stm32/src/pac/stm32f439vi.rs +++ b/embassy-stm32/src/pac/stm32f439vi.rs @@ -212,7 +212,44 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +303,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +323,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f439zg.rs b/embassy-stm32/src/pac/stm32f439zg.rs index 379a3d70..34ffaac9 100644 --- a/embassy-stm32/src/pac/stm32f439zg.rs +++ b/embassy-stm32/src/pac/stm32f439zg.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f439zi.rs b/embassy-stm32/src/pac/stm32f439zi.rs index 379a3d70..34ffaac9 100644 --- a/embassy-stm32/src/pac/stm32f439zi.rs +++ b/embassy-stm32/src/pac/stm32f439zi.rs @@ -212,7 +212,57 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, Sck, PI1, 5); +impl_spi_pin!(SPI2, Miso, PI2, 5); +impl_spi_pin!(SPI2, Mosi, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, Mosi, PF11, 5); +impl_spi_pin!(SPI5, Sck, PF7, 5); +impl_spi_pin!(SPI5, Miso, PF8, 5); +impl_spi_pin!(SPI5, Mosi, PF9, 5); +impl_spi_pin!(SPI5, Sck, PH6, 5); +impl_spi_pin!(SPI5, Miso, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, Miso, PG12, 5); +impl_spi_pin!(SPI6, Sck, PG13, 5); +impl_spi_pin!(SPI6, Mosi, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -266,6 +316,7 @@ pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -285,7 +336,7 @@ peripherals!( PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f446mc.rs b/embassy-stm32/src/pac/stm32f446mc.rs index 99da317f..eda63c60 100644 --- a/embassy-stm32/src/pac/stm32f446mc.rs +++ b/embassy-stm32/src/pac/stm32f446mc.rs @@ -160,6 +160,51 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 7); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Mosi, PB0, 7); +impl_spi_pin!(SPI3, Mosi, PB2, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Mosi, PC1, 5); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD0, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Miso, PD0, 5); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, Sck, PG11, 6); +impl_spi_pin!(SPI4, Miso, PG12, 6); +impl_spi_pin!(SPI4, Mosi, PG13, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -213,6 +258,7 @@ impl_usart_pin!(USART6, RxPin, PG9, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -229,7 +275,7 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f446me.rs b/embassy-stm32/src/pac/stm32f446me.rs index 99da317f..eda63c60 100644 --- a/embassy-stm32/src/pac/stm32f446me.rs +++ b/embassy-stm32/src/pac/stm32f446me.rs @@ -160,6 +160,51 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 7); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Mosi, PB0, 7); +impl_spi_pin!(SPI3, Mosi, PB2, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Mosi, PC1, 5); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD0, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Miso, PD0, 5); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, Sck, PG11, 6); +impl_spi_pin!(SPI4, Miso, PG12, 6); +impl_spi_pin!(SPI4, Mosi, PG13, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -213,6 +258,7 @@ impl_usart_pin!(USART6, RxPin, PG9, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -229,7 +275,7 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f446rc.rs b/embassy-stm32/src/pac/stm32f446rc.rs index 99da317f..78c721ce 100644 --- a/embassy-stm32/src/pac/stm32f446rc.rs +++ b/embassy-stm32/src/pac/stm32f446rc.rs @@ -160,6 +160,39 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 7); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Mosi, PB0, 7); +impl_spi_pin!(SPI3, Mosi, PB2, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Mosi, PC1, 5); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD0, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -213,6 +246,7 @@ impl_usart_pin!(USART6, RxPin, PG9, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -229,7 +263,7 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f446re.rs b/embassy-stm32/src/pac/stm32f446re.rs index 99da317f..78c721ce 100644 --- a/embassy-stm32/src/pac/stm32f446re.rs +++ b/embassy-stm32/src/pac/stm32f446re.rs @@ -160,6 +160,39 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 7); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Mosi, PB0, 7); +impl_spi_pin!(SPI3, Mosi, PB2, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Mosi, PC1, 5); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD0, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -213,6 +246,7 @@ impl_usart_pin!(USART6, RxPin, PG9, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -229,7 +263,7 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f446vc.rs b/embassy-stm32/src/pac/stm32f446vc.rs index 99da317f..eda63c60 100644 --- a/embassy-stm32/src/pac/stm32f446vc.rs +++ b/embassy-stm32/src/pac/stm32f446vc.rs @@ -160,6 +160,51 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 7); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Mosi, PB0, 7); +impl_spi_pin!(SPI3, Mosi, PB2, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Mosi, PC1, 5); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD0, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Miso, PD0, 5); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, Sck, PG11, 6); +impl_spi_pin!(SPI4, Miso, PG12, 6); +impl_spi_pin!(SPI4, Mosi, PG13, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -213,6 +258,7 @@ impl_usart_pin!(USART6, RxPin, PG9, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -229,7 +275,7 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f446ve.rs b/embassy-stm32/src/pac/stm32f446ve.rs index 99da317f..eda63c60 100644 --- a/embassy-stm32/src/pac/stm32f446ve.rs +++ b/embassy-stm32/src/pac/stm32f446ve.rs @@ -160,6 +160,51 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 7); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Mosi, PB0, 7); +impl_spi_pin!(SPI3, Mosi, PB2, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Mosi, PC1, 5); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD0, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Miso, PD0, 5); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, Sck, PG11, 6); +impl_spi_pin!(SPI4, Miso, PG12, 6); +impl_spi_pin!(SPI4, Mosi, PG13, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -213,6 +258,7 @@ impl_usart_pin!(USART6, RxPin, PG9, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -229,7 +275,7 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f446zc.rs b/embassy-stm32/src/pac/stm32f446zc.rs index 99da317f..eda63c60 100644 --- a/embassy-stm32/src/pac/stm32f446zc.rs +++ b/embassy-stm32/src/pac/stm32f446zc.rs @@ -160,6 +160,51 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 7); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Mosi, PB0, 7); +impl_spi_pin!(SPI3, Mosi, PB2, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Mosi, PC1, 5); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD0, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Miso, PD0, 5); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, Sck, PG11, 6); +impl_spi_pin!(SPI4, Miso, PG12, 6); +impl_spi_pin!(SPI4, Mosi, PG13, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -213,6 +258,7 @@ impl_usart_pin!(USART6, RxPin, PG9, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -229,7 +275,7 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f446ze.rs b/embassy-stm32/src/pac/stm32f446ze.rs index 99da317f..eda63c60 100644 --- a/embassy-stm32/src/pac/stm32f446ze.rs +++ b/embassy-stm32/src/pac/stm32f446ze.rs @@ -160,6 +160,51 @@ impl_gpio_pin!(PH12, 7, 12, EXTI12); impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, Sck, PA5, 5); +impl_spi_pin!(SPI1, Miso, PA6, 5); +impl_spi_pin!(SPI1, Mosi, PA7, 5); +impl_spi_pin!(SPI1, Sck, PB3, 5); +impl_spi_pin!(SPI1, Miso, PB4, 5); +impl_spi_pin!(SPI1, Mosi, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, Sck, PA9, 5); +impl_spi_pin!(SPI2, Sck, PB10, 5); +impl_spi_pin!(SPI2, Sck, PB13, 5); +impl_spi_pin!(SPI2, Miso, PB14, 5); +impl_spi_pin!(SPI2, Mosi, PB15, 5); +impl_spi_pin!(SPI2, Mosi, PC1, 7); +impl_spi_pin!(SPI2, Miso, PC2, 5); +impl_spi_pin!(SPI2, Mosi, PC3, 5); +impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, Sck, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, Mosi, PB0, 7); +impl_spi_pin!(SPI3, Mosi, PB2, 7); +impl_spi_pin!(SPI3, Sck, PB3, 6); +impl_spi_pin!(SPI3, Miso, PB4, 6); +impl_spi_pin!(SPI3, Mosi, PB5, 6); +impl_spi_pin!(SPI3, Mosi, PC1, 5); +impl_spi_pin!(SPI3, Sck, PC10, 6); +impl_spi_pin!(SPI3, Miso, PC11, 6); +impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, Mosi, PD0, 6); +impl_spi_pin!(SPI3, Mosi, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, Miso, PD0, 5); +impl_spi_pin!(SPI4, Sck, PE12, 5); +impl_spi_pin!(SPI4, Miso, PE13, 5); +impl_spi_pin!(SPI4, Mosi, PE14, 5); +impl_spi_pin!(SPI4, Sck, PE2, 5); +impl_spi_pin!(SPI4, Miso, PE5, 5); +impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, Sck, PG11, 6); +impl_spi_pin!(SPI4, Miso, PG12, 6); +impl_spi_pin!(SPI4, Mosi, PG13, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); @@ -213,6 +258,7 @@ impl_usart_pin!(USART6, RxPin, PG9, 8); pub use regs::dma_v2 as dma; pub use regs::exti_v1 as exti; pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; pub use regs::syscfg_f4 as syscfg; pub use regs::usart_v1 as usart; mod regs; @@ -229,7 +275,7 @@ peripherals!( PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, SYSCFG, USART1, USART2, USART3, USART6 + PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 ); pub mod interrupt { diff --git a/embassy-stm32/src/pac/stm32f469ae.rs b/embassy-stm32/src/pac/stm32f469ae.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469ae.rs +++ b/embassy-stm32/src/pac/stm32f469ae.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469ag.rs b/embassy-stm32/src/pac/stm32f469ag.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469ag.rs +++ b/embassy-stm32/src/pac/stm32f469ag.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469ai.rs b/embassy-stm32/src/pac/stm32f469ai.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469ai.rs +++ b/embassy-stm32/src/pac/stm32f469ai.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469be.rs b/embassy-stm32/src/pac/stm32f469be.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469be.rs +++ b/embassy-stm32/src/pac/stm32f469be.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469bg.rs b/embassy-stm32/src/pac/stm32f469bg.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469bg.rs +++ b/embassy-stm32/src/pac/stm32f469bg.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469bi.rs b/embassy-stm32/src/pac/stm32f469bi.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469bi.rs +++ b/embassy-stm32/src/pac/stm32f469bi.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469ie.rs b/embassy-stm32/src/pac/stm32f469ie.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469ie.rs +++ b/embassy-stm32/src/pac/stm32f469ie.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469ig.rs b/embassy-stm32/src/pac/stm32f469ig.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469ig.rs +++ b/embassy-stm32/src/pac/stm32f469ig.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469ii.rs b/embassy-stm32/src/pac/stm32f469ii.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469ii.rs +++ b/embassy-stm32/src/pac/stm32f469ii.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469ne.rs b/embassy-stm32/src/pac/stm32f469ne.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469ne.rs +++ b/embassy-stm32/src/pac/stm32f469ne.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469ng.rs b/embassy-stm32/src/pac/stm32f469ng.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469ng.rs +++ b/embassy-stm32/src/pac/stm32f469ng.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469ni.rs b/embassy-stm32/src/pac/stm32f469ni.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469ni.rs +++ b/embassy-stm32/src/pac/stm32f469ni.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469ve.rs b/embassy-stm32/src/pac/stm32f469ve.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469ve.rs +++ b/embassy-stm32/src/pac/stm32f469ve.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469vg.rs b/embassy-stm32/src/pac/stm32f469vg.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469vg.rs +++ b/embassy-stm32/src/pac/stm32f469vg.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469vi.rs b/embassy-stm32/src/pac/stm32f469vi.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469vi.rs +++ b/embassy-stm32/src/pac/stm32f469vi.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469ze.rs b/embassy-stm32/src/pac/stm32f469ze.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469ze.rs +++ b/embassy-stm32/src/pac/stm32f469ze.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469zg.rs b/embassy-stm32/src/pac/stm32f469zg.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469zg.rs +++ b/embassy-stm32/src/pac/stm32f469zg.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f469zi.rs b/embassy-stm32/src/pac/stm32f469zi.rs index bf68c2f6..c44fd8ee 100644 --- a/embassy-stm32/src/pac/stm32f469zi.rs +++ b/embassy-stm32/src/pac/stm32f469zi.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f479ag.rs b/embassy-stm32/src/pac/stm32f479ag.rs index 67bdb039..fbb2b54c 100644 --- a/embassy-stm32/src/pac/stm32f479ag.rs +++ b/embassy-stm32/src/pac/stm32f479ag.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f479ai.rs b/embassy-stm32/src/pac/stm32f479ai.rs index 67bdb039..fbb2b54c 100644 --- a/embassy-stm32/src/pac/stm32f479ai.rs +++ b/embassy-stm32/src/pac/stm32f479ai.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f479bg.rs b/embassy-stm32/src/pac/stm32f479bg.rs index 67bdb039..fbb2b54c 100644 --- a/embassy-stm32/src/pac/stm32f479bg.rs +++ b/embassy-stm32/src/pac/stm32f479bg.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f479bi.rs b/embassy-stm32/src/pac/stm32f479bi.rs index 67bdb039..fbb2b54c 100644 --- a/embassy-stm32/src/pac/stm32f479bi.rs +++ b/embassy-stm32/src/pac/stm32f479bi.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f479ig.rs b/embassy-stm32/src/pac/stm32f479ig.rs index 67bdb039..fbb2b54c 100644 --- a/embassy-stm32/src/pac/stm32f479ig.rs +++ b/embassy-stm32/src/pac/stm32f479ig.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f479ii.rs b/embassy-stm32/src/pac/stm32f479ii.rs index 67bdb039..fbb2b54c 100644 --- a/embassy-stm32/src/pac/stm32f479ii.rs +++ b/embassy-stm32/src/pac/stm32f479ii.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f479ng.rs b/embassy-stm32/src/pac/stm32f479ng.rs index 67bdb039..fbb2b54c 100644 --- a/embassy-stm32/src/pac/stm32f479ng.rs +++ b/embassy-stm32/src/pac/stm32f479ng.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f479ni.rs b/embassy-stm32/src/pac/stm32f479ni.rs index 67bdb039..fbb2b54c 100644 --- a/embassy-stm32/src/pac/stm32f479ni.rs +++ b/embassy-stm32/src/pac/stm32f479ni.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f479vg.rs b/embassy-stm32/src/pac/stm32f479vg.rs index 67bdb039..fbb2b54c 100644 --- a/embassy-stm32/src/pac/stm32f479vg.rs +++ b/embassy-stm32/src/pac/stm32f479vg.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f479vi.rs b/embassy-stm32/src/pac/stm32f479vi.rs index 67bdb039..fbb2b54c 100644 --- a/embassy-stm32/src/pac/stm32f479vi.rs +++ b/embassy-stm32/src/pac/stm32f479vi.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f479zg.rs b/embassy-stm32/src/pac/stm32f479zg.rs index 67bdb039..fbb2b54c 100644 --- a/embassy-stm32/src/pac/stm32f479zg.rs +++ b/embassy-stm32/src/pac/stm32f479zg.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f479zi.rs b/embassy-stm32/src/pac/stm32f479zi.rs index 67bdb039..fbb2b54c 100644 --- a/embassy-stm32/src/pac/stm32f479zi.rs +++ b/embassy-stm32/src/pac/stm32f479zi.rs @@ -212,7 +212,7 @@ impl_gpio_pin!(PK13, 10, 13, EXTI13); impl_gpio_pin!(PK14, 10, 14, EXTI14); impl_gpio_pin!(PK15, 10, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l412c8.rs b/embassy-stm32/src/pac/stm32l412c8.rs index 5478ea82..6f7f9d3b 100644 --- a/embassy-stm32/src/pac/stm32l412c8.rs +++ b/embassy-stm32/src/pac/stm32l412c8.rs @@ -110,7 +110,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l412cb.rs b/embassy-stm32/src/pac/stm32l412cb.rs index 5478ea82..6f7f9d3b 100644 --- a/embassy-stm32/src/pac/stm32l412cb.rs +++ b/embassy-stm32/src/pac/stm32l412cb.rs @@ -110,7 +110,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l412k8.rs b/embassy-stm32/src/pac/stm32l412k8.rs index f7027eea..a8f1ee4b 100644 --- a/embassy-stm32/src/pac/stm32l412k8.rs +++ b/embassy-stm32/src/pac/stm32l412k8.rs @@ -110,7 +110,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l412kb.rs b/embassy-stm32/src/pac/stm32l412kb.rs index f7027eea..a8f1ee4b 100644 --- a/embassy-stm32/src/pac/stm32l412kb.rs +++ b/embassy-stm32/src/pac/stm32l412kb.rs @@ -110,7 +110,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l412r8.rs b/embassy-stm32/src/pac/stm32l412r8.rs index 5478ea82..6f7f9d3b 100644 --- a/embassy-stm32/src/pac/stm32l412r8.rs +++ b/embassy-stm32/src/pac/stm32l412r8.rs @@ -110,7 +110,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l412rb.rs b/embassy-stm32/src/pac/stm32l412rb.rs index 5478ea82..6f7f9d3b 100644 --- a/embassy-stm32/src/pac/stm32l412rb.rs +++ b/embassy-stm32/src/pac/stm32l412rb.rs @@ -110,7 +110,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l412t8.rs b/embassy-stm32/src/pac/stm32l412t8.rs index f7027eea..a8f1ee4b 100644 --- a/embassy-stm32/src/pac/stm32l412t8.rs +++ b/embassy-stm32/src/pac/stm32l412t8.rs @@ -110,7 +110,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l412tb.rs b/embassy-stm32/src/pac/stm32l412tb.rs index f7027eea..a8f1ee4b 100644 --- a/embassy-stm32/src/pac/stm32l412tb.rs +++ b/embassy-stm32/src/pac/stm32l412tb.rs @@ -110,7 +110,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l422cb.rs b/embassy-stm32/src/pac/stm32l422cb.rs index 7a85aca7..2faebe71 100644 --- a/embassy-stm32/src/pac/stm32l422cb.rs +++ b/embassy-stm32/src/pac/stm32l422cb.rs @@ -110,7 +110,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l422kb.rs b/embassy-stm32/src/pac/stm32l422kb.rs index 7de35a6c..36dca78d 100644 --- a/embassy-stm32/src/pac/stm32l422kb.rs +++ b/embassy-stm32/src/pac/stm32l422kb.rs @@ -110,7 +110,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l422rb.rs b/embassy-stm32/src/pac/stm32l422rb.rs index 7a85aca7..2faebe71 100644 --- a/embassy-stm32/src/pac/stm32l422rb.rs +++ b/embassy-stm32/src/pac/stm32l422rb.rs @@ -110,7 +110,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l422tb.rs b/embassy-stm32/src/pac/stm32l422tb.rs index 7de35a6c..36dca78d 100644 --- a/embassy-stm32/src/pac/stm32l422tb.rs +++ b/embassy-stm32/src/pac/stm32l422tb.rs @@ -110,7 +110,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l431cb.rs b/embassy-stm32/src/pac/stm32l431cb.rs index ddb208da..3526babf 100644 --- a/embassy-stm32/src/pac/stm32l431cb.rs +++ b/embassy-stm32/src/pac/stm32l431cb.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l431cc.rs b/embassy-stm32/src/pac/stm32l431cc.rs index ddb208da..3526babf 100644 --- a/embassy-stm32/src/pac/stm32l431cc.rs +++ b/embassy-stm32/src/pac/stm32l431cc.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l431kb.rs b/embassy-stm32/src/pac/stm32l431kb.rs index 89364c77..6ee92e99 100644 --- a/embassy-stm32/src/pac/stm32l431kb.rs +++ b/embassy-stm32/src/pac/stm32l431kb.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l431kc.rs b/embassy-stm32/src/pac/stm32l431kc.rs index 89364c77..6ee92e99 100644 --- a/embassy-stm32/src/pac/stm32l431kc.rs +++ b/embassy-stm32/src/pac/stm32l431kc.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l431rb.rs b/embassy-stm32/src/pac/stm32l431rb.rs index ddb208da..3526babf 100644 --- a/embassy-stm32/src/pac/stm32l431rb.rs +++ b/embassy-stm32/src/pac/stm32l431rb.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l431rc.rs b/embassy-stm32/src/pac/stm32l431rc.rs index ddb208da..3526babf 100644 --- a/embassy-stm32/src/pac/stm32l431rc.rs +++ b/embassy-stm32/src/pac/stm32l431rc.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l431vc.rs b/embassy-stm32/src/pac/stm32l431vc.rs index ddb208da..3526babf 100644 --- a/embassy-stm32/src/pac/stm32l431vc.rs +++ b/embassy-stm32/src/pac/stm32l431vc.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l432kb.rs b/embassy-stm32/src/pac/stm32l432kb.rs index a5e060d0..520a130a 100644 --- a/embassy-stm32/src/pac/stm32l432kb.rs +++ b/embassy-stm32/src/pac/stm32l432kb.rs @@ -93,7 +93,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l432kc.rs b/embassy-stm32/src/pac/stm32l432kc.rs index a5e060d0..520a130a 100644 --- a/embassy-stm32/src/pac/stm32l432kc.rs +++ b/embassy-stm32/src/pac/stm32l432kc.rs @@ -93,7 +93,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l433cb.rs b/embassy-stm32/src/pac/stm32l433cb.rs index 0c60e842..d7c46042 100644 --- a/embassy-stm32/src/pac/stm32l433cb.rs +++ b/embassy-stm32/src/pac/stm32l433cb.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l433cc.rs b/embassy-stm32/src/pac/stm32l433cc.rs index 0c60e842..d7c46042 100644 --- a/embassy-stm32/src/pac/stm32l433cc.rs +++ b/embassy-stm32/src/pac/stm32l433cc.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l433rb.rs b/embassy-stm32/src/pac/stm32l433rb.rs index 0c60e842..d7c46042 100644 --- a/embassy-stm32/src/pac/stm32l433rb.rs +++ b/embassy-stm32/src/pac/stm32l433rb.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l433rc.rs b/embassy-stm32/src/pac/stm32l433rc.rs index 0c60e842..d7c46042 100644 --- a/embassy-stm32/src/pac/stm32l433rc.rs +++ b/embassy-stm32/src/pac/stm32l433rc.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l433vc.rs b/embassy-stm32/src/pac/stm32l433vc.rs index 0c60e842..d7c46042 100644 --- a/embassy-stm32/src/pac/stm32l433vc.rs +++ b/embassy-stm32/src/pac/stm32l433vc.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l442kc.rs b/embassy-stm32/src/pac/stm32l442kc.rs index dfccb891..7a7e0780 100644 --- a/embassy-stm32/src/pac/stm32l442kc.rs +++ b/embassy-stm32/src/pac/stm32l442kc.rs @@ -93,7 +93,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l443cc.rs b/embassy-stm32/src/pac/stm32l443cc.rs index 5e4f9fe1..a3a63382 100644 --- a/embassy-stm32/src/pac/stm32l443cc.rs +++ b/embassy-stm32/src/pac/stm32l443cc.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l443rc.rs b/embassy-stm32/src/pac/stm32l443rc.rs index 5e4f9fe1..a3a63382 100644 --- a/embassy-stm32/src/pac/stm32l443rc.rs +++ b/embassy-stm32/src/pac/stm32l443rc.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l443vc.rs b/embassy-stm32/src/pac/stm32l443vc.rs index 5e4f9fe1..a3a63382 100644 --- a/embassy-stm32/src/pac/stm32l443vc.rs +++ b/embassy-stm32/src/pac/stm32l443vc.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l451cc.rs b/embassy-stm32/src/pac/stm32l451cc.rs index 031a9af0..f574c379 100644 --- a/embassy-stm32/src/pac/stm32l451cc.rs +++ b/embassy-stm32/src/pac/stm32l451cc.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l451ce.rs b/embassy-stm32/src/pac/stm32l451ce.rs index 031a9af0..f574c379 100644 --- a/embassy-stm32/src/pac/stm32l451ce.rs +++ b/embassy-stm32/src/pac/stm32l451ce.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l451rc.rs b/embassy-stm32/src/pac/stm32l451rc.rs index 031a9af0..f574c379 100644 --- a/embassy-stm32/src/pac/stm32l451rc.rs +++ b/embassy-stm32/src/pac/stm32l451rc.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l451re.rs b/embassy-stm32/src/pac/stm32l451re.rs index 031a9af0..f574c379 100644 --- a/embassy-stm32/src/pac/stm32l451re.rs +++ b/embassy-stm32/src/pac/stm32l451re.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l451vc.rs b/embassy-stm32/src/pac/stm32l451vc.rs index 031a9af0..f574c379 100644 --- a/embassy-stm32/src/pac/stm32l451vc.rs +++ b/embassy-stm32/src/pac/stm32l451vc.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l451ve.rs b/embassy-stm32/src/pac/stm32l451ve.rs index 031a9af0..f574c379 100644 --- a/embassy-stm32/src/pac/stm32l451ve.rs +++ b/embassy-stm32/src/pac/stm32l451ve.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l452cc.rs b/embassy-stm32/src/pac/stm32l452cc.rs index 70c0e7e4..fdb8f0e7 100644 --- a/embassy-stm32/src/pac/stm32l452cc.rs +++ b/embassy-stm32/src/pac/stm32l452cc.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l452ce.rs b/embassy-stm32/src/pac/stm32l452ce.rs index 70c0e7e4..fdb8f0e7 100644 --- a/embassy-stm32/src/pac/stm32l452ce.rs +++ b/embassy-stm32/src/pac/stm32l452ce.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l452rc.rs b/embassy-stm32/src/pac/stm32l452rc.rs index 70c0e7e4..fdb8f0e7 100644 --- a/embassy-stm32/src/pac/stm32l452rc.rs +++ b/embassy-stm32/src/pac/stm32l452rc.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l452re.rs b/embassy-stm32/src/pac/stm32l452re.rs index 70c0e7e4..fdb8f0e7 100644 --- a/embassy-stm32/src/pac/stm32l452re.rs +++ b/embassy-stm32/src/pac/stm32l452re.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l452vc.rs b/embassy-stm32/src/pac/stm32l452vc.rs index 70c0e7e4..fdb8f0e7 100644 --- a/embassy-stm32/src/pac/stm32l452vc.rs +++ b/embassy-stm32/src/pac/stm32l452vc.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l452ve.rs b/embassy-stm32/src/pac/stm32l452ve.rs index 70c0e7e4..fdb8f0e7 100644 --- a/embassy-stm32/src/pac/stm32l452ve.rs +++ b/embassy-stm32/src/pac/stm32l452ve.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l462ce.rs b/embassy-stm32/src/pac/stm32l462ce.rs index 5eff9047..c039d6a8 100644 --- a/embassy-stm32/src/pac/stm32l462ce.rs +++ b/embassy-stm32/src/pac/stm32l462ce.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l462re.rs b/embassy-stm32/src/pac/stm32l462re.rs index 5eff9047..c039d6a8 100644 --- a/embassy-stm32/src/pac/stm32l462re.rs +++ b/embassy-stm32/src/pac/stm32l462re.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l462ve.rs b/embassy-stm32/src/pac/stm32l462ve.rs index 5eff9047..c039d6a8 100644 --- a/embassy-stm32/src/pac/stm32l462ve.rs +++ b/embassy-stm32/src/pac/stm32l462ve.rs @@ -127,7 +127,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l471qe.rs b/embassy-stm32/src/pac/stm32l471qe.rs index 71937686..2a9444a6 100644 --- a/embassy-stm32/src/pac/stm32l471qe.rs +++ b/embassy-stm32/src/pac/stm32l471qe.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l471qg.rs b/embassy-stm32/src/pac/stm32l471qg.rs index 71937686..2a9444a6 100644 --- a/embassy-stm32/src/pac/stm32l471qg.rs +++ b/embassy-stm32/src/pac/stm32l471qg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l471re.rs b/embassy-stm32/src/pac/stm32l471re.rs index 71937686..2a9444a6 100644 --- a/embassy-stm32/src/pac/stm32l471re.rs +++ b/embassy-stm32/src/pac/stm32l471re.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l471rg.rs b/embassy-stm32/src/pac/stm32l471rg.rs index 71937686..2a9444a6 100644 --- a/embassy-stm32/src/pac/stm32l471rg.rs +++ b/embassy-stm32/src/pac/stm32l471rg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l471ve.rs b/embassy-stm32/src/pac/stm32l471ve.rs index 71937686..2a9444a6 100644 --- a/embassy-stm32/src/pac/stm32l471ve.rs +++ b/embassy-stm32/src/pac/stm32l471ve.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l471vg.rs b/embassy-stm32/src/pac/stm32l471vg.rs index 71937686..2a9444a6 100644 --- a/embassy-stm32/src/pac/stm32l471vg.rs +++ b/embassy-stm32/src/pac/stm32l471vg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l471ze.rs b/embassy-stm32/src/pac/stm32l471ze.rs index 71937686..2a9444a6 100644 --- a/embassy-stm32/src/pac/stm32l471ze.rs +++ b/embassy-stm32/src/pac/stm32l471ze.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l471zg.rs b/embassy-stm32/src/pac/stm32l471zg.rs index 71937686..2a9444a6 100644 --- a/embassy-stm32/src/pac/stm32l471zg.rs +++ b/embassy-stm32/src/pac/stm32l471zg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l475rc.rs b/embassy-stm32/src/pac/stm32l475rc.rs index 5b993741..40de9ba8 100644 --- a/embassy-stm32/src/pac/stm32l475rc.rs +++ b/embassy-stm32/src/pac/stm32l475rc.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l475re.rs b/embassy-stm32/src/pac/stm32l475re.rs index 5b993741..40de9ba8 100644 --- a/embassy-stm32/src/pac/stm32l475re.rs +++ b/embassy-stm32/src/pac/stm32l475re.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l475rg.rs b/embassy-stm32/src/pac/stm32l475rg.rs index 5b993741..40de9ba8 100644 --- a/embassy-stm32/src/pac/stm32l475rg.rs +++ b/embassy-stm32/src/pac/stm32l475rg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l475vc.rs b/embassy-stm32/src/pac/stm32l475vc.rs index 5b993741..40de9ba8 100644 --- a/embassy-stm32/src/pac/stm32l475vc.rs +++ b/embassy-stm32/src/pac/stm32l475vc.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l475ve.rs b/embassy-stm32/src/pac/stm32l475ve.rs index 5b993741..40de9ba8 100644 --- a/embassy-stm32/src/pac/stm32l475ve.rs +++ b/embassy-stm32/src/pac/stm32l475ve.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l475vg.rs b/embassy-stm32/src/pac/stm32l475vg.rs index 5b993741..40de9ba8 100644 --- a/embassy-stm32/src/pac/stm32l475vg.rs +++ b/embassy-stm32/src/pac/stm32l475vg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l476je.rs b/embassy-stm32/src/pac/stm32l476je.rs index 1c16aaab..c2230994 100644 --- a/embassy-stm32/src/pac/stm32l476je.rs +++ b/embassy-stm32/src/pac/stm32l476je.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l476jg.rs b/embassy-stm32/src/pac/stm32l476jg.rs index 1c16aaab..c2230994 100644 --- a/embassy-stm32/src/pac/stm32l476jg.rs +++ b/embassy-stm32/src/pac/stm32l476jg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l476me.rs b/embassy-stm32/src/pac/stm32l476me.rs index 1c16aaab..c2230994 100644 --- a/embassy-stm32/src/pac/stm32l476me.rs +++ b/embassy-stm32/src/pac/stm32l476me.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l476mg.rs b/embassy-stm32/src/pac/stm32l476mg.rs index 1c16aaab..c2230994 100644 --- a/embassy-stm32/src/pac/stm32l476mg.rs +++ b/embassy-stm32/src/pac/stm32l476mg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l476qe.rs b/embassy-stm32/src/pac/stm32l476qe.rs index 1c16aaab..c2230994 100644 --- a/embassy-stm32/src/pac/stm32l476qe.rs +++ b/embassy-stm32/src/pac/stm32l476qe.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l476qg.rs b/embassy-stm32/src/pac/stm32l476qg.rs index 1c16aaab..c2230994 100644 --- a/embassy-stm32/src/pac/stm32l476qg.rs +++ b/embassy-stm32/src/pac/stm32l476qg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l476rc.rs b/embassy-stm32/src/pac/stm32l476rc.rs index 1c16aaab..c2230994 100644 --- a/embassy-stm32/src/pac/stm32l476rc.rs +++ b/embassy-stm32/src/pac/stm32l476rc.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l476re.rs b/embassy-stm32/src/pac/stm32l476re.rs index 1c16aaab..c2230994 100644 --- a/embassy-stm32/src/pac/stm32l476re.rs +++ b/embassy-stm32/src/pac/stm32l476re.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l476rg.rs b/embassy-stm32/src/pac/stm32l476rg.rs index 1c16aaab..c2230994 100644 --- a/embassy-stm32/src/pac/stm32l476rg.rs +++ b/embassy-stm32/src/pac/stm32l476rg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l476vc.rs b/embassy-stm32/src/pac/stm32l476vc.rs index 1c16aaab..c2230994 100644 --- a/embassy-stm32/src/pac/stm32l476vc.rs +++ b/embassy-stm32/src/pac/stm32l476vc.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l476ve.rs b/embassy-stm32/src/pac/stm32l476ve.rs index 1c16aaab..c2230994 100644 --- a/embassy-stm32/src/pac/stm32l476ve.rs +++ b/embassy-stm32/src/pac/stm32l476ve.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l476vg.rs b/embassy-stm32/src/pac/stm32l476vg.rs index 1c16aaab..c2230994 100644 --- a/embassy-stm32/src/pac/stm32l476vg.rs +++ b/embassy-stm32/src/pac/stm32l476vg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l476ze.rs b/embassy-stm32/src/pac/stm32l476ze.rs index 1c16aaab..c2230994 100644 --- a/embassy-stm32/src/pac/stm32l476ze.rs +++ b/embassy-stm32/src/pac/stm32l476ze.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l476zg.rs b/embassy-stm32/src/pac/stm32l476zg.rs index 1c16aaab..c2230994 100644 --- a/embassy-stm32/src/pac/stm32l476zg.rs +++ b/embassy-stm32/src/pac/stm32l476zg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l485jc.rs b/embassy-stm32/src/pac/stm32l485jc.rs index c5fb8087..bab45b91 100644 --- a/embassy-stm32/src/pac/stm32l485jc.rs +++ b/embassy-stm32/src/pac/stm32l485jc.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l485je.rs b/embassy-stm32/src/pac/stm32l485je.rs index c5fb8087..bab45b91 100644 --- a/embassy-stm32/src/pac/stm32l485je.rs +++ b/embassy-stm32/src/pac/stm32l485je.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l486jg.rs b/embassy-stm32/src/pac/stm32l486jg.rs index d791c148..89067584 100644 --- a/embassy-stm32/src/pac/stm32l486jg.rs +++ b/embassy-stm32/src/pac/stm32l486jg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l486qg.rs b/embassy-stm32/src/pac/stm32l486qg.rs index d791c148..89067584 100644 --- a/embassy-stm32/src/pac/stm32l486qg.rs +++ b/embassy-stm32/src/pac/stm32l486qg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l486rg.rs b/embassy-stm32/src/pac/stm32l486rg.rs index d791c148..89067584 100644 --- a/embassy-stm32/src/pac/stm32l486rg.rs +++ b/embassy-stm32/src/pac/stm32l486rg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l486vg.rs b/embassy-stm32/src/pac/stm32l486vg.rs index d791c148..89067584 100644 --- a/embassy-stm32/src/pac/stm32l486vg.rs +++ b/embassy-stm32/src/pac/stm32l486vg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l486zg.rs b/embassy-stm32/src/pac/stm32l486zg.rs index d791c148..89067584 100644 --- a/embassy-stm32/src/pac/stm32l486zg.rs +++ b/embassy-stm32/src/pac/stm32l486zg.rs @@ -161,7 +161,7 @@ impl_gpio_pin!(PH13, 7, 13, EXTI13); impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496ae.rs b/embassy-stm32/src/pac/stm32l496ae.rs index 22dc6767..4f15b5bf 100644 --- a/embassy-stm32/src/pac/stm32l496ae.rs +++ b/embassy-stm32/src/pac/stm32l496ae.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l496ag.rs b/embassy-stm32/src/pac/stm32l496ag.rs index 22dc6767..4f15b5bf 100644 --- a/embassy-stm32/src/pac/stm32l496ag.rs +++ b/embassy-stm32/src/pac/stm32l496ag.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l496qe.rs b/embassy-stm32/src/pac/stm32l496qe.rs index 22dc6767..4f15b5bf 100644 --- a/embassy-stm32/src/pac/stm32l496qe.rs +++ b/embassy-stm32/src/pac/stm32l496qe.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l496qg.rs b/embassy-stm32/src/pac/stm32l496qg.rs index 22dc6767..4f15b5bf 100644 --- a/embassy-stm32/src/pac/stm32l496qg.rs +++ b/embassy-stm32/src/pac/stm32l496qg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l496re.rs b/embassy-stm32/src/pac/stm32l496re.rs index 22dc6767..4f15b5bf 100644 --- a/embassy-stm32/src/pac/stm32l496re.rs +++ b/embassy-stm32/src/pac/stm32l496re.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l496rg.rs b/embassy-stm32/src/pac/stm32l496rg.rs index 22dc6767..4f15b5bf 100644 --- a/embassy-stm32/src/pac/stm32l496rg.rs +++ b/embassy-stm32/src/pac/stm32l496rg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l496ve.rs b/embassy-stm32/src/pac/stm32l496ve.rs index 22dc6767..4f15b5bf 100644 --- a/embassy-stm32/src/pac/stm32l496ve.rs +++ b/embassy-stm32/src/pac/stm32l496ve.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l496vg.rs b/embassy-stm32/src/pac/stm32l496vg.rs index 22dc6767..4f15b5bf 100644 --- a/embassy-stm32/src/pac/stm32l496vg.rs +++ b/embassy-stm32/src/pac/stm32l496vg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l496wg.rs b/embassy-stm32/src/pac/stm32l496wg.rs index 22dc6767..4f15b5bf 100644 --- a/embassy-stm32/src/pac/stm32l496wg.rs +++ b/embassy-stm32/src/pac/stm32l496wg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l496ze.rs b/embassy-stm32/src/pac/stm32l496ze.rs index 22dc6767..4f15b5bf 100644 --- a/embassy-stm32/src/pac/stm32l496ze.rs +++ b/embassy-stm32/src/pac/stm32l496ze.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l496zg.rs b/embassy-stm32/src/pac/stm32l496zg.rs index 22dc6767..4f15b5bf 100644 --- a/embassy-stm32/src/pac/stm32l496zg.rs +++ b/embassy-stm32/src/pac/stm32l496zg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4a6ag.rs b/embassy-stm32/src/pac/stm32l4a6ag.rs index 3b8c1f09..7384744e 100644 --- a/embassy-stm32/src/pac/stm32l4a6ag.rs +++ b/embassy-stm32/src/pac/stm32l4a6ag.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4a6qg.rs b/embassy-stm32/src/pac/stm32l4a6qg.rs index 3b8c1f09..7384744e 100644 --- a/embassy-stm32/src/pac/stm32l4a6qg.rs +++ b/embassy-stm32/src/pac/stm32l4a6qg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4a6rg.rs b/embassy-stm32/src/pac/stm32l4a6rg.rs index 3b8c1f09..7384744e 100644 --- a/embassy-stm32/src/pac/stm32l4a6rg.rs +++ b/embassy-stm32/src/pac/stm32l4a6rg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4a6vg.rs b/embassy-stm32/src/pac/stm32l4a6vg.rs index 3b8c1f09..7384744e 100644 --- a/embassy-stm32/src/pac/stm32l4a6vg.rs +++ b/embassy-stm32/src/pac/stm32l4a6vg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4a6zg.rs b/embassy-stm32/src/pac/stm32l4a6zg.rs index 3b8c1f09..7384744e 100644 --- a/embassy-stm32/src/pac/stm32l4a6zg.rs +++ b/embassy-stm32/src/pac/stm32l4a6zg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4p5ae.rs b/embassy-stm32/src/pac/stm32l4p5ae.rs index c3627b89..98ec9830 100644 --- a/embassy-stm32/src/pac/stm32l4p5ae.rs +++ b/embassy-stm32/src/pac/stm32l4p5ae.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4p5ag.rs b/embassy-stm32/src/pac/stm32l4p5ag.rs index c3627b89..98ec9830 100644 --- a/embassy-stm32/src/pac/stm32l4p5ag.rs +++ b/embassy-stm32/src/pac/stm32l4p5ag.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4p5ce.rs b/embassy-stm32/src/pac/stm32l4p5ce.rs index c3627b89..98ec9830 100644 --- a/embassy-stm32/src/pac/stm32l4p5ce.rs +++ b/embassy-stm32/src/pac/stm32l4p5ce.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4p5cg.rs b/embassy-stm32/src/pac/stm32l4p5cg.rs index c3627b89..98ec9830 100644 --- a/embassy-stm32/src/pac/stm32l4p5cg.rs +++ b/embassy-stm32/src/pac/stm32l4p5cg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4p5qe.rs b/embassy-stm32/src/pac/stm32l4p5qe.rs index c3627b89..98ec9830 100644 --- a/embassy-stm32/src/pac/stm32l4p5qe.rs +++ b/embassy-stm32/src/pac/stm32l4p5qe.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4p5qg.rs b/embassy-stm32/src/pac/stm32l4p5qg.rs index c3627b89..98ec9830 100644 --- a/embassy-stm32/src/pac/stm32l4p5qg.rs +++ b/embassy-stm32/src/pac/stm32l4p5qg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4p5re.rs b/embassy-stm32/src/pac/stm32l4p5re.rs index c3627b89..98ec9830 100644 --- a/embassy-stm32/src/pac/stm32l4p5re.rs +++ b/embassy-stm32/src/pac/stm32l4p5re.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4p5rg.rs b/embassy-stm32/src/pac/stm32l4p5rg.rs index c3627b89..98ec9830 100644 --- a/embassy-stm32/src/pac/stm32l4p5rg.rs +++ b/embassy-stm32/src/pac/stm32l4p5rg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4p5ve.rs b/embassy-stm32/src/pac/stm32l4p5ve.rs index c3627b89..98ec9830 100644 --- a/embassy-stm32/src/pac/stm32l4p5ve.rs +++ b/embassy-stm32/src/pac/stm32l4p5ve.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4p5vg.rs b/embassy-stm32/src/pac/stm32l4p5vg.rs index c3627b89..98ec9830 100644 --- a/embassy-stm32/src/pac/stm32l4p5vg.rs +++ b/embassy-stm32/src/pac/stm32l4p5vg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4p5ze.rs b/embassy-stm32/src/pac/stm32l4p5ze.rs index c3627b89..98ec9830 100644 --- a/embassy-stm32/src/pac/stm32l4p5ze.rs +++ b/embassy-stm32/src/pac/stm32l4p5ze.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4p5zg.rs b/embassy-stm32/src/pac/stm32l4p5zg.rs index c3627b89..98ec9830 100644 --- a/embassy-stm32/src/pac/stm32l4p5zg.rs +++ b/embassy-stm32/src/pac/stm32l4p5zg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4q5ag.rs b/embassy-stm32/src/pac/stm32l4q5ag.rs index af7690f9..f7ea12de 100644 --- a/embassy-stm32/src/pac/stm32l4q5ag.rs +++ b/embassy-stm32/src/pac/stm32l4q5ag.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4q5cg.rs b/embassy-stm32/src/pac/stm32l4q5cg.rs index af7690f9..f7ea12de 100644 --- a/embassy-stm32/src/pac/stm32l4q5cg.rs +++ b/embassy-stm32/src/pac/stm32l4q5cg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4q5qg.rs b/embassy-stm32/src/pac/stm32l4q5qg.rs index af7690f9..f7ea12de 100644 --- a/embassy-stm32/src/pac/stm32l4q5qg.rs +++ b/embassy-stm32/src/pac/stm32l4q5qg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4q5rg.rs b/embassy-stm32/src/pac/stm32l4q5rg.rs index af7690f9..f7ea12de 100644 --- a/embassy-stm32/src/pac/stm32l4q5rg.rs +++ b/embassy-stm32/src/pac/stm32l4q5rg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4q5vg.rs b/embassy-stm32/src/pac/stm32l4q5vg.rs index af7690f9..f7ea12de 100644 --- a/embassy-stm32/src/pac/stm32l4q5vg.rs +++ b/embassy-stm32/src/pac/stm32l4q5vg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4q5zg.rs b/embassy-stm32/src/pac/stm32l4q5zg.rs index af7690f9..f7ea12de 100644 --- a/embassy-stm32/src/pac/stm32l4q5zg.rs +++ b/embassy-stm32/src/pac/stm32l4q5zg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r5ag.rs b/embassy-stm32/src/pac/stm32l4r5ag.rs index 9f7c5e88..0fad849d 100644 --- a/embassy-stm32/src/pac/stm32l4r5ag.rs +++ b/embassy-stm32/src/pac/stm32l4r5ag.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r5ai.rs b/embassy-stm32/src/pac/stm32l4r5ai.rs index 9f7c5e88..0fad849d 100644 --- a/embassy-stm32/src/pac/stm32l4r5ai.rs +++ b/embassy-stm32/src/pac/stm32l4r5ai.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r5qg.rs b/embassy-stm32/src/pac/stm32l4r5qg.rs index 9f7c5e88..0fad849d 100644 --- a/embassy-stm32/src/pac/stm32l4r5qg.rs +++ b/embassy-stm32/src/pac/stm32l4r5qg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r5qi.rs b/embassy-stm32/src/pac/stm32l4r5qi.rs index 9f7c5e88..0fad849d 100644 --- a/embassy-stm32/src/pac/stm32l4r5qi.rs +++ b/embassy-stm32/src/pac/stm32l4r5qi.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r5vg.rs b/embassy-stm32/src/pac/stm32l4r5vg.rs index 9f7c5e88..0fad849d 100644 --- a/embassy-stm32/src/pac/stm32l4r5vg.rs +++ b/embassy-stm32/src/pac/stm32l4r5vg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r5vi.rs b/embassy-stm32/src/pac/stm32l4r5vi.rs index 9f7c5e88..0fad849d 100644 --- a/embassy-stm32/src/pac/stm32l4r5vi.rs +++ b/embassy-stm32/src/pac/stm32l4r5vi.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r5zg.rs b/embassy-stm32/src/pac/stm32l4r5zg.rs index 9f7c5e88..0fad849d 100644 --- a/embassy-stm32/src/pac/stm32l4r5zg.rs +++ b/embassy-stm32/src/pac/stm32l4r5zg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r5zi.rs b/embassy-stm32/src/pac/stm32l4r5zi.rs index 9f7c5e88..0fad849d 100644 --- a/embassy-stm32/src/pac/stm32l4r5zi.rs +++ b/embassy-stm32/src/pac/stm32l4r5zi.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r7ai.rs b/embassy-stm32/src/pac/stm32l4r7ai.rs index ae6fb4c4..4bc279c4 100644 --- a/embassy-stm32/src/pac/stm32l4r7ai.rs +++ b/embassy-stm32/src/pac/stm32l4r7ai.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r7vi.rs b/embassy-stm32/src/pac/stm32l4r7vi.rs index ae6fb4c4..4bc279c4 100644 --- a/embassy-stm32/src/pac/stm32l4r7vi.rs +++ b/embassy-stm32/src/pac/stm32l4r7vi.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r7zi.rs b/embassy-stm32/src/pac/stm32l4r7zi.rs index ae6fb4c4..4bc279c4 100644 --- a/embassy-stm32/src/pac/stm32l4r7zi.rs +++ b/embassy-stm32/src/pac/stm32l4r7zi.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r9ag.rs b/embassy-stm32/src/pac/stm32l4r9ag.rs index 6bf045d2..2a0a52d4 100644 --- a/embassy-stm32/src/pac/stm32l4r9ag.rs +++ b/embassy-stm32/src/pac/stm32l4r9ag.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r9ai.rs b/embassy-stm32/src/pac/stm32l4r9ai.rs index 6bf045d2..2a0a52d4 100644 --- a/embassy-stm32/src/pac/stm32l4r9ai.rs +++ b/embassy-stm32/src/pac/stm32l4r9ai.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r9vg.rs b/embassy-stm32/src/pac/stm32l4r9vg.rs index 6bf045d2..2a0a52d4 100644 --- a/embassy-stm32/src/pac/stm32l4r9vg.rs +++ b/embassy-stm32/src/pac/stm32l4r9vg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r9vi.rs b/embassy-stm32/src/pac/stm32l4r9vi.rs index 6bf045d2..2a0a52d4 100644 --- a/embassy-stm32/src/pac/stm32l4r9vi.rs +++ b/embassy-stm32/src/pac/stm32l4r9vi.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r9zg.rs b/embassy-stm32/src/pac/stm32l4r9zg.rs index 6bf045d2..2a0a52d4 100644 --- a/embassy-stm32/src/pac/stm32l4r9zg.rs +++ b/embassy-stm32/src/pac/stm32l4r9zg.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4r9zi.rs b/embassy-stm32/src/pac/stm32l4r9zi.rs index 6bf045d2..2a0a52d4 100644 --- a/embassy-stm32/src/pac/stm32l4r9zi.rs +++ b/embassy-stm32/src/pac/stm32l4r9zi.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4s5ai.rs b/embassy-stm32/src/pac/stm32l4s5ai.rs index ef21a80f..81671a5d 100644 --- a/embassy-stm32/src/pac/stm32l4s5ai.rs +++ b/embassy-stm32/src/pac/stm32l4s5ai.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4s5qi.rs b/embassy-stm32/src/pac/stm32l4s5qi.rs index ef21a80f..81671a5d 100644 --- a/embassy-stm32/src/pac/stm32l4s5qi.rs +++ b/embassy-stm32/src/pac/stm32l4s5qi.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4s5vi.rs b/embassy-stm32/src/pac/stm32l4s5vi.rs index ef21a80f..81671a5d 100644 --- a/embassy-stm32/src/pac/stm32l4s5vi.rs +++ b/embassy-stm32/src/pac/stm32l4s5vi.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4s5zi.rs b/embassy-stm32/src/pac/stm32l4s5zi.rs index ef21a80f..81671a5d 100644 --- a/embassy-stm32/src/pac/stm32l4s5zi.rs +++ b/embassy-stm32/src/pac/stm32l4s5zi.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4s7ai.rs b/embassy-stm32/src/pac/stm32l4s7ai.rs index 6c527607..402b2cad 100644 --- a/embassy-stm32/src/pac/stm32l4s7ai.rs +++ b/embassy-stm32/src/pac/stm32l4s7ai.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4s7vi.rs b/embassy-stm32/src/pac/stm32l4s7vi.rs index 6c527607..402b2cad 100644 --- a/embassy-stm32/src/pac/stm32l4s7vi.rs +++ b/embassy-stm32/src/pac/stm32l4s7vi.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4s7zi.rs b/embassy-stm32/src/pac/stm32l4s7zi.rs index 6c527607..402b2cad 100644 --- a/embassy-stm32/src/pac/stm32l4s7zi.rs +++ b/embassy-stm32/src/pac/stm32l4s7zi.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4s9ai.rs b/embassy-stm32/src/pac/stm32l4s9ai.rs index 3694825e..ccabd113 100644 --- a/embassy-stm32/src/pac/stm32l4s9ai.rs +++ b/embassy-stm32/src/pac/stm32l4s9ai.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4s9vi.rs b/embassy-stm32/src/pac/stm32l4s9vi.rs index 3694825e..ccabd113 100644 --- a/embassy-stm32/src/pac/stm32l4s9vi.rs +++ b/embassy-stm32/src/pac/stm32l4s9vi.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/pac/stm32l4s9zi.rs b/embassy-stm32/src/pac/stm32l4s9zi.rs index 3694825e..ccabd113 100644 --- a/embassy-stm32/src/pac/stm32l4s9zi.rs +++ b/embassy-stm32/src/pac/stm32l4s9zi.rs @@ -178,7 +178,7 @@ impl_gpio_pin!(PI13, 8, 13, EXTI13); impl_gpio_pin!(PI14, 8, 14, EXTI14); impl_gpio_pin!(PI15, 8, 15, EXTI15); pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); -impl_rng!(RNG); +impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); impl_spi_pin!(SPI1, Sck, PA1, 5); diff --git a/embassy-stm32/src/rng.rs b/embassy-stm32/src/rng.rs index af527cd5..672a8f62 100644 --- a/embassy-stm32/src/rng.rs +++ b/embassy-stm32/src/rng.rs @@ -9,19 +9,10 @@ use embassy_extras::unborrow; use futures::future::poll_fn; use rand_core::{CryptoRng, RngCore}; -use crate::interrupt; +//Guse crate::interrupt; use crate::pac; -static RNG_WAKER: AtomicWaker = AtomicWaker::new(); - -#[interrupt] -unsafe fn RNG() { - let bits = crate::pac::RNG.sr().read(); - if bits.drdy() || bits.seis() || bits.ceis() { - crate::pac::RNG.cr().write(|reg| reg.set_ie(false)); - RNG_WAKER.wake(); - } -} +pub(crate) static RNG_WAKER: AtomicWaker = AtomicWaker::new(); pub struct Random { inner: T, @@ -146,7 +137,7 @@ pub(crate) mod sealed { pub trait Instance: sealed::Instance {} macro_rules! impl_rng { - ($inst:ident) => { + ($inst:ident, $irq:ident) => { impl crate::rng::sealed::Instance for peripherals::RNG { fn regs() -> crate::pac::chip::rng::Rng { crate::pac::RNG @@ -154,5 +145,14 @@ macro_rules! impl_rng { } impl crate::rng::Instance for peripherals::RNG {} + + #[$crate::interrupt] + unsafe fn $irq() { + let bits = $crate::pac::RNG.sr().read(); + if bits.drdy() || bits.seis() || bits.ceis() { + $crate::pac::RNG.cr().write(|reg| reg.set_ie(false)); + $crate::rng::RNG_WAKER.wake(); + } + } }; } diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs new file mode 100644 index 00000000..27f1be93 --- /dev/null +++ b/embassy-stm32/src/spi/mod.rs @@ -0,0 +1,34 @@ +#![macro_use] + +#[cfg_attr(feature = "_spi_v1", path = "spi_v1.rs")] +#[cfg_attr(feature = "_spi_v2", path = "spi_v2.rs")] +mod spi; + +pub use spi::*; + +// TODO move upwards in the tree +pub enum ByteOrder { + LsbFirst, + MsbFirst, +} + +#[derive(Copy, Clone, PartialOrd, PartialEq)] +enum WordSize { + EightBit, + SixteenBit, +} + +#[non_exhaustive] +pub struct Config { + pub mode: Mode, + pub byte_order: ByteOrder, +} + +impl Default for Config { + fn default() -> Self { + Self { + mode: MODE_0, + byte_order: ByteOrder::MsbFirst, + } + } +} diff --git a/embassy-stm32/src/spi/spi_v1.rs b/embassy-stm32/src/spi/spi_v1.rs new file mode 100644 index 00000000..3ef096e4 --- /dev/null +++ b/embassy-stm32/src/spi/spi_v1.rs @@ -0,0 +1,364 @@ +#![macro_use] + +pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; +use core::marker::PhantomData; +use embassy::interrupt::Interrupt; +use embedded_hal::blocking::spi::{Write, Transfer}; +use embassy::util::Unborrow; +use embassy_extras::{impl_unborrow, unborrow}; +use crate::gpio::{Pin, AnyPin}; +use crate::pac::gpio::vals::{Afr, Moder}; +use crate::pac::spi; +use crate::pac::gpio::Gpio; +use crate::time::Hertz; +use crate::spi::{WordSize, Config, ByteOrder}; + +impl WordSize { + fn dff(&self) -> spi::vals::Dff { + match self { + WordSize::EightBit => spi::vals::Dff::EIGHTBIT, + WordSize::SixteenBit => spi::vals::Dff::SIXTEENBIT, + } + } +} + +pub struct Spi<'d, T: Instance> { + peri: T, + sck: AnyPin, + mosi: AnyPin, + miso: AnyPin, + current_word_size: WordSize, + phantom: PhantomData<&'d mut T>, +} + +impl<'d, T: Instance> Spi<'d, T> { + pub fn new(pclk: Hertz, + peri: impl Unborrow + 'd, + sck: impl Unborrow>, + mosi: impl Unborrow>, + miso: impl Unborrow>, + freq: F, + config: Config, + ) -> Self + where + F: Into + { + unborrow!(peri); + unborrow!(sck, mosi, miso); + + unsafe { + Self::configure_pin(sck.block(), sck.pin() as _, sck.af()); + Self::configure_pin(mosi.block(), mosi.pin() as _, mosi.af()); + Self::configure_pin(miso.block(), miso.pin() as _, miso.af()); + } + + let sck = sck.degrade(); + let mosi = mosi.degrade(); + let miso = miso.degrade(); + + unsafe { + T::regs().cr2() + .write(|w| { + w.set_ssoe(false); + }); + } + + let br = Self::compute_baud_rate(pclk, freq.into()); + + unsafe { + T::regs().cr1().write(|w| { + w.set_cpha( + match config.mode.phase == Phase::CaptureOnSecondTransition { + true => spi::vals::Cpha::SECONDEDGE, + false => spi::vals::Cpha::FIRSTEDGE, + } + ); + w.set_cpol(match config.mode.polarity == Polarity::IdleHigh { + true => spi::vals::Cpol::IDLEHIGH, + false => spi::vals::Cpol::IDLELOW, + }); + + w.set_mstr(spi::vals::Mstr::MASTER); + w.set_br(spi::vals::Br(br)); + w.set_spe(true); + w.set_lsbfirst( + match config.byte_order { + ByteOrder::LsbFirst => spi::vals::Lsbfirst::LSBFIRST, + ByteOrder::MsbFirst => spi::vals::Lsbfirst::MSBFIRST, + } + ); + w.set_ssi(true); + w.set_ssm(true); + w.set_crcen(false); + w.set_bidimode(spi::vals::Bidimode::UNIDIRECTIONAL); + w.set_dff( WordSize::EightBit.dff() ) + }); + } + + Self { + peri, + sck, + mosi, + miso, + current_word_size: WordSize::EightBit, + phantom: PhantomData, + } + } + + unsafe fn configure_pin(block: Gpio, pin: usize, af_num: u8) { + let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) }; + block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE)); + block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num))); + } + + unsafe fn unconfigure_pin(block: Gpio, pin: usize) { + let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) }; + block.moder().modify(|w| w.set_moder(pin, Moder::ANALOG)); + } + + fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 { + match clocks.0 / freq.0 { + 0 => unreachable!(), + 1..=2 => 0b000, + 3..=5 => 0b001, + 6..=11 => 0b010, + 12..=23 => 0b011, + 24..=39 => 0b100, + 40..=95 => 0b101, + 96..=191 => 0b110, + _ => 0b111, + } + } + + fn set_word_size(&mut self, word_size: WordSize) { + if self.current_word_size == word_size { + return + } + unsafe { + T::regs().cr1().modify( |reg| { + reg.set_spe(false); + reg.set_dff( word_size.dff() ) + }); + T::regs().cr1().modify( |reg| { + reg.set_spe(true); + }); + self.current_word_size = word_size; + } + } +} + +impl<'d, T: Instance> Drop for Spi<'d, T> { + fn drop(&mut self) { + unsafe { + Self::unconfigure_pin(self.sck.block(), self.sck.pin() as _); + Self::unconfigure_pin(self.mosi.block(), self.mosi.pin() as _); + Self::unconfigure_pin(self.miso.block(), self.miso.pin() as _); + } + } +} + +pub enum Error { + Framing, + Crc, + Overrun, +} + +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { + type Error = Error; + + fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> { + self.set_word_size(WordSize::EightBit); + let regs = T::regs(); + + for word in words.iter() { + while unsafe { !regs.sr().read().txe() } { + // spin + } + unsafe { + regs.dr().write(|reg| reg.0 = *word as u32); + } + loop { + let sr = unsafe { regs.sr().read() }; + if sr.fre() { + return Err(Error::Framing); + } + if sr.ovr() { + return Err(Error::Overrun); + } + if sr.crcerr() { + return Err(Error::Crc); + } + if !sr.txe() { + // loop waiting for TXE + } + } + } + + Ok(()) + } +} + +impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { + type Error = Error; + + fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> { + self.set_word_size(WordSize::EightBit); + let regs = T::regs(); + + for word in words.iter_mut() { + while unsafe { !regs.sr().read().txe() } { + // spin + } + unsafe { + regs.dr().write(|reg| reg.0 = *word as u32); + } + while unsafe { !regs.sr().read().rxne() } { + // spin waiting for inbound to shift in. + } + *word = unsafe { regs.dr().read().0 as u8 }; + let sr = unsafe { regs.sr().read() }; + if sr.fre() { + return Err(Error::Framing); + } + if sr.ovr() { + return Err(Error::Overrun); + } + if sr.crcerr() { + return Err(Error::Crc); + } + } + + Ok(words) + } +} + +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { + type Error = Error; + + fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> { + self.set_word_size(WordSize::SixteenBit); + let regs = T::regs(); + + for word in words.iter() { + while unsafe { !regs.sr().read().txe() } { + // spin + } + unsafe { + regs.dr().write(|reg| reg.0 = *word as u32); + } + loop { + let sr = unsafe { regs.sr().read() }; + if sr.fre() { + return Err(Error::Framing); + } + if sr.ovr() { + return Err(Error::Overrun); + } + if sr.crcerr() { + return Err(Error::Crc); + } + if !sr.txe() { + // loop waiting for TXE + } + } + } + + Ok(()) + } +} + +impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { + type Error = Error; + + fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> { + self.set_word_size(WordSize::SixteenBit); + let regs = T::regs(); + + for word in words.iter_mut() { + while unsafe { !regs.sr().read().txe() } { + // spin + } + unsafe { + regs.dr().write(|reg| reg.0 = *word as u32); + } + while unsafe { !regs.sr().read().rxne() } { + // spin waiting for inbound to shift in. + } + *word = unsafe { regs.dr().read().0 as u16 }; + let sr = unsafe { regs.sr().read() }; + if sr.fre() { + return Err(Error::Framing); + } + if sr.ovr() { + return Err(Error::Overrun); + } + if sr.crcerr() { + return Err(Error::Crc); + } + } + + Ok(words) + } +} + + +pub(crate) mod sealed { + use super::*; + use embassy::util::AtomicWaker; + + pub trait Instance { + fn regs() -> &'static spi::Spi; + } + + pub trait Sck: Pin { + const AF: u8; + fn af(&self) -> u8 { + Self::AF + } + } + + pub trait Mosi: Pin { + const AF: u8; + fn af(&self) -> u8 { + Self::AF + } + } + + pub trait Miso: Pin { + const AF: u8; + fn af(&self) -> u8 { + Self::AF + } + } +} + +pub trait Instance: sealed::Instance + 'static {} + +pub trait Sck: sealed::Sck + 'static {} + +pub trait Mosi: sealed::Mosi + 'static {} + +pub trait Miso: sealed::Miso + 'static {} + +macro_rules! impl_spi { + ($inst:ident, $clk:ident) => { + impl crate::spi::sealed::Instance for peripherals::$inst { + fn regs() -> &'static crate::pac::spi::Spi { + &crate::pac::$inst + } + } + + impl crate::spi::Instance for peripherals::$inst {} + }; +} + +macro_rules! impl_spi_pin { + ($inst:ident, $pin_func:ident, $pin:ident, $af:expr) => { + impl crate::spi::$pin_func for peripherals::$pin { + } + + impl crate::spi::sealed::$pin_func for peripherals::$pin { + const AF: u8 = $af; + } + } +} \ No newline at end of file diff --git a/embassy-stm32/src/spi.rs b/embassy-stm32/src/spi/spi_v2.rs similarity index 95% rename from embassy-stm32/src/spi.rs rename to embassy-stm32/src/spi/spi_v2.rs index 40944d74..48370c84 100644 --- a/embassy-stm32/src/spi.rs +++ b/embassy-stm32/src/spi/spi_v2.rs @@ -11,33 +11,7 @@ use crate::pac::gpio::vals::{Afr, Moder}; use crate::pac::spi; use crate::pac::gpio::Gpio; use crate::time::Hertz; -use term::terminfo::parm::Param::Words; - -#[non_exhaustive] -pub struct Config { - pub mode: Mode, - pub byte_order: ByteOrder, -} - -impl Default for Config { - fn default() -> Self { - Self { - mode: MODE_0, - byte_order: ByteOrder::MsbFirst, - } - } -} - -// TODO move upwards in the tree -pub enum ByteOrder { - LsbFirst, - MsbFirst, -} - -enum WordSize { - EightBit, - SixteenBit, -} +use crate::spi::{WordSize, Config, ByteOrder}; impl WordSize { fn ds(&self) -> spi::vals::Ds { @@ -125,7 +99,6 @@ impl<'d, T: Instance> Spi<'d, T> { w.set_crcen(false); w.set_bidimode(spi::vals::Bidimode::UNIDIRECTIONAL); }); - T::regs().cr2().write(|w| {}) } Self { From 2569d38ab4bce2d927fbdd07129311b04718df4f Mon Sep 17 00:00:00 2001 From: Bob McWhirter Date: Fri, 14 May 2021 10:11:43 -0400 Subject: [PATCH 7/8] Adjust pin-names to FooPin. Move common bits up to spi/mod.rs. Isolate the RNG interrupt in a sub-module to avoid conflict with the const. --- embassy-stm32/gen.py | 6 +- embassy-stm32/src/lib.rs | 2 + embassy-stm32/src/pac/regs.rs | 15974 ++++++++++++------------- embassy-stm32/src/pac/stm32f401cb.rs | 40 +- embassy-stm32/src/pac/stm32f401cc.rs | 40 +- embassy-stm32/src/pac/stm32f401cd.rs | 40 +- embassy-stm32/src/pac/stm32f401ce.rs | 40 +- embassy-stm32/src/pac/stm32f401rb.rs | 40 +- embassy-stm32/src/pac/stm32f401rc.rs | 40 +- embassy-stm32/src/pac/stm32f401rd.rs | 40 +- embassy-stm32/src/pac/stm32f401re.rs | 40 +- embassy-stm32/src/pac/stm32f401vb.rs | 52 +- embassy-stm32/src/pac/stm32f401vc.rs | 52 +- embassy-stm32/src/pac/stm32f401vd.rs | 52 +- embassy-stm32/src/pac/stm32f401ve.rs | 52 +- embassy-stm32/src/pac/stm32f405oe.rs | 42 +- embassy-stm32/src/pac/stm32f405og.rs | 42 +- embassy-stm32/src/pac/stm32f405rg.rs | 42 +- embassy-stm32/src/pac/stm32f405vg.rs | 42 +- embassy-stm32/src/pac/stm32f405zg.rs | 42 +- embassy-stm32/src/pac/stm32f407ie.rs | 42 +- embassy-stm32/src/pac/stm32f407ig.rs | 42 +- embassy-stm32/src/pac/stm32f407ve.rs | 42 +- embassy-stm32/src/pac/stm32f407vg.rs | 42 +- embassy-stm32/src/pac/stm32f407ze.rs | 42 +- embassy-stm32/src/pac/stm32f407zg.rs | 42 +- embassy-stm32/src/pac/stm32f411cc.rs | 82 +- embassy-stm32/src/pac/stm32f411ce.rs | 82 +- embassy-stm32/src/pac/stm32f411rc.rs | 82 +- embassy-stm32/src/pac/stm32f411re.rs | 82 +- embassy-stm32/src/pac/stm32f411vc.rs | 82 +- embassy-stm32/src/pac/stm32f411ve.rs | 82 +- embassy-stm32/src/pac/stm32f412ce.rs | 54 +- embassy-stm32/src/pac/stm32f412cg.rs | 54 +- embassy-stm32/src/pac/stm32f412re.rs | 58 +- embassy-stm32/src/pac/stm32f412rg.rs | 58 +- embassy-stm32/src/pac/stm32f412ve.rs | 82 +- embassy-stm32/src/pac/stm32f412vg.rs | 82 +- embassy-stm32/src/pac/stm32f412ze.rs | 82 +- embassy-stm32/src/pac/stm32f412zg.rs | 82 +- embassy-stm32/src/pac/stm32f413cg.rs | 88 +- embassy-stm32/src/pac/stm32f413ch.rs | 88 +- embassy-stm32/src/pac/stm32f413mg.rs | 88 +- embassy-stm32/src/pac/stm32f413mh.rs | 88 +- embassy-stm32/src/pac/stm32f413rg.rs | 88 +- embassy-stm32/src/pac/stm32f413rh.rs | 88 +- embassy-stm32/src/pac/stm32f413vg.rs | 88 +- embassy-stm32/src/pac/stm32f413vh.rs | 88 +- embassy-stm32/src/pac/stm32f413zg.rs | 88 +- embassy-stm32/src/pac/stm32f413zh.rs | 88 +- embassy-stm32/src/pac/stm32f415og.rs | 42 +- embassy-stm32/src/pac/stm32f415rg.rs | 42 +- embassy-stm32/src/pac/stm32f415vg.rs | 42 +- embassy-stm32/src/pac/stm32f415zg.rs | 42 +- embassy-stm32/src/pac/stm32f417ie.rs | 42 +- embassy-stm32/src/pac/stm32f417ig.rs | 42 +- embassy-stm32/src/pac/stm32f417ve.rs | 42 +- embassy-stm32/src/pac/stm32f417vg.rs | 42 +- embassy-stm32/src/pac/stm32f417ze.rs | 42 +- embassy-stm32/src/pac/stm32f417zg.rs | 42 +- embassy-stm32/src/pac/stm32f423ch.rs | 88 +- embassy-stm32/src/pac/stm32f423mh.rs | 88 +- embassy-stm32/src/pac/stm32f423rh.rs | 88 +- embassy-stm32/src/pac/stm32f423vh.rs | 88 +- embassy-stm32/src/pac/stm32f423zh.rs | 88 +- embassy-stm32/src/pac/stm32f427ag.rs | 70 +- embassy-stm32/src/pac/stm32f427ai.rs | 70 +- embassy-stm32/src/pac/stm32f427ig.rs | 76 +- embassy-stm32/src/pac/stm32f427ii.rs | 76 +- embassy-stm32/src/pac/stm32f427vg.rs | 58 +- embassy-stm32/src/pac/stm32f427vi.rs | 58 +- embassy-stm32/src/pac/stm32f427zg.rs | 76 +- embassy-stm32/src/pac/stm32f427zi.rs | 76 +- embassy-stm32/src/pac/stm32f429ag.rs | 70 +- embassy-stm32/src/pac/stm32f429ai.rs | 70 +- embassy-stm32/src/pac/stm32f429be.rs | 76 +- embassy-stm32/src/pac/stm32f429bg.rs | 76 +- embassy-stm32/src/pac/stm32f429bi.rs | 76 +- embassy-stm32/src/pac/stm32f429ie.rs | 76 +- embassy-stm32/src/pac/stm32f429ig.rs | 76 +- embassy-stm32/src/pac/stm32f429ii.rs | 76 +- embassy-stm32/src/pac/stm32f429ne.rs | 76 +- embassy-stm32/src/pac/stm32f429ng.rs | 76 +- embassy-stm32/src/pac/stm32f429ni.rs | 76 +- embassy-stm32/src/pac/stm32f429ve.rs | 58 +- embassy-stm32/src/pac/stm32f429vg.rs | 58 +- embassy-stm32/src/pac/stm32f429vi.rs | 58 +- embassy-stm32/src/pac/stm32f429ze.rs | 76 +- embassy-stm32/src/pac/stm32f429zg.rs | 76 +- embassy-stm32/src/pac/stm32f429zi.rs | 76 +- embassy-stm32/src/pac/stm32f437ai.rs | 70 +- embassy-stm32/src/pac/stm32f437ig.rs | 76 +- embassy-stm32/src/pac/stm32f437ii.rs | 76 +- embassy-stm32/src/pac/stm32f437vg.rs | 58 +- embassy-stm32/src/pac/stm32f437vi.rs | 58 +- embassy-stm32/src/pac/stm32f437zg.rs | 76 +- embassy-stm32/src/pac/stm32f437zi.rs | 76 +- embassy-stm32/src/pac/stm32f439ai.rs | 70 +- embassy-stm32/src/pac/stm32f439bg.rs | 76 +- embassy-stm32/src/pac/stm32f439bi.rs | 76 +- embassy-stm32/src/pac/stm32f439ig.rs | 76 +- embassy-stm32/src/pac/stm32f439ii.rs | 76 +- embassy-stm32/src/pac/stm32f439ng.rs | 76 +- embassy-stm32/src/pac/stm32f439ni.rs | 76 +- embassy-stm32/src/pac/stm32f439vg.rs | 58 +- embassy-stm32/src/pac/stm32f439vi.rs | 58 +- embassy-stm32/src/pac/stm32f439zg.rs | 76 +- embassy-stm32/src/pac/stm32f439zi.rs | 76 +- embassy-stm32/src/pac/stm32f446mc.rs | 74 +- embassy-stm32/src/pac/stm32f446me.rs | 74 +- embassy-stm32/src/pac/stm32f446rc.rs | 54 +- embassy-stm32/src/pac/stm32f446re.rs | 54 +- embassy-stm32/src/pac/stm32f446vc.rs | 74 +- embassy-stm32/src/pac/stm32f446ve.rs | 74 +- embassy-stm32/src/pac/stm32f446zc.rs | 74 +- embassy-stm32/src/pac/stm32f446ze.rs | 74 +- embassy-stm32/src/pac/stm32l431cb.rs | 54 +- embassy-stm32/src/pac/stm32l431cc.rs | 54 +- embassy-stm32/src/pac/stm32l431kb.rs | 36 +- embassy-stm32/src/pac/stm32l431kc.rs | 36 +- embassy-stm32/src/pac/stm32l431rb.rs | 54 +- embassy-stm32/src/pac/stm32l431rc.rs | 54 +- embassy-stm32/src/pac/stm32l431vc.rs | 54 +- embassy-stm32/src/pac/stm32l432kb.rs | 30 +- embassy-stm32/src/pac/stm32l432kc.rs | 30 +- embassy-stm32/src/pac/stm32l433cb.rs | 54 +- embassy-stm32/src/pac/stm32l433cc.rs | 54 +- embassy-stm32/src/pac/stm32l433rb.rs | 54 +- embassy-stm32/src/pac/stm32l433rc.rs | 54 +- embassy-stm32/src/pac/stm32l433vc.rs | 54 +- embassy-stm32/src/pac/stm32l442kc.rs | 30 +- embassy-stm32/src/pac/stm32l443cc.rs | 54 +- embassy-stm32/src/pac/stm32l443rc.rs | 54 +- embassy-stm32/src/pac/stm32l443vc.rs | 54 +- embassy-stm32/src/pac/stm32l496ae.rs | 78 +- embassy-stm32/src/pac/stm32l496ag.rs | 78 +- embassy-stm32/src/pac/stm32l496qe.rs | 78 +- embassy-stm32/src/pac/stm32l496qg.rs | 78 +- embassy-stm32/src/pac/stm32l496re.rs | 78 +- embassy-stm32/src/pac/stm32l496rg.rs | 78 +- embassy-stm32/src/pac/stm32l496ve.rs | 78 +- embassy-stm32/src/pac/stm32l496vg.rs | 78 +- embassy-stm32/src/pac/stm32l496wg.rs | 78 +- embassy-stm32/src/pac/stm32l496ze.rs | 78 +- embassy-stm32/src/pac/stm32l496zg.rs | 78 +- embassy-stm32/src/pac/stm32l4a6ag.rs | 78 +- embassy-stm32/src/pac/stm32l4a6qg.rs | 78 +- embassy-stm32/src/pac/stm32l4a6rg.rs | 78 +- embassy-stm32/src/pac/stm32l4a6vg.rs | 78 +- embassy-stm32/src/pac/stm32l4a6zg.rs | 78 +- embassy-stm32/src/pac/stm32l4p5ae.rs | 80 +- embassy-stm32/src/pac/stm32l4p5ag.rs | 80 +- embassy-stm32/src/pac/stm32l4p5ce.rs | 80 +- embassy-stm32/src/pac/stm32l4p5cg.rs | 80 +- embassy-stm32/src/pac/stm32l4p5qe.rs | 80 +- embassy-stm32/src/pac/stm32l4p5qg.rs | 80 +- embassy-stm32/src/pac/stm32l4p5re.rs | 80 +- embassy-stm32/src/pac/stm32l4p5rg.rs | 80 +- embassy-stm32/src/pac/stm32l4p5ve.rs | 80 +- embassy-stm32/src/pac/stm32l4p5vg.rs | 80 +- embassy-stm32/src/pac/stm32l4p5ze.rs | 80 +- embassy-stm32/src/pac/stm32l4p5zg.rs | 80 +- embassy-stm32/src/pac/stm32l4q5ag.rs | 80 +- embassy-stm32/src/pac/stm32l4q5cg.rs | 80 +- embassy-stm32/src/pac/stm32l4q5qg.rs | 80 +- embassy-stm32/src/pac/stm32l4q5rg.rs | 80 +- embassy-stm32/src/pac/stm32l4q5vg.rs | 80 +- embassy-stm32/src/pac/stm32l4q5zg.rs | 80 +- embassy-stm32/src/pac/stm32l4r5ag.rs | 80 +- embassy-stm32/src/pac/stm32l4r5ai.rs | 80 +- embassy-stm32/src/pac/stm32l4r5qg.rs | 80 +- embassy-stm32/src/pac/stm32l4r5qi.rs | 80 +- embassy-stm32/src/pac/stm32l4r5vg.rs | 80 +- embassy-stm32/src/pac/stm32l4r5vi.rs | 80 +- embassy-stm32/src/pac/stm32l4r5zg.rs | 80 +- embassy-stm32/src/pac/stm32l4r5zi.rs | 80 +- embassy-stm32/src/pac/stm32l4r7ai.rs | 80 +- embassy-stm32/src/pac/stm32l4r7vi.rs | 80 +- embassy-stm32/src/pac/stm32l4r7zi.rs | 80 +- embassy-stm32/src/pac/stm32l4r9ag.rs | 80 +- embassy-stm32/src/pac/stm32l4r9ai.rs | 80 +- embassy-stm32/src/pac/stm32l4r9vg.rs | 80 +- embassy-stm32/src/pac/stm32l4r9vi.rs | 80 +- embassy-stm32/src/pac/stm32l4r9zg.rs | 80 +- embassy-stm32/src/pac/stm32l4r9zi.rs | 80 +- embassy-stm32/src/pac/stm32l4s5ai.rs | 80 +- embassy-stm32/src/pac/stm32l4s5qi.rs | 80 +- embassy-stm32/src/pac/stm32l4s5vi.rs | 80 +- embassy-stm32/src/pac/stm32l4s5zi.rs | 80 +- embassy-stm32/src/pac/stm32l4s7ai.rs | 80 +- embassy-stm32/src/pac/stm32l4s7vi.rs | 80 +- embassy-stm32/src/pac/stm32l4s7zi.rs | 80 +- embassy-stm32/src/pac/stm32l4s9ai.rs | 80 +- embassy-stm32/src/pac/stm32l4s9vi.rs | 80 +- embassy-stm32/src/pac/stm32l4s9zi.rs | 80 +- embassy-stm32/src/rng.rs | 29 +- embassy-stm32/src/spi/mod.rs | 67 + embassy-stm32/src/spi/spi_v1.rs | 137 +- embassy-stm32/src/spi/spi_v2.rs | 131 +- embassy-stm32/src/time.rs | 3 +- embassy-stm32/stm32-data | 2 +- 201 files changed, 14694 insertions(+), 14765 deletions(-) diff --git a/embassy-stm32/gen.py b/embassy-stm32/gen.py index 04a2f333..056d66ec 100644 --- a/embassy-stm32/gen.py +++ b/embassy-stm32/gen.py @@ -124,11 +124,11 @@ for chip in chips.values(): for pin, funcs in af.items(): if pin in pins: if func := funcs.get(f'{name}_SCK'): - f.write(f'impl_spi_pin!({name}, Sck, {pin}, {func});') + f.write(f'impl_spi_pin!({name}, SckPin, {pin}, {func});') if func := funcs.get(f'{name}_MOSI'): - f.write(f'impl_spi_pin!({name}, Mosi, {pin}, {func});') + f.write(f'impl_spi_pin!({name}, MosiPin, {pin}, {func});') if func := funcs.get(f'{name}_MISO'): - f.write(f'impl_spi_pin!({name}, Miso, {pin}, {func});') + f.write(f'impl_spi_pin!({name}, MisoPin, {pin}, {func});') if block_mod == 'gpio': custom_singletons = True diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs index f14dbfae..82a73938 100644 --- a/embassy-stm32/src/lib.rs +++ b/embassy-stm32/src/lib.rs @@ -26,7 +26,9 @@ pub mod usart; mod pac; pub mod time; +pub use embassy_macros; pub use embassy_macros::interrupt; +pub use embassy_macros::interrupt as irq; pub use pac::{interrupt, peripherals, Peripherals}; // workaround for svd2rust-generated code using `use crate::generic::*;` diff --git a/embassy-stm32/src/pac/regs.rs b/embassy-stm32/src/pac/regs.rs index 26378413..1adb6ca0 100644 --- a/embassy-stm32/src/pac/regs.rs +++ b/embassy-stm32/src/pac/regs.rs @@ -1,5 +1,7077 @@ #![no_std] #![doc = "Peripheral access API (generated using svd2rust v0.17.0 (22741fa 2021-04-20))"] +pub mod dma_v2 { + use crate::generic::*; + #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"] + #[derive(Copy, Clone)] + pub struct St(pub *mut u8); + unsafe impl Send for St {} + unsafe impl Sync for St {} + impl St { + #[doc = "stream x configuration register"] + pub fn cr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "stream x number of data register"] + pub fn ndtr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "stream x peripheral address register"] + pub fn par(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "stream x memory 0 address register"] + pub fn m0ar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "stream x memory 1 address register"] + pub fn m1ar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "stream x FIFO control register"] + pub fn fcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + } + #[doc = "DMA controller"] + #[derive(Copy, Clone)] + pub struct Dma(pub *mut u8); + unsafe impl Send for Dma {} + unsafe impl Sync for Dma {} + impl Dma { + #[doc = "low interrupt status register"] + pub fn isr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) } + } + #[doc = "low interrupt flag clear register"] + pub fn ifcr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } + } + #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"] + pub fn st(self, n: usize) -> St { + assert!(n < 8usize); + unsafe { St(self.0.add(16usize + n * 24usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "stream x number of data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ndtr(pub u32); + impl Ndtr { + #[doc = "Number of data items to transfer"] + pub const fn ndt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Number of data items to transfer"] + pub fn set_ndt(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Ndtr { + fn default() -> Ndtr { + Ndtr(0) + } + } + #[doc = "low interrupt flag clear register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ifcr(pub u32); + impl Ifcr { + #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"] + pub fn cfeif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"] + pub fn set_cfeif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"] + pub fn cdmeif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"] + pub fn set_cdmeif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"] + pub fn cteif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"] + pub fn set_cteif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"] + pub fn chtif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"] + pub fn set_chtif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"] + pub fn ctcif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"] + pub fn set_ctcif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Ifcr { + fn default() -> Ifcr { + Ifcr(0) + } + } + #[doc = "low interrupt status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Isr(pub u32); + impl Isr { + #[doc = "Stream x FIFO error interrupt flag (x=3..0)"] + pub fn feif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x FIFO error interrupt flag (x=3..0)"] + pub fn set_feif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x direct mode error interrupt flag (x=3..0)"] + pub fn dmeif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x direct mode error interrupt flag (x=3..0)"] + pub fn set_dmeif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x transfer error interrupt flag (x=3..0)"] + pub fn teif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x transfer error interrupt flag (x=3..0)"] + pub fn set_teif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x half transfer interrupt flag (x=3..0)"] + pub fn htif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x half transfer interrupt flag (x=3..0)"] + pub fn set_htif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"] + pub fn tcif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"] + pub fn set_tcif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Isr { + fn default() -> Isr { + Isr(0) + } + } + #[doc = "stream x configuration register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Stream enable / flag stream ready when read low"] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Stream enable / flag stream ready when read low"] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Direct mode error interrupt enable"] + pub const fn dmeie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Direct mode error interrupt enable"] + pub fn set_dmeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Transfer error interrupt enable"] + pub const fn teie(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Transfer error interrupt enable"] + pub fn set_teie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Half transfer interrupt enable"] + pub const fn htie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Half transfer interrupt enable"] + pub fn set_htie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Transfer complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Transfer complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Peripheral flow controller"] + pub const fn pfctrl(&self) -> super::vals::Pfctrl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Pfctrl(val as u8) + } + #[doc = "Peripheral flow controller"] + pub fn set_pfctrl(&mut self, val: super::vals::Pfctrl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "Data transfer direction"] + pub const fn dir(&self) -> super::vals::Dir { + let val = (self.0 >> 6usize) & 0x03; + super::vals::Dir(val as u8) + } + #[doc = "Data transfer direction"] + pub fn set_dir(&mut self, val: super::vals::Dir) { + self.0 = (self.0 & !(0x03 << 6usize)) | (((val.0 as u32) & 0x03) << 6usize); + } + #[doc = "Circular mode"] + pub const fn circ(&self) -> super::vals::Circ { + let val = (self.0 >> 8usize) & 0x01; + super::vals::Circ(val as u8) + } + #[doc = "Circular mode"] + pub fn set_circ(&mut self, val: super::vals::Circ) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize); + } + #[doc = "Peripheral increment mode"] + pub const fn pinc(&self) -> super::vals::Inc { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Peripheral increment mode"] + pub fn set_pinc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Memory increment mode"] + pub const fn minc(&self) -> super::vals::Inc { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Memory increment mode"] + pub fn set_minc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Peripheral data size"] + pub const fn psize(&self) -> super::vals::Size { + let val = (self.0 >> 11usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Peripheral data size"] + pub fn set_psize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 11usize)) | (((val.0 as u32) & 0x03) << 11usize); + } + #[doc = "Memory data size"] + pub const fn msize(&self) -> super::vals::Size { + let val = (self.0 >> 13usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Memory data size"] + pub fn set_msize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 13usize)) | (((val.0 as u32) & 0x03) << 13usize); + } + #[doc = "Peripheral increment offset size"] + pub const fn pincos(&self) -> super::vals::Pincos { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Pincos(val as u8) + } + #[doc = "Peripheral increment offset size"] + pub fn set_pincos(&mut self, val: super::vals::Pincos) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + #[doc = "Priority level"] + pub const fn pl(&self) -> super::vals::Pl { + let val = (self.0 >> 16usize) & 0x03; + super::vals::Pl(val as u8) + } + #[doc = "Priority level"] + pub fn set_pl(&mut self, val: super::vals::Pl) { + self.0 = (self.0 & !(0x03 << 16usize)) | (((val.0 as u32) & 0x03) << 16usize); + } + #[doc = "Double buffer mode"] + pub const fn dbm(&self) -> super::vals::Dbm { + let val = (self.0 >> 18usize) & 0x01; + super::vals::Dbm(val as u8) + } + #[doc = "Double buffer mode"] + pub fn set_dbm(&mut self, val: super::vals::Dbm) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize); + } + #[doc = "Current target (only in double buffer mode)"] + pub const fn ct(&self) -> super::vals::Ct { + let val = (self.0 >> 19usize) & 0x01; + super::vals::Ct(val as u8) + } + #[doc = "Current target (only in double buffer mode)"] + pub fn set_ct(&mut self, val: super::vals::Ct) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize); + } + #[doc = "Peripheral burst transfer configuration"] + pub const fn pburst(&self) -> super::vals::Burst { + let val = (self.0 >> 21usize) & 0x03; + super::vals::Burst(val as u8) + } + #[doc = "Peripheral burst transfer configuration"] + pub fn set_pburst(&mut self, val: super::vals::Burst) { + self.0 = (self.0 & !(0x03 << 21usize)) | (((val.0 as u32) & 0x03) << 21usize); + } + #[doc = "Memory burst transfer configuration"] + pub const fn mburst(&self) -> super::vals::Burst { + let val = (self.0 >> 23usize) & 0x03; + super::vals::Burst(val as u8) + } + #[doc = "Memory burst transfer configuration"] + pub fn set_mburst(&mut self, val: super::vals::Burst) { + self.0 = (self.0 & !(0x03 << 23usize)) | (((val.0 as u32) & 0x03) << 23usize); + } + #[doc = "Channel selection"] + pub const fn chsel(&self) -> u8 { + let val = (self.0 >> 25usize) & 0x0f; + val as u8 + } + #[doc = "Channel selection"] + pub fn set_chsel(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 25usize)) | (((val as u32) & 0x0f) << 25usize); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + #[doc = "stream x FIFO control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Fcr(pub u32); + impl Fcr { + #[doc = "FIFO threshold selection"] + pub const fn fth(&self) -> super::vals::Fth { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Fth(val as u8) + } + #[doc = "FIFO threshold selection"] + pub fn set_fth(&mut self, val: super::vals::Fth) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize); + } + #[doc = "Direct mode disable"] + pub const fn dmdis(&self) -> super::vals::Dmdis { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Dmdis(val as u8) + } + #[doc = "Direct mode disable"] + pub fn set_dmdis(&mut self, val: super::vals::Dmdis) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "FIFO status"] + pub const fn fs(&self) -> super::vals::Fs { + let val = (self.0 >> 3usize) & 0x07; + super::vals::Fs(val as u8) + } + #[doc = "FIFO status"] + pub fn set_fs(&mut self, val: super::vals::Fs) { + self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); + } + #[doc = "FIFO error interrupt enable"] + pub const fn feie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "FIFO error interrupt enable"] + pub fn set_feie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for Fcr { + fn default() -> Fcr { + Fcr(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pl(pub u8); + impl Pl { + #[doc = "Low"] + pub const LOW: Self = Self(0); + #[doc = "Medium"] + pub const MEDIUM: Self = Self(0x01); + #[doc = "High"] + pub const HIGH: Self = Self(0x02); + #[doc = "Very high"] + pub const VERYHIGH: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Peripheral-to-memory"] + pub const PERIPHERALTOMEMORY: Self = Self(0); + #[doc = "Memory-to-peripheral"] + pub const MEMORYTOPERIPHERAL: Self = Self(0x01); + #[doc = "Memory-to-memory"] + pub const MEMORYTOMEMORY: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pincos(pub u8); + impl Pincos { + #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] + pub const PSIZE: Self = Self(0); + #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] + pub const FIXED4: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Burst(pub u8); + impl Burst { + #[doc = "Single transfer"] + pub const SINGLE: Self = Self(0); + #[doc = "Incremental burst of 4 beats"] + pub const INCR4: Self = Self(0x01); + #[doc = "Incremental burst of 8 beats"] + pub const INCR8: Self = Self(0x02); + #[doc = "Incremental burst of 16 beats"] + pub const INCR16: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Size(pub u8); + impl Size { + #[doc = "Byte (8-bit)"] + pub const BITS8: Self = Self(0); + #[doc = "Half-word (16-bit)"] + pub const BITS16: Self = Self(0x01); + #[doc = "Word (32-bit)"] + pub const BITS32: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Inc(pub u8); + impl Inc { + #[doc = "Address pointer is fixed"] + pub const FIXED: Self = Self(0); + #[doc = "Address pointer is incremented after each data transfer"] + pub const INCREMENTED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Circ(pub u8); + impl Circ { + #[doc = "Circular mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Circular mode enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dmdis(pub u8); + impl Dmdis { + #[doc = "Direct mode is enabled"] + pub const ENABLED: Self = Self(0); + #[doc = "Direct mode is disabled"] + pub const DISABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Fs(pub u8); + impl Fs { + #[doc = "0 < fifo_level < 1/4"] + pub const QUARTER1: Self = Self(0); + #[doc = "1/4 <= fifo_level < 1/2"] + pub const QUARTER2: Self = Self(0x01); + #[doc = "1/2 <= fifo_level < 3/4"] + pub const QUARTER3: Self = Self(0x02); + #[doc = "3/4 <= fifo_level < full"] + pub const QUARTER4: Self = Self(0x03); + #[doc = "FIFO is empty"] + pub const EMPTY: Self = Self(0x04); + #[doc = "FIFO is full"] + pub const FULL: Self = Self(0x05); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dbm(pub u8); + impl Dbm { + #[doc = "No buffer switching at the end of transfer"] + pub const DISABLED: Self = Self(0); + #[doc = "Memory target switched at the end of the DMA transfer"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Fth(pub u8); + impl Fth { + #[doc = "1/4 full FIFO"] + pub const QUARTER: Self = Self(0); + #[doc = "1/2 full FIFO"] + pub const HALF: Self = Self(0x01); + #[doc = "3/4 full FIFO"] + pub const THREEQUARTERS: Self = Self(0x02); + #[doc = "Full FIFO"] + pub const FULL: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ct(pub u8); + impl Ct { + #[doc = "The current target memory is Memory 0"] + pub const MEMORY0: Self = Self(0); + #[doc = "The current target memory is Memory 1"] + pub const MEMORY1: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pfctrl(pub u8); + impl Pfctrl { + #[doc = "The DMA is the flow controller"] + pub const DMA: Self = Self(0); + #[doc = "The peripheral is the flow controller"] + pub const PERIPHERAL: Self = Self(0x01); + } + } +} +pub mod syscfg_h7 { + use crate::generic::*; + #[doc = "System configuration controller"] + #[derive(Copy, Clone)] + pub struct Syscfg(pub *mut u8); + unsafe impl Send for Syscfg {} + unsafe impl Sync for Syscfg {} + impl Syscfg { + #[doc = "peripheral mode configuration register"] + pub fn pmcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "external interrupt configuration register 1"] + pub fn exticr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } + } + #[doc = "compensation cell control/status register"] + pub fn cccsr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "SYSCFG compensation cell value register"] + pub fn ccvr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "SYSCFG compensation cell code register"] + pub fn cccr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "SYSCFG power control register"] + pub fn pwrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "SYSCFG package register"] + pub fn pkgr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(292usize)) } + } + #[doc = "SYSCFG user register 0"] + pub fn ur0(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(768usize)) } + } + #[doc = "SYSCFG user register 2"] + pub fn ur2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(776usize)) } + } + #[doc = "SYSCFG user register 3"] + pub fn ur3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(780usize)) } + } + #[doc = "SYSCFG user register 4"] + pub fn ur4(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(784usize)) } + } + #[doc = "SYSCFG user register 5"] + pub fn ur5(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(788usize)) } + } + #[doc = "SYSCFG user register 6"] + pub fn ur6(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(792usize)) } + } + #[doc = "SYSCFG user register 7"] + pub fn ur7(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(796usize)) } + } + #[doc = "SYSCFG user register 8"] + pub fn ur8(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(800usize)) } + } + #[doc = "SYSCFG user register 9"] + pub fn ur9(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(804usize)) } + } + #[doc = "SYSCFG user register 10"] + pub fn ur10(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(808usize)) } + } + #[doc = "SYSCFG user register 11"] + pub fn ur11(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(812usize)) } + } + #[doc = "SYSCFG user register 12"] + pub fn ur12(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(816usize)) } + } + #[doc = "SYSCFG user register 13"] + pub fn ur13(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(820usize)) } + } + #[doc = "SYSCFG user register 14"] + pub fn ur14(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(824usize)) } + } + #[doc = "SYSCFG user register 15"] + pub fn ur15(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(828usize)) } + } + #[doc = "SYSCFG user register 16"] + pub fn ur16(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(832usize)) } + } + #[doc = "SYSCFG user register 17"] + pub fn ur17(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(836usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "SYSCFG user register 7"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur7(pub u32); + impl Ur7 { + #[doc = "Secured area start address for bank 1"] + pub const fn sa_beg_1(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area start address for bank 1"] + pub fn set_sa_beg_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Secured area end address for bank 1"] + pub const fn sa_end_1(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area end address for bank 1"] + pub fn set_sa_end_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur7 { + fn default() -> Ur7 { + Ur7(0) + } + } + #[doc = "SYSCFG user register 0"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur0(pub u32); + impl Ur0 { + #[doc = "Bank Swap"] + pub const fn bks(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Bank Swap"] + pub fn set_bks(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Readout protection"] + pub const fn rdp(&self) -> u8 { + let val = (self.0 >> 16usize) & 0xff; + val as u8 + } + #[doc = "Readout protection"] + pub fn set_rdp(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); + } + } + impl Default for Ur0 { + fn default() -> Ur0 { + Ur0(0) + } + } + #[doc = "SYSCFG user register 13"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur13(pub u32); + impl Ur13 { + #[doc = "Secured DTCM RAM Size"] + pub const fn sdrs(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x03; + val as u8 + } + #[doc = "Secured DTCM RAM Size"] + pub fn set_sdrs(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); + } + #[doc = "D1 Standby reset"] + pub const fn d1sbrst(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "D1 Standby reset"] + pub fn set_d1sbrst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur13 { + fn default() -> Ur13 { + Ur13(0) + } + } + #[doc = "SYSCFG user register 12"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur12(pub u32); + impl Ur12 { + #[doc = "Secure mode"] + pub const fn secure(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Secure mode"] + pub fn set_secure(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur12 { + fn default() -> Ur12 { + Ur12(0) + } + } + #[doc = "SYSCFG power control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pwrcr(pub u32); + impl Pwrcr { + #[doc = "Overdrive enable"] + pub const fn oden(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Overdrive enable"] + pub fn set_oden(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + } + impl Default for Pwrcr { + fn default() -> Pwrcr { + Pwrcr(0) + } + } + #[doc = "SYSCFG user register 16"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur16(pub u32); + impl Ur16 { + #[doc = "Freeze independent watchdog in Stop mode"] + pub const fn fziwdgstp(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Freeze independent watchdog in Stop mode"] + pub fn set_fziwdgstp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Private key programmed"] + pub const fn pkp(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Private key programmed"] + pub fn set_pkp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur16 { + fn default() -> Ur16 { + Ur16(0) + } + } + #[doc = "SYSCFG user register 5"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur5(pub u32); + impl Ur5 { + #[doc = "Mass erase secured area disabled for bank 1"] + pub const fn mesad_1(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Mass erase secured area disabled for bank 1"] + pub fn set_mesad_1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Write protection for flash bank 1"] + pub const fn wrpn_1(&self) -> u8 { + let val = (self.0 >> 16usize) & 0xff; + val as u8 + } + #[doc = "Write protection for flash bank 1"] + pub fn set_wrpn_1(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); + } + } + impl Default for Ur5 { + fn default() -> Ur5 { + Ur5(0) + } + } + #[doc = "SYSCFG user register 8"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur8(pub u32); + impl Ur8 { + #[doc = "Mass erase protected area disabled for bank 2"] + pub const fn mepad_2(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Mass erase protected area disabled for bank 2"] + pub fn set_mepad_2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Mass erase secured area disabled for bank 2"] + pub const fn mesad_2(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Mass erase secured area disabled for bank 2"] + pub fn set_mesad_2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur8 { + fn default() -> Ur8 { + Ur8(0) + } + } + #[doc = "SYSCFG user register 11"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur11(pub u32); + impl Ur11 { + #[doc = "Secured area end address for bank 2"] + pub const fn sa_end_2(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area end address for bank 2"] + pub fn set_sa_end_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Independent Watchdog 1 mode"] + pub const fn iwdg1m(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Independent Watchdog 1 mode"] + pub fn set_iwdg1m(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur11 { + fn default() -> Ur11 { + Ur11(0) + } + } + #[doc = "SYSCFG user register 4"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur4(pub u32); + impl Ur4 { + #[doc = "Mass Erase Protected Area Disabled for bank 1"] + pub const fn mepad_1(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Mass Erase Protected Area Disabled for bank 1"] + pub fn set_mepad_1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur4 { + fn default() -> Ur4 { + Ur4(0) + } + } + #[doc = "peripheral mode configuration register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pmcr(pub u32); + impl Pmcr { + #[doc = "I2C1 Fm+"] + pub const fn i2c1fmp(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "I2C1 Fm+"] + pub fn set_i2c1fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "I2C2 Fm+"] + pub const fn i2c2fmp(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "I2C2 Fm+"] + pub fn set_i2c2fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "I2C3 Fm+"] + pub const fn i2c3fmp(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "I2C3 Fm+"] + pub fn set_i2c3fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "I2C4 Fm+"] + pub const fn i2c4fmp(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "I2C4 Fm+"] + pub fn set_i2c4fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "PB(6) Fm+"] + pub const fn pb6fmp(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "PB(6) Fm+"] + pub fn set_pb6fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "PB(7) Fast Mode Plus"] + pub const fn pb7fmp(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "PB(7) Fast Mode Plus"] + pub fn set_pb7fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "PB(8) Fast Mode Plus"] + pub const fn pb8fmp(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "PB(8) Fast Mode Plus"] + pub fn set_pb8fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "PB(9) Fm+"] + pub const fn pb9fmp(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "PB(9) Fm+"] + pub fn set_pb9fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Booster Enable"] + pub const fn booste(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Booster Enable"] + pub fn set_booste(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Analog switch supply voltage selection"] + pub const fn boostvddsel(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Analog switch supply voltage selection"] + pub fn set_boostvddsel(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Ethernet PHY Interface Selection"] + pub const fn epis(&self) -> u8 { + let val = (self.0 >> 21usize) & 0x07; + val as u8 + } + #[doc = "Ethernet PHY Interface Selection"] + pub fn set_epis(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 21usize)) | (((val as u32) & 0x07) << 21usize); + } + #[doc = "PA0 Switch Open"] + pub const fn pa0so(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "PA0 Switch Open"] + pub fn set_pa0so(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "PA1 Switch Open"] + pub const fn pa1so(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "PA1 Switch Open"] + pub fn set_pa1so(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "PC2 Switch Open"] + pub const fn pc2so(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "PC2 Switch Open"] + pub fn set_pc2so(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "PC3 Switch Open"] + pub const fn pc3so(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "PC3 Switch Open"] + pub fn set_pc3so(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + } + impl Default for Pmcr { + fn default() -> Pmcr { + Pmcr(0) + } + } + #[doc = "SYSCFG user register 10"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur10(pub u32); + impl Ur10 { + #[doc = "Protected area end address for bank 2"] + pub const fn pa_end_2(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area end address for bank 2"] + pub fn set_pa_end_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Secured area start address for bank 2"] + pub const fn sa_beg_2(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area start address for bank 2"] + pub fn set_sa_beg_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur10 { + fn default() -> Ur10 { + Ur10(0) + } + } + #[doc = "SYSCFG user register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur3(pub u32); + impl Ur3 { + #[doc = "Boot Address 1"] + pub const fn boot_add1(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "Boot Address 1"] + pub fn set_boot_add1(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + } + } + impl Default for Ur3 { + fn default() -> Ur3 { + Ur3(0) + } + } + #[doc = "SYSCFG user register 15"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur15(pub u32); + impl Ur15 { + #[doc = "Freeze independent watchdog in Standby mode"] + pub const fn fziwdgstb(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Freeze independent watchdog in Standby mode"] + pub fn set_fziwdgstb(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur15 { + fn default() -> Ur15 { + Ur15(0) + } + } + #[doc = "SYSCFG compensation cell value register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccvr(pub u32); + impl Ccvr { + #[doc = "NMOS compensation value"] + pub const fn ncv(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "NMOS compensation value"] + pub fn set_ncv(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "PMOS compensation value"] + pub const fn pcv(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "PMOS compensation value"] + pub fn set_pcv(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + } + impl Default for Ccvr { + fn default() -> Ccvr { + Ccvr(0) + } + } + #[doc = "SYSCFG user register 9"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur9(pub u32); + impl Ur9 { + #[doc = "Write protection for flash bank 2"] + pub const fn wrpn_2(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Write protection for flash bank 2"] + pub fn set_wrpn_2(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Protected area start address for bank 2"] + pub const fn pa_beg_2(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area start address for bank 2"] + pub fn set_pa_beg_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur9 { + fn default() -> Ur9 { + Ur9(0) + } + } + #[doc = "SYSCFG user register 17"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur17(pub u32); + impl Ur17 { + #[doc = "I/O high speed / low voltage"] + pub const fn io_hslv(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "I/O high speed / low voltage"] + pub fn set_io_hslv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for Ur17 { + fn default() -> Ur17 { + Ur17(0) + } + } + #[doc = "SYSCFG user register 6"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur6(pub u32); + impl Ur6 { + #[doc = "Protected area start address for bank 1"] + pub const fn pa_beg_1(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area start address for bank 1"] + pub fn set_pa_beg_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Protected area end address for bank 1"] + pub const fn pa_end_1(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area end address for bank 1"] + pub fn set_pa_end_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur6 { + fn default() -> Ur6 { + Ur6(0) + } + } + #[doc = "compensation cell control/status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cccsr(pub u32); + impl Cccsr { + #[doc = "enable"] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "enable"] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Code selection"] + pub const fn cs(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Code selection"] + pub fn set_cs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Compensation cell ready flag"] + pub const fn ready(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Compensation cell ready flag"] + pub fn set_ready(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "High-speed at low-voltage"] + pub const fn hslv(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "High-speed at low-voltage"] + pub fn set_hslv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Cccsr { + fn default() -> Cccsr { + Cccsr(0) + } + } + #[doc = "SYSCFG package register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pkgr(pub u32); + impl Pkgr { + #[doc = "Package"] + pub const fn pkg(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Package"] + pub fn set_pkg(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + } + impl Default for Pkgr { + fn default() -> Pkgr { + Pkgr(0) + } + } + #[doc = "external interrupt configuration register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Exticr(pub u32); + impl Exticr { + #[doc = "EXTI x configuration (x = 4 to 7)"] + pub fn exti(&self, n: usize) -> u8 { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + val as u8 + } + #[doc = "EXTI x configuration (x = 4 to 7)"] + pub fn set_exti(&mut self, n: usize, val: u8) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); + } + } + impl Default for Exticr { + fn default() -> Exticr { + Exticr(0) + } + } + #[doc = "SYSCFG user register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur2(pub u32); + impl Ur2 { + #[doc = "BOR_LVL Brownout Reset Threshold Level"] + pub const fn borh(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x03; + val as u8 + } + #[doc = "BOR_LVL Brownout Reset Threshold Level"] + pub fn set_borh(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); + } + #[doc = "Boot Address 0"] + pub const fn boot_add0(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "Boot Address 0"] + pub fn set_boot_add0(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + } + } + impl Default for Ur2 { + fn default() -> Ur2 { + Ur2(0) + } + } + #[doc = "SYSCFG user register 14"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur14(pub u32); + impl Ur14 { + #[doc = "D1 Stop Reset"] + pub const fn d1stprst(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "D1 Stop Reset"] + pub fn set_d1stprst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for Ur14 { + fn default() -> Ur14 { + Ur14(0) + } + } + #[doc = "SYSCFG compensation cell code register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cccr(pub u32); + impl Cccr { + #[doc = "NMOS compensation code"] + pub const fn ncc(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "NMOS compensation code"] + pub fn set_ncc(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "PMOS compensation code"] + pub const fn pcc(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "PMOS compensation code"] + pub fn set_pcc(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + } + impl Default for Cccr { + fn default() -> Cccr { + Cccr(0) + } + } + } +} +pub mod dma_v1 { + use crate::generic::*; + #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] + #[derive(Copy, Clone)] + pub struct Ch(pub *mut u8); + unsafe impl Send for Ch {} + unsafe impl Sync for Ch {} + impl Ch { + #[doc = "DMA channel configuration register (DMA_CCR)"] + pub fn cr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "DMA channel 1 number of data register"] + pub fn ndtr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "DMA channel 1 peripheral address register"] + pub fn par(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA channel 1 memory address register"] + pub fn mar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + } + #[doc = "DMA controller"] + #[derive(Copy, Clone)] + pub struct Dma(pub *mut u8); + unsafe impl Send for Dma {} + unsafe impl Sync for Dma {} + impl Dma { + #[doc = "DMA interrupt status register (DMA_ISR)"] + pub fn isr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] + pub fn ifcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] + pub fn ch(self, n: usize) -> Ch { + assert!(n < 7usize); + unsafe { Ch(self.0.add(8usize + n * 20usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ifcr(pub u32); + impl Ifcr { + #[doc = "Channel 1 Global interrupt clear"] + pub fn cgif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Global interrupt clear"] + pub fn set_cgif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Complete clear"] + pub fn ctcif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Complete clear"] + pub fn set_ctcif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Half Transfer clear"] + pub fn chtif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Half Transfer clear"] + pub fn set_chtif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Error clear"] + pub fn cteif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Error clear"] + pub fn set_cteif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Ifcr { + fn default() -> Ifcr { + Ifcr(0) + } + } + #[doc = "DMA interrupt status register (DMA_ISR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Isr(pub u32); + impl Isr { + #[doc = "Channel 1 Global interrupt flag"] + pub fn gif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Global interrupt flag"] + pub fn set_gif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Complete flag"] + pub fn tcif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Complete flag"] + pub fn set_tcif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Half Transfer Complete flag"] + pub fn htif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Half Transfer Complete flag"] + pub fn set_htif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Error flag"] + pub fn teif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Error flag"] + pub fn set_teif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Isr { + fn default() -> Isr { + Isr(0) + } + } + #[doc = "DMA channel 1 number of data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ndtr(pub u32); + impl Ndtr { + #[doc = "Number of data to transfer"] + pub const fn ndt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Number of data to transfer"] + pub fn set_ndt(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Ndtr { + fn default() -> Ndtr { + Ndtr(0) + } + } + #[doc = "DMA channel configuration register (DMA_CCR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Channel enable"] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Channel enable"] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Transfer complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Transfer complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Half Transfer interrupt enable"] + pub const fn htie(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Half Transfer interrupt enable"] + pub fn set_htie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Transfer error interrupt enable"] + pub const fn teie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Transfer error interrupt enable"] + pub fn set_teie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Data transfer direction"] + pub const fn dir(&self) -> super::vals::Dir { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Dir(val as u8) + } + #[doc = "Data transfer direction"] + pub fn set_dir(&mut self, val: super::vals::Dir) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Circular mode"] + pub const fn circ(&self) -> super::vals::Circ { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Circ(val as u8) + } + #[doc = "Circular mode"] + pub fn set_circ(&mut self, val: super::vals::Circ) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "Peripheral increment mode"] + pub const fn pinc(&self) -> super::vals::Inc { + let val = (self.0 >> 6usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Peripheral increment mode"] + pub fn set_pinc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize); + } + #[doc = "Memory increment mode"] + pub const fn minc(&self) -> super::vals::Inc { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Memory increment mode"] + pub fn set_minc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Peripheral size"] + pub const fn psize(&self) -> super::vals::Size { + let val = (self.0 >> 8usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Peripheral size"] + pub fn set_psize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); + } + #[doc = "Memory size"] + pub const fn msize(&self) -> super::vals::Size { + let val = (self.0 >> 10usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Memory size"] + pub fn set_msize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 10usize)) | (((val.0 as u32) & 0x03) << 10usize); + } + #[doc = "Channel Priority level"] + pub const fn pl(&self) -> super::vals::Pl { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Pl(val as u8) + } + #[doc = "Channel Priority level"] + pub fn set_pl(&mut self, val: super::vals::Pl) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "Memory to memory mode"] + pub const fn mem2mem(&self) -> super::vals::Memmem { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Memmem(val as u8) + } + #[doc = "Memory to memory mode"] + pub fn set_mem2mem(&mut self, val: super::vals::Memmem) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Size(pub u8); + impl Size { + #[doc = "8-bit size"] + pub const BITS8: Self = Self(0); + #[doc = "16-bit size"] + pub const BITS16: Self = Self(0x01); + #[doc = "32-bit size"] + pub const BITS32: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Inc(pub u8); + impl Inc { + #[doc = "Increment mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Increment mode enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Read from peripheral"] + pub const FROMPERIPHERAL: Self = Self(0); + #[doc = "Read from memory"] + pub const FROMMEMORY: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Memmem(pub u8); + impl Memmem { + #[doc = "Memory to memory mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Memory to memory mode enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Circ(pub u8); + impl Circ { + #[doc = "Circular buffer disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Circular buffer enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pl(pub u8); + impl Pl { + #[doc = "Low priority"] + pub const LOW: Self = Self(0); + #[doc = "Medium priority"] + pub const MEDIUM: Self = Self(0x01); + #[doc = "High priority"] + pub const HIGH: Self = Self(0x02); + #[doc = "Very high priority"] + pub const VERYHIGH: Self = Self(0x03); + } + } +} +pub mod timer_v1 { + use crate::generic::*; + #[doc = "General purpose 16-bit timer"] + #[derive(Copy, Clone)] + pub struct TimGp16(pub *mut u8); + unsafe impl Send for TimGp16 {} + unsafe impl Sync for TimGp16 {} + impl TimGp16 { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "slave mode control register"] + pub fn smcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "capture/compare mode register 1 (input mode)"] + pub fn ccmr_input(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare mode register 1 (output mode)"] + pub fn ccmr_output(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare enable register"] + pub fn ccer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "capture/compare register"] + pub fn ccr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } + } + #[doc = "DMA control register"] + pub fn dcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(72usize)) } + } + #[doc = "DMA address for full transfer"] + pub fn dmar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(76usize)) } + } + } + #[doc = "General purpose 32-bit timer"] + #[derive(Copy, Clone)] + pub struct TimGp32(pub *mut u8); + unsafe impl Send for TimGp32 {} + unsafe impl Sync for TimGp32 {} + impl TimGp32 { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "slave mode control register"] + pub fn smcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "capture/compare mode register 1 (input mode)"] + pub fn ccmr_input(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare mode register 1 (output mode)"] + pub fn ccmr_output(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare enable register"] + pub fn ccer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "capture/compare register"] + pub fn ccr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } + } + #[doc = "DMA control register"] + pub fn dcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(72usize)) } + } + #[doc = "DMA address for full transfer"] + pub fn dmar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(76usize)) } + } + } + #[doc = "Basic timer"] + #[derive(Copy, Clone)] + pub struct TimBasic(pub *mut u8); + unsafe impl Send for TimBasic {} + unsafe impl Sync for TimBasic {} + impl TimBasic { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + } + #[doc = "Advanced-timers"] + #[derive(Copy, Clone)] + pub struct TimAdv(pub *mut u8); + unsafe impl Send for TimAdv {} + unsafe impl Sync for TimAdv {} + impl TimAdv { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "slave mode control register"] + pub fn smcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "capture/compare mode register 1 (input mode)"] + pub fn ccmr_input(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare mode register 1 (output mode)"] + pub fn ccmr_output(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare enable register"] + pub fn ccer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "repetition counter register"] + pub fn rcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(48usize)) } + } + #[doc = "capture/compare register"] + pub fn ccr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } + } + #[doc = "break and dead-time register"] + pub fn bdtr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(68usize)) } + } + #[doc = "DMA control register"] + pub fn dcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(72usize)) } + } + #[doc = "DMA address for full transfer"] + pub fn dmar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(76usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierBasic(pub u32); + impl DierBasic { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for DierBasic { + fn default() -> DierBasic { + DierBasic(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrGp(pub u32); + impl SrGp { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn ccif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn set_ccif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt flag"] + pub const fn comif(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt flag"] + pub fn set_comif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt flag"] + pub const fn tif(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt flag"] + pub fn set_tif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt flag"] + pub const fn bif(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break interrupt flag"] + pub fn set_bif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn ccof(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn set_ccof(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for SrGp { + fn default() -> SrGp { + SrGp(0) + } + } + #[doc = "counter"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cnt16(pub u32); + impl Cnt16 { + #[doc = "counter value"] + pub const fn cnt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "counter value"] + pub fn set_cnt(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Cnt16 { + fn default() -> Cnt16 { + Cnt16(0) + } + } + #[doc = "capture/compare enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcerGp(pub u32); + impl CcerGp { + #[doc = "Capture/Compare 1 output enable"] + pub fn cce(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output enable"] + pub fn set_cce(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccnp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccnp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcerGp { + fn default() -> CcerGp { + CcerGp(0) + } + } + #[doc = "capture/compare register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccr16(pub u32); + impl Ccr16 { + #[doc = "Capture/Compare 1 value"] + pub const fn ccr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Capture/Compare 1 value"] + pub fn set_ccr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Ccr16 { + fn default() -> Ccr16 { + Ccr16(0) + } + } + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierGp(pub u32); + impl DierGp { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn ccie(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn set_ccie(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Trigger interrupt enable"] + pub const fn tie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt enable"] + pub fn set_tie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn ccde(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn set_ccde(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Trigger DMA request enable"] + pub const fn tde(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Trigger DMA request enable"] + pub fn set_tde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for DierGp { + fn default() -> DierGp { + DierGp(0) + } + } + #[doc = "prescaler"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Psc(pub u32); + impl Psc { + #[doc = "Prescaler value"] + pub const fn psc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Prescaler value"] + pub fn set_psc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Psc { + fn default() -> Psc { + Psc(0) + } + } + #[doc = "capture/compare mode register 2 (output mode)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcmrOutput(pub u32); + impl CcmrOutput { + #[doc = "Capture/Compare 3 selection"] + pub fn ccs(&self, n: usize) -> super::vals::CcmrOutputCcs { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + super::vals::CcmrOutputCcs(val as u8) + } + #[doc = "Capture/Compare 3 selection"] + pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrOutputCcs) { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Output compare 3 fast enable"] + pub fn ocfe(&self, n: usize) -> bool { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output compare 3 fast enable"] + pub fn set_ocfe(&mut self, n: usize, val: bool) { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Output compare 3 preload enable"] + pub fn ocpe(&self, n: usize) -> super::vals::Ocpe { + assert!(n < 2usize); + let offs = 3usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Ocpe(val as u8) + } + #[doc = "Output compare 3 preload enable"] + pub fn set_ocpe(&mut self, n: usize, val: super::vals::Ocpe) { + assert!(n < 2usize); + let offs = 3usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Output compare 3 mode"] + pub fn ocm(&self, n: usize) -> super::vals::Ocm { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + let val = (self.0 >> offs) & 0x07; + super::vals::Ocm(val as u8) + } + #[doc = "Output compare 3 mode"] + pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + self.0 = (self.0 & !(0x07 << offs)) | (((val.0 as u32) & 0x07) << offs); + } + #[doc = "Output compare 3 clear enable"] + pub fn occe(&self, n: usize) -> bool { + assert!(n < 2usize); + let offs = 7usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output compare 3 clear enable"] + pub fn set_occe(&mut self, n: usize, val: bool) { + assert!(n < 2usize); + let offs = 7usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcmrOutput { + fn default() -> CcmrOutput { + CcmrOutput(0) + } + } + #[doc = "DMA address for full transfer"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dmar(pub u32); + impl Dmar { + #[doc = "DMA register for burst accesses"] + pub const fn dmab(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "DMA register for burst accesses"] + pub fn set_dmab(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Dmar { + fn default() -> Dmar { + Dmar(0) + } + } + #[doc = "capture/compare enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcerAdv(pub u32); + impl CcerAdv { + #[doc = "Capture/Compare 1 output enable"] + pub fn cce(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output enable"] + pub fn set_cce(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 complementary output enable"] + pub fn ccne(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 complementary output enable"] + pub fn set_ccne(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccnp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccnp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcerAdv { + fn default() -> CcerAdv { + CcerAdv(0) + } + } + #[doc = "break and dead-time register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Bdtr(pub u32); + impl Bdtr { + #[doc = "Dead-time generator setup"] + pub const fn dtg(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Dead-time generator setup"] + pub fn set_dtg(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Lock configuration"] + pub const fn lock(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x03; + val as u8 + } + #[doc = "Lock configuration"] + pub fn set_lock(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); + } + #[doc = "Off-state selection for Idle mode"] + pub const fn ossi(&self) -> super::vals::Ossi { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Ossi(val as u8) + } + #[doc = "Off-state selection for Idle mode"] + pub fn set_ossi(&mut self, val: super::vals::Ossi) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Off-state selection for Run mode"] + pub const fn ossr(&self) -> super::vals::Ossr { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Ossr(val as u8) + } + #[doc = "Off-state selection for Run mode"] + pub fn set_ossr(&mut self, val: super::vals::Ossr) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "Break enable"] + pub const fn bke(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Break enable"] + pub fn set_bke(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Break polarity"] + pub const fn bkp(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Break polarity"] + pub fn set_bkp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Automatic output enable"] + pub const fn aoe(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Automatic output enable"] + pub fn set_aoe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Main output enable"] + pub const fn moe(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Main output enable"] + pub fn set_moe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + } + impl Default for Bdtr { + fn default() -> Bdtr { + Bdtr(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrAdv(pub u32); + impl SrAdv { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn ccif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn set_ccif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt flag"] + pub const fn comif(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt flag"] + pub fn set_comif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt flag"] + pub const fn tif(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt flag"] + pub fn set_tif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt flag"] + pub const fn bif(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break interrupt flag"] + pub fn set_bif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn ccof(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn set_ccof(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for SrAdv { + fn default() -> SrAdv { + SrAdv(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1Gp(pub u32); + impl Cr1Gp { + #[doc = "Counter enable"] + pub const fn cen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Counter enable"] + pub fn set_cen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update disable"] + pub const fn udis(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Update disable"] + pub fn set_udis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Update request source"] + pub const fn urs(&self) -> super::vals::Urs { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Urs(val as u8) + } + #[doc = "Update request source"] + pub fn set_urs(&mut self, val: super::vals::Urs) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "One-pulse mode"] + pub const fn opm(&self) -> super::vals::Opm { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Opm(val as u8) + } + #[doc = "One-pulse mode"] + pub fn set_opm(&mut self, val: super::vals::Opm) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Direction"] + pub const fn dir(&self) -> super::vals::Dir { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Dir(val as u8) + } + #[doc = "Direction"] + pub fn set_dir(&mut self, val: super::vals::Dir) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Center-aligned mode selection"] + pub const fn cms(&self) -> super::vals::Cms { + let val = (self.0 >> 5usize) & 0x03; + super::vals::Cms(val as u8) + } + #[doc = "Center-aligned mode selection"] + pub fn set_cms(&mut self, val: super::vals::Cms) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize); + } + #[doc = "Auto-reload preload enable"] + pub const fn arpe(&self) -> super::vals::Arpe { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Arpe(val as u8) + } + #[doc = "Auto-reload preload enable"] + pub fn set_arpe(&mut self, val: super::vals::Arpe) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Clock division"] + pub const fn ckd(&self) -> super::vals::Ckd { + let val = (self.0 >> 8usize) & 0x03; + super::vals::Ckd(val as u8) + } + #[doc = "Clock division"] + pub fn set_ckd(&mut self, val: super::vals::Ckd) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); + } + } + impl Default for Cr1Gp { + fn default() -> Cr1Gp { + Cr1Gp(0) + } + } + #[doc = "DMA control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dcr(pub u32); + impl Dcr { + #[doc = "DMA base address"] + pub const fn dba(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 + } + #[doc = "DMA base address"] + pub fn set_dba(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); + } + #[doc = "DMA burst length"] + pub const fn dbl(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x1f; + val as u8 + } + #[doc = "DMA burst length"] + pub fn set_dbl(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); + } + } + impl Default for Dcr { + fn default() -> Dcr { + Dcr(0) + } + } + #[doc = "event generation register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct EgrBasic(pub u32); + impl EgrBasic { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for EgrBasic { + fn default() -> EgrBasic { + EgrBasic(0) + } + } + #[doc = "counter"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cnt32(pub u32); + impl Cnt32 { + #[doc = "counter value"] + pub const fn cnt(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "counter value"] + pub fn set_cnt(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Cnt32 { + fn default() -> Cnt32 { + Cnt32(0) + } + } + #[doc = "auto-reload register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Arr32(pub u32); + impl Arr32 { + #[doc = "Auto-reload value"] + pub const fn arr(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Auto-reload value"] + pub fn set_arr(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Arr32 { + fn default() -> Arr32 { + Arr32(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Adv(pub u32); + impl Cr2Adv { + #[doc = "Capture/compare preloaded control"] + pub const fn ccpc(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Capture/compare preloaded control"] + pub fn set_ccpc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare control update selection"] + pub const fn ccus(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Capture/compare control update selection"] + pub fn set_ccus(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Capture/compare DMA selection"] + pub const fn ccds(&self) -> super::vals::Ccds { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Ccds(val as u8) + } + #[doc = "Capture/compare DMA selection"] + pub fn set_ccds(&mut self, val: super::vals::Ccds) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "TI1 selection"] + pub const fn ti1s(&self) -> super::vals::Tis { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Tis(val as u8) + } + #[doc = "TI1 selection"] + pub fn set_ti1s(&mut self, val: super::vals::Tis) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Output Idle state 1"] + pub fn ois(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 8usize + n * 2usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output Idle state 1"] + pub fn set_ois(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 8usize + n * 2usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Output Idle state 1"] + pub const fn ois1n(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 1"] + pub fn set_ois1n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Output Idle state 2"] + pub const fn ois2n(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 2"] + pub fn set_ois2n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Output Idle state 3"] + pub const fn ois3n(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 3"] + pub fn set_ois3n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + } + impl Default for Cr2Adv { + fn default() -> Cr2Adv { + Cr2Adv(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1Basic(pub u32); + impl Cr1Basic { + #[doc = "Counter enable"] + pub const fn cen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Counter enable"] + pub fn set_cen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update disable"] + pub const fn udis(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Update disable"] + pub fn set_udis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Update request source"] + pub const fn urs(&self) -> super::vals::Urs { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Urs(val as u8) + } + #[doc = "Update request source"] + pub fn set_urs(&mut self, val: super::vals::Urs) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "One-pulse mode"] + pub const fn opm(&self) -> super::vals::Opm { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Opm(val as u8) + } + #[doc = "One-pulse mode"] + pub fn set_opm(&mut self, val: super::vals::Opm) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Auto-reload preload enable"] + pub const fn arpe(&self) -> super::vals::Arpe { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Arpe(val as u8) + } + #[doc = "Auto-reload preload enable"] + pub fn set_arpe(&mut self, val: super::vals::Arpe) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + } + impl Default for Cr1Basic { + fn default() -> Cr1Basic { + Cr1Basic(0) + } + } + #[doc = "capture/compare mode register 1 (input mode)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcmrInput(pub u32); + impl CcmrInput { + #[doc = "Capture/Compare 1 selection"] + pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + super::vals::CcmrInputCcs(val as u8) + } + #[doc = "Capture/Compare 1 selection"] + pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Input capture 1 prescaler"] + pub fn icpsc(&self, n: usize) -> u8 { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + val as u8 + } + #[doc = "Input capture 1 prescaler"] + pub fn set_icpsc(&mut self, n: usize, val: u8) { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs); + } + #[doc = "Input capture 1 filter"] + pub fn icf(&self, n: usize) -> super::vals::Icf { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + let val = (self.0 >> offs) & 0x0f; + super::vals::Icf(val as u8) + } + #[doc = "Input capture 1 filter"] + pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); + } + } + impl Default for CcmrInput { + fn default() -> CcmrInput { + CcmrInput(0) + } + } + #[doc = "repetition counter register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rcr(pub u32); + impl Rcr { + #[doc = "Repetition counter value"] + pub const fn rep(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Repetition counter value"] + pub fn set_rep(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + } + impl Default for Rcr { + fn default() -> Rcr { + Rcr(0) + } + } + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierAdv(pub u32); + impl DierAdv { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn ccie(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn set_ccie(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt enable"] + pub const fn comie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt enable"] + pub fn set_comie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt enable"] + pub const fn tie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt enable"] + pub fn set_tie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt enable"] + pub const fn bie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break interrupt enable"] + pub fn set_bie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn ccde(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn set_ccde(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM DMA request enable"] + pub const fn comde(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "COM DMA request enable"] + pub fn set_comde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Trigger DMA request enable"] + pub const fn tde(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Trigger DMA request enable"] + pub fn set_tde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for DierAdv { + fn default() -> DierAdv { + DierAdv(0) + } + } + #[doc = "auto-reload register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Arr16(pub u32); + impl Arr16 { + #[doc = "Auto-reload value"] + pub const fn arr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Auto-reload value"] + pub fn set_arr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Arr16 { + fn default() -> Arr16 { + Arr16(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrBasic(pub u32); + impl SrBasic { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for SrBasic { + fn default() -> SrBasic { + SrBasic(0) + } + } + #[doc = "slave mode control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Smcr(pub u32); + impl Smcr { + #[doc = "Slave mode selection"] + pub const fn sms(&self) -> super::vals::Sms { + let val = (self.0 >> 0usize) & 0x07; + super::vals::Sms(val as u8) + } + #[doc = "Slave mode selection"] + pub fn set_sms(&mut self, val: super::vals::Sms) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize); + } + #[doc = "Trigger selection"] + pub const fn ts(&self) -> super::vals::Ts { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Ts(val as u8) + } + #[doc = "Trigger selection"] + pub fn set_ts(&mut self, val: super::vals::Ts) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "Master/Slave mode"] + pub const fn msm(&self) -> super::vals::Msm { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Msm(val as u8) + } + #[doc = "Master/Slave mode"] + pub fn set_msm(&mut self, val: super::vals::Msm) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "External trigger filter"] + pub const fn etf(&self) -> super::vals::Etf { + let val = (self.0 >> 8usize) & 0x0f; + super::vals::Etf(val as u8) + } + #[doc = "External trigger filter"] + pub fn set_etf(&mut self, val: super::vals::Etf) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); + } + #[doc = "External trigger prescaler"] + pub const fn etps(&self) -> super::vals::Etps { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Etps(val as u8) + } + #[doc = "External trigger prescaler"] + pub fn set_etps(&mut self, val: super::vals::Etps) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "External clock enable"] + pub const fn ece(&self) -> super::vals::Ece { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Ece(val as u8) + } + #[doc = "External clock enable"] + pub fn set_ece(&mut self, val: super::vals::Ece) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + #[doc = "External trigger polarity"] + pub const fn etp(&self) -> super::vals::Etp { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Etp(val as u8) + } + #[doc = "External trigger polarity"] + pub fn set_etp(&mut self, val: super::vals::Etp) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + } + impl Default for Smcr { + fn default() -> Smcr { + Smcr(0) + } + } + #[doc = "event generation register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct EgrGp(pub u32); + impl EgrGp { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 generation"] + pub fn ccg(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 generation"] + pub fn set_ccg(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare control update generation"] + pub const fn comg(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Capture/Compare control update generation"] + pub fn set_comg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger generation"] + pub const fn tg(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger generation"] + pub fn set_tg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break generation"] + pub const fn bg(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break generation"] + pub fn set_bg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for EgrGp { + fn default() -> EgrGp { + EgrGp(0) + } + } + #[doc = "capture/compare register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccr32(pub u32); + impl Ccr32 { + #[doc = "Capture/Compare 1 value"] + pub const fn ccr(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Capture/Compare 1 value"] + pub fn set_ccr(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Ccr32 { + fn default() -> Ccr32 { + Ccr32(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Basic(pub u32); + impl Cr2Basic { + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + } + impl Default for Cr2Basic { + fn default() -> Cr2Basic { + Cr2Basic(0) + } + } + #[doc = "event generation register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct EgrAdv(pub u32); + impl EgrAdv { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 generation"] + pub fn ccg(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 generation"] + pub fn set_ccg(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare control update generation"] + pub const fn comg(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Capture/Compare control update generation"] + pub fn set_comg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger generation"] + pub const fn tg(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger generation"] + pub fn set_tg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break generation"] + pub const fn bg(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break generation"] + pub fn set_bg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for EgrAdv { + fn default() -> EgrAdv { + EgrAdv(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Gp(pub u32); + impl Cr2Gp { + #[doc = "Capture/compare DMA selection"] + pub const fn ccds(&self) -> super::vals::Ccds { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Ccds(val as u8) + } + #[doc = "Capture/compare DMA selection"] + pub fn set_ccds(&mut self, val: super::vals::Ccds) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "TI1 selection"] + pub const fn ti1s(&self) -> super::vals::Tis { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Tis(val as u8) + } + #[doc = "TI1 selection"] + pub fn set_ti1s(&mut self, val: super::vals::Tis) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + } + impl Default for Cr2Gp { + fn default() -> Cr2Gp { + Cr2Gp(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Opm(pub u8); + impl Opm { + #[doc = "Counter is not stopped at update event"] + pub const DISABLED: Self = Self(0); + #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Tis(pub u8); + impl Tis { + #[doc = "The TIMx_CH1 pin is connected to TI1 input"] + pub const NORMAL: Self = Self(0); + #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"] + pub const XOR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Msm(pub u8); + impl Msm { + #[doc = "No action"] + pub const NOSYNC: Self = Self(0); + #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."] + pub const SYNC: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Urs(pub u8); + impl Urs { + #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"] + pub const ANYEVENT: Self = Self(0); + #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"] + pub const COUNTERONLY: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ocm(pub u8); + impl Ocm { + #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] + pub const FROZEN: Self = Self(0); + #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] + pub const ACTIVEONMATCH: Self = Self(0x01); + #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] + pub const INACTIVEONMATCH: Self = Self(0x02); + #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] + pub const TOGGLE: Self = Self(0x03); + #[doc = "OCyREF is forced low"] + pub const FORCEINACTIVE: Self = Self(0x04); + #[doc = "OCyREF is forced high"] + pub const FORCEACTIVE: Self = Self(0x05); + #[doc = "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active"] + pub const PWMMODE1: Self = Self(0x06); + #[doc = "Inversely to PwmMode1"] + pub const PWMMODE2: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Arpe(pub u8); + impl Arpe { + #[doc = "TIMx_APRR register is not buffered"] + pub const DISABLED: Self = Self(0); + #[doc = "TIMx_APRR register is buffered"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ossi(pub u8); + impl Ossi { + #[doc = "When inactive, OC/OCN outputs are disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "When inactive, OC/OCN outputs are forced to idle level"] + pub const IDLELEVEL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ts(pub u8); + impl Ts { + #[doc = "Internal Trigger 0 (ITR0)"] + pub const ITR0: Self = Self(0); + #[doc = "Internal Trigger 1 (ITR1)"] + pub const ITR1: Self = Self(0x01); + #[doc = "Internal Trigger 2 (ITR2)"] + pub const ITR2: Self = Self(0x02); + #[doc = "TI1 Edge Detector (TI1F_ED)"] + pub const TI1F_ED: Self = Self(0x04); + #[doc = "Filtered Timer Input 1 (TI1FP1)"] + pub const TI1FP1: Self = Self(0x05); + #[doc = "Filtered Timer Input 2 (TI2FP2)"] + pub const TI2FP2: Self = Self(0x06); + #[doc = "External Trigger input (ETRF)"] + pub const ETRF: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Counter used as upcounter"] + pub const UP: Self = Self(0); + #[doc = "Counter used as downcounter"] + pub const DOWN: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mms(pub u8); + impl Mms { + #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"] + pub const RESET: Self = Self(0); + #[doc = "The counter enable signal, CNT_EN, is used as trigger output"] + pub const ENABLE: Self = Self(0x01); + #[doc = "The update event is selected as trigger output"] + pub const UPDATE: Self = Self(0x02); + #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"] + pub const COMPAREPULSE: Self = Self(0x03); + #[doc = "OC1REF signal is used as trigger output"] + pub const COMPAREOC1: Self = Self(0x04); + #[doc = "OC2REF signal is used as trigger output"] + pub const COMPAREOC2: Self = Self(0x05); + #[doc = "OC3REF signal is used as trigger output"] + pub const COMPAREOC3: Self = Self(0x06); + #[doc = "OC4REF signal is used as trigger output"] + pub const COMPAREOC4: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Sms(pub u8); + impl Sms { + #[doc = "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] + pub const DISABLED: Self = Self(0); + #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."] + pub const ENCODER_MODE_1: Self = Self(0x01); + #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."] + pub const ENCODER_MODE_2: Self = Self(0x02); + #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."] + pub const ENCODER_MODE_3: Self = Self(0x03); + #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."] + pub const RESET_MODE: Self = Self(0x04); + #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."] + pub const GATED_MODE: Self = Self(0x05); + #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."] + pub const TRIGGER_MODE: Self = Self(0x06); + #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."] + pub const EXT_CLOCK_MODE: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ckd(pub u8); + impl Ckd { + #[doc = "t_DTS = t_CK_INT"] + pub const DIV1: Self = Self(0); + #[doc = "t_DTS = 2 × t_CK_INT"] + pub const DIV2: Self = Self(0x01); + #[doc = "t_DTS = 4 × t_CK_INT"] + pub const DIV4: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ece(pub u8); + impl Ece { + #[doc = "External clock mode 2 disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct CcmrOutputCcs(pub u8); + impl CcmrOutputCcs { + #[doc = "CCx channel is configured as output"] + pub const OUTPUT: Self = Self(0); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etf(pub u8); + impl Etf { + #[doc = "No filter, sampling is done at fDTS"] + pub const NOFILTER: Self = Self(0); + #[doc = "fSAMPLING=fCK_INT, N=2"] + pub const FCK_INT_N2: Self = Self(0x01); + #[doc = "fSAMPLING=fCK_INT, N=4"] + pub const FCK_INT_N4: Self = Self(0x02); + #[doc = "fSAMPLING=fCK_INT, N=8"] + pub const FCK_INT_N8: Self = Self(0x03); + #[doc = "fSAMPLING=fDTS/2, N=6"] + pub const FDTS_DIV2_N6: Self = Self(0x04); + #[doc = "fSAMPLING=fDTS/2, N=8"] + pub const FDTS_DIV2_N8: Self = Self(0x05); + #[doc = "fSAMPLING=fDTS/4, N=6"] + pub const FDTS_DIV4_N6: Self = Self(0x06); + #[doc = "fSAMPLING=fDTS/4, N=8"] + pub const FDTS_DIV4_N8: Self = Self(0x07); + #[doc = "fSAMPLING=fDTS/8, N=6"] + pub const FDTS_DIV8_N6: Self = Self(0x08); + #[doc = "fSAMPLING=fDTS/8, N=8"] + pub const FDTS_DIV8_N8: Self = Self(0x09); + #[doc = "fSAMPLING=fDTS/16, N=5"] + pub const FDTS_DIV16_N5: Self = Self(0x0a); + #[doc = "fSAMPLING=fDTS/16, N=6"] + pub const FDTS_DIV16_N6: Self = Self(0x0b); + #[doc = "fSAMPLING=fDTS/16, N=8"] + pub const FDTS_DIV16_N8: Self = Self(0x0c); + #[doc = "fSAMPLING=fDTS/32, N=5"] + pub const FDTS_DIV32_N5: Self = Self(0x0d); + #[doc = "fSAMPLING=fDTS/32, N=6"] + pub const FDTS_DIV32_N6: Self = Self(0x0e); + #[doc = "fSAMPLING=fDTS/32, N=8"] + pub const FDTS_DIV32_N8: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etp(pub u8); + impl Etp { + #[doc = "ETR is noninverted, active at high level or rising edge"] + pub const NOTINVERTED: Self = Self(0); + #[doc = "ETR is inverted, active at low level or falling edge"] + pub const INVERTED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Icf(pub u8); + impl Icf { + #[doc = "No filter, sampling is done at fDTS"] + pub const NOFILTER: Self = Self(0); + #[doc = "fSAMPLING=fCK_INT, N=2"] + pub const FCK_INT_N2: Self = Self(0x01); + #[doc = "fSAMPLING=fCK_INT, N=4"] + pub const FCK_INT_N4: Self = Self(0x02); + #[doc = "fSAMPLING=fCK_INT, N=8"] + pub const FCK_INT_N8: Self = Self(0x03); + #[doc = "fSAMPLING=fDTS/2, N=6"] + pub const FDTS_DIV2_N6: Self = Self(0x04); + #[doc = "fSAMPLING=fDTS/2, N=8"] + pub const FDTS_DIV2_N8: Self = Self(0x05); + #[doc = "fSAMPLING=fDTS/4, N=6"] + pub const FDTS_DIV4_N6: Self = Self(0x06); + #[doc = "fSAMPLING=fDTS/4, N=8"] + pub const FDTS_DIV4_N8: Self = Self(0x07); + #[doc = "fSAMPLING=fDTS/8, N=6"] + pub const FDTS_DIV8_N6: Self = Self(0x08); + #[doc = "fSAMPLING=fDTS/8, N=8"] + pub const FDTS_DIV8_N8: Self = Self(0x09); + #[doc = "fSAMPLING=fDTS/16, N=5"] + pub const FDTS_DIV16_N5: Self = Self(0x0a); + #[doc = "fSAMPLING=fDTS/16, N=6"] + pub const FDTS_DIV16_N6: Self = Self(0x0b); + #[doc = "fSAMPLING=fDTS/16, N=8"] + pub const FDTS_DIV16_N8: Self = Self(0x0c); + #[doc = "fSAMPLING=fDTS/32, N=5"] + pub const FDTS_DIV32_N5: Self = Self(0x0d); + #[doc = "fSAMPLING=fDTS/32, N=6"] + pub const FDTS_DIV32_N6: Self = Self(0x0e); + #[doc = "fSAMPLING=fDTS/32, N=8"] + pub const FDTS_DIV32_N8: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct CcmrInputCcs(pub u8); + impl CcmrInputCcs { + #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"] + pub const TI4: Self = Self(0x01); + #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"] + pub const TI3: Self = Self(0x02); + #[doc = "CCx channel is configured as input, ICx is mapped on TRC"] + pub const TRC: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ocpe(pub u8); + impl Ocpe { + #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"] + pub const DISABLED: Self = Self(0); + #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ccds(pub u8); + impl Ccds { + #[doc = "CCx DMA request sent when CCx event occurs"] + pub const ONCOMPARE: Self = Self(0); + #[doc = "CCx DMA request sent when update event occurs"] + pub const ONUPDATE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ossr(pub u8); + impl Ossr { + #[doc = "When inactive, OC/OCN outputs are disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"] + pub const IDLELEVEL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cms(pub u8); + impl Cms { + #[doc = "The counter counts up or down depending on the direction bit"] + pub const EDGEALIGNED: Self = Self(0); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] + pub const CENTERALIGNED1: Self = Self(0x01); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] + pub const CENTERALIGNED2: Self = Self(0x02); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] + pub const CENTERALIGNED3: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etps(pub u8); + impl Etps { + #[doc = "Prescaler OFF"] + pub const DIV1: Self = Self(0); + #[doc = "ETRP frequency divided by 2"] + pub const DIV2: Self = Self(0x01); + #[doc = "ETRP frequency divided by 4"] + pub const DIV4: Self = Self(0x02); + #[doc = "ETRP frequency divided by 8"] + pub const DIV8: Self = Self(0x03); + } + } +} +pub mod gpio_v2 { + use crate::generic::*; + #[doc = "General-purpose I/Os"] + #[derive(Copy, Clone)] + pub struct Gpio(pub *mut u8); + unsafe impl Send for Gpio {} + unsafe impl Sync for Gpio {} + impl Gpio { + #[doc = "GPIO port mode register"] + pub fn moder(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "GPIO port output type register"] + pub fn otyper(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "GPIO port output speed register"] + pub fn ospeedr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "GPIO port pull-up/pull-down register"] + pub fn pupdr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "GPIO port input data register"] + pub fn idr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "GPIO port output data register"] + pub fn odr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "GPIO port bit set/reset register"] + pub fn bsrr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + #[doc = "GPIO port configuration lock register"] + pub fn lckr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(28usize)) } + } + #[doc = "GPIO alternate function register (low, high)"] + pub fn afr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(32usize + n * 4usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "GPIO port input data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idr(pub u32); + impl Idr { + #[doc = "Port input data (y = 0..15)"] + pub fn idr(&self, n: usize) -> super::vals::Idr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Idr(val as u8) + } + #[doc = "Port input data (y = 0..15)"] + pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Idr { + fn default() -> Idr { + Idr(0) + } + } + #[doc = "GPIO port pull-up/pull-down register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pupdr(pub u32); + impl Pupdr { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn pupdr(&self, n: usize) -> super::vals::Pupdr { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Pupdr(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_pupdr(&mut self, n: usize, val: super::vals::Pupdr) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Pupdr { + fn default() -> Pupdr { + Pupdr(0) + } + } + #[doc = "GPIO port output type register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Otyper(pub u32); + impl Otyper { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn ot(&self, n: usize) -> super::vals::Ot { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Ot(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_ot(&mut self, n: usize, val: super::vals::Ot) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Otyper { + fn default() -> Otyper { + Otyper(0) + } + } + #[doc = "GPIO alternate function register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Afr(pub u32); + impl Afr { + #[doc = "Alternate function selection for port x bit y (y = 0..15)"] + pub fn afr(&self, n: usize) -> super::vals::Afr { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + super::vals::Afr(val as u8) + } + #[doc = "Alternate function selection for port x bit y (y = 0..15)"] + pub fn set_afr(&mut self, n: usize, val: super::vals::Afr) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); + } + } + impl Default for Afr { + fn default() -> Afr { + Afr(0) + } + } + #[doc = "GPIO port configuration lock register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Lckr(pub u32); + impl Lckr { + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn lck(&self, n: usize) -> super::vals::Lck { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Lck(val as u8) + } + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Port x lock bit y (y= 0..15)"] + pub const fn lckk(&self) -> super::vals::Lckk { + let val = (self.0 >> 16usize) & 0x01; + super::vals::Lckk(val as u8) + } + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn set_lckk(&mut self, val: super::vals::Lckk) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); + } + } + impl Default for Lckr { + fn default() -> Lckr { + Lckr(0) + } + } + #[doc = "GPIO port bit set/reset register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Bsrr(pub u32); + impl Bsrr { + #[doc = "Port x set bit y (y= 0..15)"] + pub fn bs(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Port x set bit y (y= 0..15)"] + pub fn set_bs(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Port x set bit y (y= 0..15)"] + pub fn br(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Port x set bit y (y= 0..15)"] + pub fn set_br(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Bsrr { + fn default() -> Bsrr { + Bsrr(0) + } + } + #[doc = "GPIO port output data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Odr(pub u32); + impl Odr { + #[doc = "Port output data (y = 0..15)"] + pub fn odr(&self, n: usize) -> super::vals::Odr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Odr(val as u8) + } + #[doc = "Port output data (y = 0..15)"] + pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Odr { + fn default() -> Odr { + Odr(0) + } + } + #[doc = "GPIO port output speed register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ospeedr(pub u32); + impl Ospeedr { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Ospeedr(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Ospeedr { + fn default() -> Ospeedr { + Ospeedr(0) + } + } + #[doc = "GPIO port mode register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Moder(pub u32); + impl Moder { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn moder(&self, n: usize) -> super::vals::Moder { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Moder(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Moder { + fn default() -> Moder { + Moder(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Brw(pub u8); + impl Brw { + #[doc = "Resets the corresponding ODRx bit"] + pub const RESET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pupdr(pub u8); + impl Pupdr { + #[doc = "No pull-up, pull-down"] + pub const FLOATING: Self = Self(0); + #[doc = "Pull-up"] + pub const PULLUP: Self = Self(0x01); + #[doc = "Pull-down"] + pub const PULLDOWN: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Odr(pub u8); + impl Odr { + #[doc = "Set output to logic low"] + pub const LOW: Self = Self(0); + #[doc = "Set output to logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ospeedr(pub u8); + impl Ospeedr { + #[doc = "Low speed"] + pub const LOWSPEED: Self = Self(0); + #[doc = "Medium speed"] + pub const MEDIUMSPEED: Self = Self(0x01); + #[doc = "High speed"] + pub const HIGHSPEED: Self = Self(0x02); + #[doc = "Very high speed"] + pub const VERYHIGHSPEED: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Idr(pub u8); + impl Idr { + #[doc = "Input is logic low"] + pub const LOW: Self = Self(0); + #[doc = "Input is logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lckk(pub u8); + impl Lckk { + #[doc = "Port configuration lock key not active"] + pub const NOTACTIVE: Self = Self(0); + #[doc = "Port configuration lock key active"] + pub const ACTIVE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Moder(pub u8); + impl Moder { + #[doc = "Input mode (reset state)"] + pub const INPUT: Self = Self(0); + #[doc = "General purpose output mode"] + pub const OUTPUT: Self = Self(0x01); + #[doc = "Alternate function mode"] + pub const ALTERNATE: Self = Self(0x02); + #[doc = "Analog mode"] + pub const ANALOG: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ot(pub u8); + impl Ot { + #[doc = "Output push-pull (reset state)"] + pub const PUSHPULL: Self = Self(0); + #[doc = "Output open-drain"] + pub const OPENDRAIN: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Afr(pub u8); + impl Afr { + #[doc = "AF0"] + pub const AF0: Self = Self(0); + #[doc = "AF1"] + pub const AF1: Self = Self(0x01); + #[doc = "AF2"] + pub const AF2: Self = Self(0x02); + #[doc = "AF3"] + pub const AF3: Self = Self(0x03); + #[doc = "AF4"] + pub const AF4: Self = Self(0x04); + #[doc = "AF5"] + pub const AF5: Self = Self(0x05); + #[doc = "AF6"] + pub const AF6: Self = Self(0x06); + #[doc = "AF7"] + pub const AF7: Self = Self(0x07); + #[doc = "AF8"] + pub const AF8: Self = Self(0x08); + #[doc = "AF9"] + pub const AF9: Self = Self(0x09); + #[doc = "AF10"] + pub const AF10: Self = Self(0x0a); + #[doc = "AF11"] + pub const AF11: Self = Self(0x0b); + #[doc = "AF12"] + pub const AF12: Self = Self(0x0c); + #[doc = "AF13"] + pub const AF13: Self = Self(0x0d); + #[doc = "AF14"] + pub const AF14: Self = Self(0x0e); + #[doc = "AF15"] + pub const AF15: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bsw(pub u8); + impl Bsw { + #[doc = "Sets the corresponding ODRx bit"] + pub const SET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lck(pub u8); + impl Lck { + #[doc = "Port configuration not locked"] + pub const UNLOCKED: Self = Self(0); + #[doc = "Port configuration locked"] + pub const LOCKED: Self = Self(0x01); + } + } +} +pub mod rng_v1 { + use crate::generic::*; + #[doc = "Random number generator"] + #[derive(Copy, Clone)] + pub struct Rng(pub *mut u8); + unsafe impl Send for Rng {} + unsafe impl Sync for Rng {} + impl Rng { + #[doc = "control register"] + pub fn cr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Data ready"] + pub const fn drdy(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Data ready"] + pub fn set_drdy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Clock error current status"] + pub const fn cecs(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Clock error current status"] + pub fn set_cecs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Seed error current status"] + pub const fn secs(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Seed error current status"] + pub fn set_secs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Clock error interrupt status"] + pub const fn ceis(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Clock error interrupt status"] + pub fn set_ceis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Seed error interrupt status"] + pub const fn seis(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Seed error interrupt status"] + pub fn set_seis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + #[doc = "control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Random number generator enable"] + pub const fn rngen(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Random number generator enable"] + pub fn set_rngen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Interrupt enable"] + pub const fn ie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Interrupt enable"] + pub fn set_ie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + } +} +pub mod syscfg_l4 { + use crate::generic::*; + #[doc = "System configuration controller"] + #[derive(Copy, Clone)] + pub struct Syscfg(pub *mut u8); + unsafe impl Send for Syscfg {} + unsafe impl Sync for Syscfg {} + impl Syscfg { + #[doc = "memory remap register"] + pub fn memrmp(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "configuration register 1"] + pub fn cfgr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "external interrupt configuration register 1"] + pub fn exticr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } + } + #[doc = "SCSR"] + pub fn scsr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + #[doc = "CFGR2"] + pub fn cfgr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(28usize)) } + } + #[doc = "SWPR"] + pub fn swpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "SKR"] + pub fn skr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "external interrupt configuration register 4"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Exticr(pub u32); + impl Exticr { + #[doc = "EXTI12 configuration bits"] + pub fn exti(&self, n: usize) -> u8 { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + val as u8 + } + #[doc = "EXTI12 configuration bits"] + pub fn set_exti(&mut self, n: usize, val: u8) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); + } + } + impl Default for Exticr { + fn default() -> Exticr { + Exticr(0) + } + } + #[doc = "SKR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Skr(pub u32); + impl Skr { + #[doc = "SRAM2 write protection key for software erase"] + pub const fn key(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "SRAM2 write protection key for software erase"] + pub fn set_key(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + } + impl Default for Skr { + fn default() -> Skr { + Skr(0) + } + } + #[doc = "configuration register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cfgr1(pub u32); + impl Cfgr1 { + #[doc = "Firewall disable"] + pub const fn fwdis(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Firewall disable"] + pub fn set_fwdis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "I/O analog switch voltage booster enable"] + pub const fn boosten(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "I/O analog switch voltage booster enable"] + pub fn set_boosten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"] + pub const fn i2c_pb6_fmp(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"] + pub fn set_i2c_pb6_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"] + pub const fn i2c_pb7_fmp(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"] + pub fn set_i2c_pb7_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"] + pub const fn i2c_pb8_fmp(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"] + pub fn set_i2c_pb8_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"] + pub const fn i2c_pb9_fmp(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"] + pub fn set_i2c_pb9_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "I2C1 Fast-mode Plus driving capability activation"] + pub const fn i2c1_fmp(&self) -> bool { + let val = (self.0 >> 20usize) & 0x01; + val != 0 + } + #[doc = "I2C1 Fast-mode Plus driving capability activation"] + pub fn set_i2c1_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); + } + #[doc = "I2C2 Fast-mode Plus driving capability activation"] + pub const fn i2c2_fmp(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "I2C2 Fast-mode Plus driving capability activation"] + pub fn set_i2c2_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "I2C3 Fast-mode Plus driving capability activation"] + pub const fn i2c3_fmp(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "I2C3 Fast-mode Plus driving capability activation"] + pub fn set_i2c3_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "Floating Point Unit interrupts enable bits"] + pub const fn fpu_ie(&self) -> u8 { + let val = (self.0 >> 26usize) & 0x3f; + val as u8 + } + #[doc = "Floating Point Unit interrupts enable bits"] + pub fn set_fpu_ie(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 26usize)) | (((val as u32) & 0x3f) << 26usize); + } + } + impl Default for Cfgr1 { + fn default() -> Cfgr1 { + Cfgr1(0) + } + } + #[doc = "memory remap register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Memrmp(pub u32); + impl Memrmp { + #[doc = "Memory mapping selection"] + pub const fn mem_mode(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x07; + val as u8 + } + #[doc = "Memory mapping selection"] + pub fn set_mem_mode(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); + } + #[doc = "QUADSPI memory mapping swap"] + pub const fn qfs(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "QUADSPI memory mapping swap"] + pub fn set_qfs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Flash Bank mode selection"] + pub const fn fb_mode(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Flash Bank mode selection"] + pub fn set_fb_mode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Memrmp { + fn default() -> Memrmp { + Memrmp(0) + } + } + #[doc = "SWPR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Swpr(pub u32); + impl Swpr { + #[doc = "SRAWM2 write protection."] + pub fn pwp(&self, n: usize) -> bool { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "SRAWM2 write protection."] + pub fn set_pwp(&mut self, n: usize, val: bool) { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Swpr { + fn default() -> Swpr { + Swpr(0) + } + } + #[doc = "CFGR2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cfgr2(pub u32); + impl Cfgr2 { + #[doc = "Cortex LOCKUP (Hardfault) output enable bit"] + pub const fn cll(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Cortex LOCKUP (Hardfault) output enable bit"] + pub fn set_cll(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "SRAM2 parity lock bit"] + pub const fn spl(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 parity lock bit"] + pub fn set_spl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "PVD lock enable bit"] + pub const fn pvdl(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "PVD lock enable bit"] + pub fn set_pvdl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "ECC Lock"] + pub const fn eccl(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "ECC Lock"] + pub fn set_eccl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "SRAM2 parity error flag"] + pub const fn spf(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 parity error flag"] + pub fn set_spf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Cfgr2 { + fn default() -> Cfgr2 { + Cfgr2(0) + } + } + #[doc = "SCSR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Scsr(pub u32); + impl Scsr { + #[doc = "SRAM2 Erase"] + pub const fn sram2er(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 Erase"] + pub fn set_sram2er(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "SRAM2 busy by erase operation"] + pub const fn sram2bsy(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 busy by erase operation"] + pub fn set_sram2bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + } + impl Default for Scsr { + fn default() -> Scsr { + Scsr(0) + } + } + } +} +pub mod usart_v1 { + use crate::generic::*; + #[doc = "Universal asynchronous receiver transmitter"] + #[derive(Copy, Clone)] + pub struct Uart(pub *mut u8); + unsafe impl Send for Uart {} + unsafe impl Sync for Uart {} + impl Uart { + #[doc = "Status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Baud rate register"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Control register 3"] + pub fn cr3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + } + #[doc = "Universal synchronous asynchronous receiver transmitter"] + #[derive(Copy, Clone)] + pub struct Usart(pub *mut u8); + unsafe impl Send for Usart {} + unsafe impl Sync for Usart {} + impl Usart { + #[doc = "Status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Baud rate register"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Control register 3"] + pub fn cr3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "Guard time and prescaler register"] + pub fn gtpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "Data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dr(pub u32); + impl Dr { + #[doc = "Data value"] + pub const fn dr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x01ff; + val as u16 + } + #[doc = "Data value"] + pub fn set_dr(&mut self, val: u16) { + self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize); + } + } + impl Default for Dr { + fn default() -> Dr { + Dr(0) + } + } + #[doc = "Status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Parity error"] + pub const fn pe(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Parity error"] + pub fn set_pe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Framing error"] + pub const fn fe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Framing error"] + pub fn set_fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Noise error flag"] + pub const fn ne(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Noise error flag"] + pub fn set_ne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Overrun error"] + pub const fn ore(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Overrun error"] + pub fn set_ore(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE line detected"] + pub const fn idle(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE line detected"] + pub fn set_idle(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Read data register not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Read data register not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete"] + pub const fn tc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete"] + pub fn set_tc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Transmit data register empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Transmit data register empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "LIN break detection flag"] + pub const fn lbd(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection flag"] + pub fn set_lbd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + #[doc = "Control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2(pub u32); + impl Cr2 { + #[doc = "Address of the USART node"] + pub const fn add(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Address of the USART node"] + pub fn set_add(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "lin break detection length"] + pub const fn lbdl(&self) -> super::vals::Lbdl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Lbdl(val as u8) + } + #[doc = "lin break detection length"] + pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "LIN break detection interrupt enable"] + pub const fn lbdie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection interrupt enable"] + pub fn set_lbdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "STOP bits"] + pub const fn stop(&self) -> super::vals::Stop { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Stop(val as u8) + } + #[doc = "STOP bits"] + pub fn set_stop(&mut self, val: super::vals::Stop) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "LIN mode enable"] + pub const fn linen(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "LIN mode enable"] + pub fn set_linen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for Cr2 { + fn default() -> Cr2 { + Cr2(0) + } + } + #[doc = "Control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Usart(pub u32); + impl Cr2Usart { + #[doc = "Address of the USART node"] + pub const fn add(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Address of the USART node"] + pub fn set_add(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "lin break detection length"] + pub const fn lbdl(&self) -> super::vals::Lbdl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Lbdl(val as u8) + } + #[doc = "lin break detection length"] + pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "LIN break detection interrupt enable"] + pub const fn lbdie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection interrupt enable"] + pub fn set_lbdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Last bit clock pulse"] + pub const fn lbcl(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Last bit clock pulse"] + pub fn set_lbcl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Clock phase"] + pub const fn cpha(&self) -> super::vals::Cpha { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Cpha(val as u8) + } + #[doc = "Clock phase"] + pub fn set_cpha(&mut self, val: super::vals::Cpha) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Clock polarity"] + pub const fn cpol(&self) -> super::vals::Cpol { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Cpol(val as u8) + } + #[doc = "Clock polarity"] + pub fn set_cpol(&mut self, val: super::vals::Cpol) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Clock enable"] + pub const fn clken(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Clock enable"] + pub fn set_clken(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "STOP bits"] + pub const fn stop(&self) -> super::vals::Stop { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Stop(val as u8) + } + #[doc = "STOP bits"] + pub fn set_stop(&mut self, val: super::vals::Stop) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "LIN mode enable"] + pub const fn linen(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "LIN mode enable"] + pub fn set_linen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for Cr2Usart { + fn default() -> Cr2Usart { + Cr2Usart(0) + } + } + #[doc = "Control register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr3(pub u32); + impl Cr3 { + #[doc = "Error interrupt enable"] + pub const fn eie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_eie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "IrDA mode enable"] + pub const fn iren(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "IrDA mode enable"] + pub fn set_iren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "IrDA low-power"] + pub const fn irlp(&self) -> super::vals::Irlp { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Irlp(val as u8) + } + #[doc = "IrDA low-power"] + pub fn set_irlp(&mut self, val: super::vals::Irlp) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Half-duplex selection"] + pub const fn hdsel(&self) -> super::vals::Hdsel { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Hdsel(val as u8) + } + #[doc = "Half-duplex selection"] + pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "DMA enable receiver"] + pub const fn dmar(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "DMA enable receiver"] + pub fn set_dmar(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "DMA enable transmitter"] + pub const fn dmat(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "DMA enable transmitter"] + pub fn set_dmat(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for Cr3 { + fn default() -> Cr3 { + Cr3(0) + } + } + #[doc = "Control register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr3Usart(pub u32); + impl Cr3Usart { + #[doc = "Error interrupt enable"] + pub const fn eie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_eie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "IrDA mode enable"] + pub const fn iren(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "IrDA mode enable"] + pub fn set_iren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "IrDA low-power"] + pub const fn irlp(&self) -> super::vals::Irlp { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Irlp(val as u8) + } + #[doc = "IrDA low-power"] + pub fn set_irlp(&mut self, val: super::vals::Irlp) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Half-duplex selection"] + pub const fn hdsel(&self) -> super::vals::Hdsel { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Hdsel(val as u8) + } + #[doc = "Half-duplex selection"] + pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Smartcard NACK enable"] + pub const fn nack(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Smartcard NACK enable"] + pub fn set_nack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Smartcard mode enable"] + pub const fn scen(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Smartcard mode enable"] + pub fn set_scen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "DMA enable receiver"] + pub const fn dmar(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "DMA enable receiver"] + pub fn set_dmar(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "DMA enable transmitter"] + pub const fn dmat(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "DMA enable transmitter"] + pub fn set_dmat(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "RTS enable"] + pub const fn rtse(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "RTS enable"] + pub fn set_rtse(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "CTS enable"] + pub const fn ctse(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "CTS enable"] + pub fn set_ctse(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "CTS interrupt enable"] + pub const fn ctsie(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "CTS interrupt enable"] + pub fn set_ctsie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + } + impl Default for Cr3Usart { + fn default() -> Cr3Usart { + Cr3Usart(0) + } + } + #[doc = "Status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrUsart(pub u32); + impl SrUsart { + #[doc = "Parity error"] + pub const fn pe(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Parity error"] + pub fn set_pe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Framing error"] + pub const fn fe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Framing error"] + pub fn set_fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Noise error flag"] + pub const fn ne(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Noise error flag"] + pub fn set_ne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Overrun error"] + pub const fn ore(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Overrun error"] + pub fn set_ore(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE line detected"] + pub const fn idle(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE line detected"] + pub fn set_idle(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Read data register not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Read data register not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete"] + pub const fn tc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete"] + pub fn set_tc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Transmit data register empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Transmit data register empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "LIN break detection flag"] + pub const fn lbd(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection flag"] + pub fn set_lbd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "CTS flag"] + pub const fn cts(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "CTS flag"] + pub fn set_cts(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + } + impl Default for SrUsart { + fn default() -> SrUsart { + SrUsart(0) + } + } + #[doc = "Guard time and prescaler register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Gtpr(pub u32); + impl Gtpr { + #[doc = "Prescaler value"] + pub const fn psc(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Prescaler value"] + pub fn set_psc(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Guard time value"] + pub const fn gt(&self) -> u8 { + let val = (self.0 >> 8usize) & 0xff; + val as u8 + } + #[doc = "Guard time value"] + pub fn set_gt(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); + } + } + impl Default for Gtpr { + fn default() -> Gtpr { + Gtpr(0) + } + } + #[doc = "Baud rate register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Brr(pub u32); + impl Brr { + #[doc = "fraction of USARTDIV"] + pub const fn div_fraction(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "fraction of USARTDIV"] + pub fn set_div_fraction(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "mantissa of USARTDIV"] + pub const fn div_mantissa(&self) -> u16 { + let val = (self.0 >> 4usize) & 0x0fff; + val as u16 + } + #[doc = "mantissa of USARTDIV"] + pub fn set_div_mantissa(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize); + } + } + impl Default for Brr { + fn default() -> Brr { + Brr(0) + } + } + #[doc = "Control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1(pub u32); + impl Cr1 { + #[doc = "Send break"] + pub const fn sbk(&self) -> super::vals::Sbk { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Sbk(val as u8) + } + #[doc = "Send break"] + pub fn set_sbk(&mut self, val: super::vals::Sbk) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); + } + #[doc = "Receiver wakeup"] + pub const fn rwu(&self) -> super::vals::Rwu { + let val = (self.0 >> 1usize) & 0x01; + super::vals::Rwu(val as u8) + } + #[doc = "Receiver wakeup"] + pub fn set_rwu(&mut self, val: super::vals::Rwu) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); + } + #[doc = "Receiver enable"] + pub const fn re(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Receiver enable"] + pub fn set_re(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Transmitter enable"] + pub const fn te(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Transmitter enable"] + pub fn set_te(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE interrupt enable"] + pub const fn idleie(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE interrupt enable"] + pub fn set_idleie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "RXNE interrupt enable"] + pub const fn rxneie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "RXNE interrupt enable"] + pub fn set_rxneie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "TXE interrupt enable"] + pub const fn txeie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "TXE interrupt enable"] + pub fn set_txeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "PE interrupt enable"] + pub const fn peie(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "PE interrupt enable"] + pub fn set_peie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Parity selection"] + pub const fn ps(&self) -> super::vals::Ps { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Ps(val as u8) + } + #[doc = "Parity selection"] + pub fn set_ps(&mut self, val: super::vals::Ps) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Parity control enable"] + pub const fn pce(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Parity control enable"] + pub fn set_pce(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Wakeup method"] + pub const fn wake(&self) -> super::vals::Wake { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Wake(val as u8) + } + #[doc = "Wakeup method"] + pub fn set_wake(&mut self, val: super::vals::Wake) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "Word length"] + pub const fn m(&self) -> super::vals::M { + let val = (self.0 >> 12usize) & 0x01; + super::vals::M(val as u8) + } + #[doc = "Word length"] + pub fn set_m(&mut self, val: super::vals::M) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "USART enable"] + pub const fn ue(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "USART enable"] + pub fn set_ue(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + } + impl Default for Cr1 { + fn default() -> Cr1 { + Cr1(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRST: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECOND: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Irlp(pub u8); + impl Irlp { + #[doc = "Normal mode"] + pub const NORMAL: Self = Self(0); + #[doc = "Low-power mode"] + pub const LOWPOWER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpol(pub u8); + impl Cpol { + #[doc = "Steady low value on CK pin outside transmission window"] + pub const LOW: Self = Self(0); + #[doc = "Steady high value on CK pin outside transmission window"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Stop(pub u8); + impl Stop { + #[doc = "1 stop bit"] + pub const STOP1: Self = Self(0); + #[doc = "0.5 stop bits"] + pub const STOP0P5: Self = Self(0x01); + #[doc = "2 stop bits"] + pub const STOP2: Self = Self(0x02); + #[doc = "1.5 stop bits"] + pub const STOP1P5: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lbdl(pub u8); + impl Lbdl { + #[doc = "10-bit break detection"] + pub const LBDL10: Self = Self(0); + #[doc = "11-bit break detection"] + pub const LBDL11: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ps(pub u8); + impl Ps { + #[doc = "Even parity"] + pub const EVEN: Self = Self(0); + #[doc = "Odd parity"] + pub const ODD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct M(pub u8); + impl M { + #[doc = "8 data bits"] + pub const M8: Self = Self(0); + #[doc = "9 data bits"] + pub const M9: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Sbk(pub u8); + impl Sbk { + #[doc = "No break character is transmitted"] + pub const NOBREAK: Self = Self(0); + #[doc = "Break character transmitted"] + pub const BREAK: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Hdsel(pub u8); + impl Hdsel { + #[doc = "Half duplex mode is not selected"] + pub const FULLDUPLEX: Self = Self(0); + #[doc = "Half duplex mode is selected"] + pub const HALFDUPLEX: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rwu(pub u8); + impl Rwu { + #[doc = "Receiver in active mode"] + pub const ACTIVE: Self = Self(0); + #[doc = "Receiver in mute mode"] + pub const MUTE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Wake(pub u8); + impl Wake { + #[doc = "USART wakeup on idle line"] + pub const IDLELINE: Self = Self(0); + #[doc = "USART wakeup on address mark"] + pub const ADDRESSMARK: Self = Self(0x01); + } + } +} +pub mod spi_v2 { + use crate::generic::*; + #[doc = "Serial peripheral interface"] + #[derive(Copy, Clone)] + pub struct Spi(pub *mut u8); + unsafe impl Send for Spi {} + unsafe impl Sync for Spi {} + impl Spi { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "CRC polynomial register"] + pub fn crcpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "RX CRC register"] + pub fn rxcrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "TX CRC register"] + pub fn txcrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frlvlr(pub u8); + impl Frlvlr { + #[doc = "Rx FIFO Empty"] + pub const EMPTY: Self = Self(0); + #[doc = "Rx 1/4 FIFO"] + pub const QUARTER: Self = Self(0x01); + #[doc = "Rx 1/2 FIFO"] + pub const HALF: Self = Self(0x02); + #[doc = "Rx FIFO full"] + pub const FULL: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rxonly(pub u8); + impl Rxonly { + #[doc = "Full duplex (Transmit and receive)"] + pub const FULLDUPLEX: Self = Self(0); + #[doc = "Output disabled (Receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mstr(pub u8); + impl Mstr { + #[doc = "Slave configuration"] + pub const SLAVE: Self = Self(0); + #[doc = "Master configuration"] + pub const MASTER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRSTEDGE: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECONDEDGE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frxth(pub u8); + impl Frxth { + #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"] + pub const HALF: Self = Self(0); + #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"] + pub const QUARTER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ftlvlr(pub u8); + impl Ftlvlr { + #[doc = "Tx FIFO Empty"] + pub const EMPTY: Self = Self(0); + #[doc = "Tx 1/4 FIFO"] + pub const QUARTER: Self = Self(0x01); + #[doc = "Tx 1/2 FIFO"] + pub const HALF: Self = Self(0x02); + #[doc = "Tx FIFO full"] + pub const FULL: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidioe(pub u8); + impl Bidioe { + #[doc = "Output disabled (receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0); + #[doc = "Output enabled (transmit-only mode)"] + pub const OUTPUTENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lsbfirst(pub u8); + impl Lsbfirst { + #[doc = "Data is transmitted/received with the MSB first"] + pub const MSBFIRST: Self = Self(0); + #[doc = "Data is transmitted/received with the LSB first"] + pub const LSBFIRST: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct LdmaTx(pub u8); + impl LdmaTx { + #[doc = "Number of data to transfer for transmit is even"] + pub const EVEN: Self = Self(0); + #[doc = "Number of data to transfer for transmit is odd"] + pub const ODD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Crcnext(pub u8); + impl Crcnext { + #[doc = "Next transmit value is from Tx buffer"] + pub const TXBUFFER: Self = Self(0); + #[doc = "Next transmit value is from Tx CRC register"] + pub const CRC: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ds(pub u8); + impl Ds { + #[doc = "4-bit"] + pub const FOURBIT: Self = Self(0x03); + #[doc = "5-bit"] + pub const FIVEBIT: Self = Self(0x04); + #[doc = "6-bit"] + pub const SIXBIT: Self = Self(0x05); + #[doc = "7-bit"] + pub const SEVENBIT: Self = Self(0x06); + #[doc = "8-bit"] + pub const EIGHTBIT: Self = Self(0x07); + #[doc = "9-bit"] + pub const NINEBIT: Self = Self(0x08); + #[doc = "10-bit"] + pub const TENBIT: Self = Self(0x09); + #[doc = "11-bit"] + pub const ELEVENBIT: Self = Self(0x0a); + #[doc = "12-bit"] + pub const TWELVEBIT: Self = Self(0x0b); + #[doc = "13-bit"] + pub const THIRTEENBIT: Self = Self(0x0c); + #[doc = "14-bit"] + pub const FOURTEENBIT: Self = Self(0x0d); + #[doc = "15-bit"] + pub const FIFTEENBIT: Self = Self(0x0e); + #[doc = "16-bit"] + pub const SIXTEENBIT: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct LdmaRx(pub u8); + impl LdmaRx { + #[doc = "Number of data to transfer for receive is even"] + pub const EVEN: Self = Self(0); + #[doc = "Number of data to transfer for receive is odd"] + pub const ODD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Br(pub u8); + impl Br { + #[doc = "f_PCLK / 2"] + pub const DIV2: Self = Self(0); + #[doc = "f_PCLK / 4"] + pub const DIV4: Self = Self(0x01); + #[doc = "f_PCLK / 8"] + pub const DIV8: Self = Self(0x02); + #[doc = "f_PCLK / 16"] + pub const DIV16: Self = Self(0x03); + #[doc = "f_PCLK / 32"] + pub const DIV32: Self = Self(0x04); + #[doc = "f_PCLK / 64"] + pub const DIV64: Self = Self(0x05); + #[doc = "f_PCLK / 128"] + pub const DIV128: Self = Self(0x06); + #[doc = "f_PCLK / 256"] + pub const DIV256: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Crcl(pub u8); + impl Crcl { + #[doc = "8-bit CRC length"] + pub const EIGHTBIT: Self = Self(0); + #[doc = "16-bit CRC length"] + pub const SIXTEENBIT: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frer(pub u8); + impl Frer { + #[doc = "No frame format error"] + pub const NOERROR: Self = Self(0); + #[doc = "A frame format error occurred"] + pub const ERROR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frf(pub u8); + impl Frf { + #[doc = "SPI Motorola mode"] + pub const MOTOROLA: Self = Self(0); + #[doc = "SPI TI mode"] + pub const TI: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidimode(pub u8); + impl Bidimode { + #[doc = "2-line unidirectional data mode selected"] + pub const UNIDIRECTIONAL: Self = Self(0); + #[doc = "1-line bidirectional data mode selected"] + pub const BIDIRECTIONAL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpol(pub u8); + impl Cpol { + #[doc = "CK to 0 when idle"] + pub const IDLELOW: Self = Self(0); + #[doc = "CK to 1 when idle"] + pub const IDLEHIGH: Self = Self(0x01); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1(pub u32); + impl Cr1 { + #[doc = "Clock phase"] + pub const fn cpha(&self) -> super::vals::Cpha { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Cpha(val as u8) + } + #[doc = "Clock phase"] + pub fn set_cpha(&mut self, val: super::vals::Cpha) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); + } + #[doc = "Clock polarity"] + pub const fn cpol(&self) -> super::vals::Cpol { + let val = (self.0 >> 1usize) & 0x01; + super::vals::Cpol(val as u8) + } + #[doc = "Clock polarity"] + pub fn set_cpol(&mut self, val: super::vals::Cpol) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); + } + #[doc = "Master selection"] + pub const fn mstr(&self) -> super::vals::Mstr { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Mstr(val as u8) + } + #[doc = "Master selection"] + pub fn set_mstr(&mut self, val: super::vals::Mstr) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Baud rate control"] + pub const fn br(&self) -> super::vals::Br { + let val = (self.0 >> 3usize) & 0x07; + super::vals::Br(val as u8) + } + #[doc = "Baud rate control"] + pub fn set_br(&mut self, val: super::vals::Br) { + self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); + } + #[doc = "SPI enable"] + pub const fn spe(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "SPI enable"] + pub fn set_spe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Frame format"] + pub const fn lsbfirst(&self) -> super::vals::Lsbfirst { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Lsbfirst(val as u8) + } + #[doc = "Frame format"] + pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Internal slave select"] + pub const fn ssi(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Internal slave select"] + pub fn set_ssi(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Software slave management"] + pub const fn ssm(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Software slave management"] + pub fn set_ssm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Receive only"] + pub const fn rxonly(&self) -> super::vals::Rxonly { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Rxonly(val as u8) + } + #[doc = "Receive only"] + pub fn set_rxonly(&mut self, val: super::vals::Rxonly) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "CRC length"] + pub const fn crcl(&self) -> super::vals::Crcl { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Crcl(val as u8) + } + #[doc = "CRC length"] + pub fn set_crcl(&mut self, val: super::vals::Crcl) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "CRC transfer next"] + pub const fn crcnext(&self) -> super::vals::Crcnext { + let val = (self.0 >> 12usize) & 0x01; + super::vals::Crcnext(val as u8) + } + #[doc = "CRC transfer next"] + pub fn set_crcnext(&mut self, val: super::vals::Crcnext) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "Hardware CRC calculation enable"] + pub const fn crcen(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Hardware CRC calculation enable"] + pub fn set_crcen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Output enable in bidirectional mode"] + pub const fn bidioe(&self) -> super::vals::Bidioe { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Bidioe(val as u8) + } + #[doc = "Output enable in bidirectional mode"] + pub fn set_bidioe(&mut self, val: super::vals::Bidioe) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + #[doc = "Bidirectional data mode enable"] + pub const fn bidimode(&self) -> super::vals::Bidimode { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Bidimode(val as u8) + } + #[doc = "Bidirectional data mode enable"] + pub fn set_bidimode(&mut self, val: super::vals::Bidimode) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + } + impl Default for Cr1 { + fn default() -> Cr1 { + Cr1(0) + } + } + #[doc = "data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dr(pub u32); + impl Dr { + #[doc = "Data register"] + pub const fn dr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Data register"] + pub fn set_dr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Dr { + fn default() -> Dr { + Dr(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Receive buffer not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Receive buffer not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Transmit buffer empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Transmit buffer empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "CRC error flag"] + pub const fn crcerr(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "CRC error flag"] + pub fn set_crcerr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Mode fault"] + pub const fn modf(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Mode fault"] + pub fn set_modf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Overrun flag"] + pub const fn ovr(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Overrun flag"] + pub fn set_ovr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Busy flag"] + pub const fn bsy(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Busy flag"] + pub fn set_bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Frame format error"] + pub const fn fre(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Frame format error"] + pub fn set_fre(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "FIFO reception level"] + pub const fn frlvl(&self) -> u8 { + let val = (self.0 >> 9usize) & 0x03; + val as u8 + } + #[doc = "FIFO reception level"] + pub fn set_frlvl(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 9usize)) | (((val as u32) & 0x03) << 9usize); + } + #[doc = "FIFO Transmission Level"] + pub const fn ftlvl(&self) -> u8 { + let val = (self.0 >> 11usize) & 0x03; + val as u8 + } + #[doc = "FIFO Transmission Level"] + pub fn set_ftlvl(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 11usize)) | (((val as u32) & 0x03) << 11usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2(pub u32); + impl Cr2 { + #[doc = "Rx buffer DMA enable"] + pub const fn rxdmaen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Rx buffer DMA enable"] + pub fn set_rxdmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Tx buffer DMA enable"] + pub const fn txdmaen(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Tx buffer DMA enable"] + pub fn set_txdmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "SS output enable"] + pub const fn ssoe(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "SS output enable"] + pub fn set_ssoe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "NSS pulse management"] + pub const fn nssp(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "NSS pulse management"] + pub fn set_nssp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Frame format"] + pub const fn frf(&self) -> super::vals::Frf { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Frf(val as u8) + } + #[doc = "Frame format"] + pub fn set_frf(&mut self, val: super::vals::Frf) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Error interrupt enable"] + pub const fn errie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_errie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "RX buffer not empty interrupt enable"] + pub const fn rxneie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "RX buffer not empty interrupt enable"] + pub fn set_rxneie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Tx buffer empty interrupt enable"] + pub const fn txeie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Tx buffer empty interrupt enable"] + pub fn set_txeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Data size"] + pub const fn ds(&self) -> super::vals::Ds { + let val = (self.0 >> 8usize) & 0x0f; + super::vals::Ds(val as u8) + } + #[doc = "Data size"] + pub fn set_ds(&mut self, val: super::vals::Ds) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); + } + #[doc = "FIFO reception threshold"] + pub const fn frxth(&self) -> super::vals::Frxth { + let val = (self.0 >> 12usize) & 0x01; + super::vals::Frxth(val as u8) + } + #[doc = "FIFO reception threshold"] + pub fn set_frxth(&mut self, val: super::vals::Frxth) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "Last DMA transfer for reception"] + pub const fn ldma_rx(&self) -> super::vals::LdmaRx { + let val = (self.0 >> 13usize) & 0x01; + super::vals::LdmaRx(val as u8) + } + #[doc = "Last DMA transfer for reception"] + pub fn set_ldma_rx(&mut self, val: super::vals::LdmaRx) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val.0 as u32) & 0x01) << 13usize); + } + #[doc = "Last DMA transfer for transmission"] + pub const fn ldma_tx(&self) -> super::vals::LdmaTx { + let val = (self.0 >> 14usize) & 0x01; + super::vals::LdmaTx(val as u8) + } + #[doc = "Last DMA transfer for transmission"] + pub fn set_ldma_tx(&mut self, val: super::vals::LdmaTx) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + } + impl Default for Cr2 { + fn default() -> Cr2 { + Cr2(0) + } + } + #[doc = "CRC polynomial register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Crcpr(pub u32); + impl Crcpr { + #[doc = "CRC polynomial register"] + pub const fn crcpoly(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "CRC polynomial register"] + pub fn set_crcpoly(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Crcpr { + fn default() -> Crcpr { + Crcpr(0) + } + } + #[doc = "TX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Txcrcr(pub u32); + impl Txcrcr { + #[doc = "Tx CRC register"] + pub const fn tx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Tx CRC register"] + pub fn set_tx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Txcrcr { + fn default() -> Txcrcr { + Txcrcr(0) + } + } + #[doc = "RX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rxcrcr(pub u32); + impl Rxcrcr { + #[doc = "Rx CRC register"] + pub const fn rx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Rx CRC register"] + pub fn set_rx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Rxcrcr { + fn default() -> Rxcrcr { + Rxcrcr(0) + } + } + } +} +pub mod syscfg_f4 { + use crate::generic::*; + #[doc = "System configuration controller"] + #[derive(Copy, Clone)] + pub struct Syscfg(pub *mut u8); + unsafe impl Send for Syscfg {} + unsafe impl Sync for Syscfg {} + impl Syscfg { + #[doc = "memory remap register"] + pub fn memrm(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "peripheral mode configuration register"] + pub fn pmc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "external interrupt configuration register"] + pub fn exticr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } + } + #[doc = "Compensation cell control register"] + pub fn cmpcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "memory remap register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Memrm(pub u32); + impl Memrm { + #[doc = "Memory mapping selection"] + pub const fn mem_mode(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x07; + val as u8 + } + #[doc = "Memory mapping selection"] + pub fn set_mem_mode(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); + } + #[doc = "Flash bank mode selection"] + pub const fn fb_mode(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Flash bank mode selection"] + pub fn set_fb_mode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "FMC memory mapping swap"] + pub const fn swp_fmc(&self) -> u8 { + let val = (self.0 >> 10usize) & 0x03; + val as u8 + } + #[doc = "FMC memory mapping swap"] + pub fn set_swp_fmc(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize); + } + } + impl Default for Memrm { + fn default() -> Memrm { + Memrm(0) + } + } + #[doc = "external interrupt configuration register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Exticr(pub u32); + impl Exticr { + #[doc = "EXTI x configuration"] + pub fn exti(&self, n: usize) -> u8 { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + val as u8 + } + #[doc = "EXTI x configuration"] + pub fn set_exti(&mut self, n: usize, val: u8) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); + } + } + impl Default for Exticr { + fn default() -> Exticr { + Exticr(0) + } + } + #[doc = "peripheral mode configuration register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pmc(pub u32); + impl Pmc { + #[doc = "ADC1DC2"] + pub const fn adc1dc2(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "ADC1DC2"] + pub fn set_adc1dc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "ADC2DC2"] + pub const fn adc2dc2(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "ADC2DC2"] + pub fn set_adc2dc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "ADC3DC2"] + pub const fn adc3dc2(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "ADC3DC2"] + pub fn set_adc3dc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Ethernet PHY interface selection"] + pub const fn mii_rmii_sel(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Ethernet PHY interface selection"] + pub fn set_mii_rmii_sel(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + } + impl Default for Pmc { + fn default() -> Pmc { + Pmc(0) + } + } + #[doc = "Compensation cell control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cmpcr(pub u32); + impl Cmpcr { + #[doc = "Compensation cell power-down"] + pub const fn cmp_pd(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Compensation cell power-down"] + pub fn set_cmp_pd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "READY"] + pub const fn ready(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "READY"] + pub fn set_ready(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Cmpcr { + fn default() -> Cmpcr { + Cmpcr(0) + } + } + } +} +pub mod spi_v1 { + use crate::generic::*; + #[doc = "Serial peripheral interface"] + #[derive(Copy, Clone)] + pub struct Spi(pub *mut u8); + unsafe impl Send for Spi {} + unsafe impl Sync for Spi {} + impl Spi { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "CRC polynomial register"] + pub fn crcpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "RX CRC register"] + pub fn rxcrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "TX CRC register"] + pub fn txcrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lsbfirst(pub u8); + impl Lsbfirst { + #[doc = "Data is transmitted/received with the MSB first"] + pub const MSBFIRST: Self = Self(0); + #[doc = "Data is transmitted/received with the LSB first"] + pub const LSBFIRST: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Iscfg(pub u8); + impl Iscfg { + #[doc = "Slave - transmit"] + pub const SLAVETX: Self = Self(0); + #[doc = "Slave - receive"] + pub const SLAVERX: Self = Self(0x01); + #[doc = "Master - transmit"] + pub const MASTERTX: Self = Self(0x02); + #[doc = "Master - receive"] + pub const MASTERRX: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rxonly(pub u8); + impl Rxonly { + #[doc = "Full duplex (Transmit and receive)"] + pub const FULLDUPLEX: Self = Self(0); + #[doc = "Output disabled (Receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mstr(pub u8); + impl Mstr { + #[doc = "Slave configuration"] + pub const SLAVE: Self = Self(0); + #[doc = "Master configuration"] + pub const MASTER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Crcnext(pub u8); + impl Crcnext { + #[doc = "Next transmit value is from Tx buffer"] + pub const TXBUFFER: Self = Self(0); + #[doc = "Next transmit value is from Tx CRC register"] + pub const CRC: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Br(pub u8); + impl Br { + #[doc = "f_PCLK / 2"] + pub const DIV2: Self = Self(0); + #[doc = "f_PCLK / 4"] + pub const DIV4: Self = Self(0x01); + #[doc = "f_PCLK / 8"] + pub const DIV8: Self = Self(0x02); + #[doc = "f_PCLK / 16"] + pub const DIV16: Self = Self(0x03); + #[doc = "f_PCLK / 32"] + pub const DIV32: Self = Self(0x04); + #[doc = "f_PCLK / 64"] + pub const DIV64: Self = Self(0x05); + #[doc = "f_PCLK / 128"] + pub const DIV128: Self = Self(0x06); + #[doc = "f_PCLK / 256"] + pub const DIV256: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frf(pub u8); + impl Frf { + #[doc = "SPI Motorola mode"] + pub const MOTOROLA: Self = Self(0); + #[doc = "SPI TI mode"] + pub const TI: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRSTEDGE: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECONDEDGE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidioe(pub u8); + impl Bidioe { + #[doc = "Output disabled (receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0); + #[doc = "Output enabled (transmit-only mode)"] + pub const OUTPUTENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpol(pub u8); + impl Cpol { + #[doc = "CK to 0 when idle"] + pub const IDLELOW: Self = Self(0); + #[doc = "CK to 1 when idle"] + pub const IDLEHIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dff(pub u8); + impl Dff { + #[doc = "8-bit data frame format is selected for transmission/reception"] + pub const EIGHTBIT: Self = Self(0); + #[doc = "16-bit data frame format is selected for transmission/reception"] + pub const SIXTEENBIT: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frer(pub u8); + impl Frer { + #[doc = "No frame format error"] + pub const NOERROR: Self = Self(0); + #[doc = "A frame format error occurred"] + pub const ERROR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidimode(pub u8); + impl Bidimode { + #[doc = "2-line unidirectional data mode selected"] + pub const UNIDIRECTIONAL: Self = Self(0); + #[doc = "1-line bidirectional data mode selected"] + pub const BIDIRECTIONAL: Self = Self(0x01); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "CRC polynomial register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Crcpr(pub u32); + impl Crcpr { + #[doc = "CRC polynomial register"] + pub const fn crcpoly(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "CRC polynomial register"] + pub fn set_crcpoly(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Crcpr { + fn default() -> Crcpr { + Crcpr(0) + } + } + #[doc = "TX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Txcrcr(pub u32); + impl Txcrcr { + #[doc = "Tx CRC register"] + pub const fn tx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Tx CRC register"] + pub fn set_tx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Txcrcr { + fn default() -> Txcrcr { + Txcrcr(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2(pub u32); + impl Cr2 { + #[doc = "Rx buffer DMA enable"] + pub const fn rxdmaen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Rx buffer DMA enable"] + pub fn set_rxdmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Tx buffer DMA enable"] + pub const fn txdmaen(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Tx buffer DMA enable"] + pub fn set_txdmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "SS output enable"] + pub const fn ssoe(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "SS output enable"] + pub fn set_ssoe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Frame format"] + pub const fn frf(&self) -> super::vals::Frf { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Frf(val as u8) + } + #[doc = "Frame format"] + pub fn set_frf(&mut self, val: super::vals::Frf) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Error interrupt enable"] + pub const fn errie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_errie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "RX buffer not empty interrupt enable"] + pub const fn rxneie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "RX buffer not empty interrupt enable"] + pub fn set_rxneie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Tx buffer empty interrupt enable"] + pub const fn txeie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Tx buffer empty interrupt enable"] + pub fn set_txeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for Cr2 { + fn default() -> Cr2 { + Cr2(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1(pub u32); + impl Cr1 { + #[doc = "Clock phase"] + pub const fn cpha(&self) -> super::vals::Cpha { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Cpha(val as u8) + } + #[doc = "Clock phase"] + pub fn set_cpha(&mut self, val: super::vals::Cpha) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); + } + #[doc = "Clock polarity"] + pub const fn cpol(&self) -> super::vals::Cpol { + let val = (self.0 >> 1usize) & 0x01; + super::vals::Cpol(val as u8) + } + #[doc = "Clock polarity"] + pub fn set_cpol(&mut self, val: super::vals::Cpol) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); + } + #[doc = "Master selection"] + pub const fn mstr(&self) -> super::vals::Mstr { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Mstr(val as u8) + } + #[doc = "Master selection"] + pub fn set_mstr(&mut self, val: super::vals::Mstr) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Baud rate control"] + pub const fn br(&self) -> super::vals::Br { + let val = (self.0 >> 3usize) & 0x07; + super::vals::Br(val as u8) + } + #[doc = "Baud rate control"] + pub fn set_br(&mut self, val: super::vals::Br) { + self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); + } + #[doc = "SPI enable"] + pub const fn spe(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "SPI enable"] + pub fn set_spe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Frame format"] + pub const fn lsbfirst(&self) -> super::vals::Lsbfirst { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Lsbfirst(val as u8) + } + #[doc = "Frame format"] + pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Internal slave select"] + pub const fn ssi(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Internal slave select"] + pub fn set_ssi(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Software slave management"] + pub const fn ssm(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Software slave management"] + pub fn set_ssm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Receive only"] + pub const fn rxonly(&self) -> super::vals::Rxonly { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Rxonly(val as u8) + } + #[doc = "Receive only"] + pub fn set_rxonly(&mut self, val: super::vals::Rxonly) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Data frame format"] + pub const fn dff(&self) -> super::vals::Dff { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Dff(val as u8) + } + #[doc = "Data frame format"] + pub fn set_dff(&mut self, val: super::vals::Dff) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "CRC transfer next"] + pub const fn crcnext(&self) -> super::vals::Crcnext { + let val = (self.0 >> 12usize) & 0x01; + super::vals::Crcnext(val as u8) + } + #[doc = "CRC transfer next"] + pub fn set_crcnext(&mut self, val: super::vals::Crcnext) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "Hardware CRC calculation enable"] + pub const fn crcen(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Hardware CRC calculation enable"] + pub fn set_crcen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Output enable in bidirectional mode"] + pub const fn bidioe(&self) -> super::vals::Bidioe { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Bidioe(val as u8) + } + #[doc = "Output enable in bidirectional mode"] + pub fn set_bidioe(&mut self, val: super::vals::Bidioe) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + #[doc = "Bidirectional data mode enable"] + pub const fn bidimode(&self) -> super::vals::Bidimode { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Bidimode(val as u8) + } + #[doc = "Bidirectional data mode enable"] + pub fn set_bidimode(&mut self, val: super::vals::Bidimode) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + } + impl Default for Cr1 { + fn default() -> Cr1 { + Cr1(0) + } + } + #[doc = "RX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rxcrcr(pub u32); + impl Rxcrcr { + #[doc = "Rx CRC register"] + pub const fn rx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Rx CRC register"] + pub fn set_rx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Rxcrcr { + fn default() -> Rxcrcr { + Rxcrcr(0) + } + } + #[doc = "data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dr(pub u32); + impl Dr { + #[doc = "Data register"] + pub const fn dr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Data register"] + pub fn set_dr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Dr { + fn default() -> Dr { + Dr(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Receive buffer not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Receive buffer not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Transmit buffer empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Transmit buffer empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "CRC error flag"] + pub const fn crcerr(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "CRC error flag"] + pub fn set_crcerr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Mode fault"] + pub const fn modf(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Mode fault"] + pub fn set_modf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Overrun flag"] + pub const fn ovr(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Overrun flag"] + pub fn set_ovr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Busy flag"] + pub const fn bsy(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Busy flag"] + pub fn set_bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "TI frame format error"] + pub const fn fre(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "TI frame format error"] + pub fn set_fre(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + } +} +pub mod generic { + use core::marker::PhantomData; + #[derive(Copy, Clone)] + pub struct RW; + #[derive(Copy, Clone)] + pub struct R; + #[derive(Copy, Clone)] + pub struct W; + mod sealed { + use super::*; + pub trait Access {} + impl Access for R {} + impl Access for W {} + impl Access for RW {} + } + pub trait Access: sealed::Access + Copy {} + impl Access for R {} + impl Access for W {} + impl Access for RW {} + pub trait Read: Access {} + impl Read for RW {} + impl Read for R {} + pub trait Write: Access {} + impl Write for RW {} + impl Write for W {} + #[derive(Copy, Clone)] + pub struct Reg { + ptr: *mut u8, + phantom: PhantomData<*mut (T, A)>, + } + unsafe impl Send for Reg {} + unsafe impl Sync for Reg {} + impl Reg { + pub fn from_ptr(ptr: *mut u8) -> Self { + Self { + ptr, + phantom: PhantomData, + } + } + pub fn ptr(&self) -> *mut T { + self.ptr as _ + } + } + impl Reg { + pub unsafe fn read(&self) -> T { + (self.ptr as *mut T).read_volatile() + } + } + impl Reg { + pub unsafe fn write_value(&self, val: T) { + (self.ptr as *mut T).write_volatile(val) + } + } + impl Reg { + pub unsafe fn write(&self, f: impl FnOnce(&mut T) -> R) -> R { + let mut val = Default::default(); + let res = f(&mut val); + self.write_value(val); + res + } + } + impl Reg { + pub unsafe fn modify(&self, f: impl FnOnce(&mut T) -> R) -> R { + let mut val = self.read(); + let res = f(&mut val); + self.write_value(val); + res + } + } +} pub mod sdmmc_v2 { use crate::generic::*; #[doc = "SDMMC"] @@ -96,296 +7168,176 @@ pub mod sdmmc_v2 { } pub mod regs { use crate::generic::*; - #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."] + #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dctrl(pub u32); - impl Dctrl { - #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."] - pub const fn dten(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 + pub struct Dtimer(pub u32); + impl Dtimer { + #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] + pub const fn datatime(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 } - #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."] - pub fn set_dten(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] + pub fn set_datatime(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); } - #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn dtdir(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 + } + impl Default for Dtimer { + fn default() -> Dtimer { + Dtimer(0) } - #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_dtdir(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Clkcr(pub u32); + impl Clkcr { + #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] + pub const fn clkdiv(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x03ff; + val as u16 } - #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn dtmode(&self) -> u8 { - let val = (self.0 >> 2usize) & 0x03; - val as u8 + #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] + pub fn set_clkdiv(&mut self, val: u16) { + self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize); } - #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_dtmode(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize); - } - #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"] - pub const fn dblocksize(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 - } - #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"] - pub fn set_dblocksize(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); - } - #[doc = "Read wait start. If this bit is set, read wait operation starts."] - pub const fn rwstart(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Read wait start. If this bit is set, read wait operation starts."] - pub fn set_rwstart(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."] - pub const fn rwstop(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."] - pub fn set_rwstop(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn rwmod(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_rwmod(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."] - pub const fn sdioen(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."] - pub fn set_sdioen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn bootacken(&self) -> bool { + #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] + pub const fn pwrsav(&self) -> bool { let val = (self.0 >> 12usize) & 0x01; val != 0 } - #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_bootacken(&mut self, val: bool) { + #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] + pub fn set_pwrsav(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); } - #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."] - pub const fn fiforst(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; + #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub const fn widbus(&self) -> u8 { + let val = (self.0 >> 14usize) & 0x03; + val as u8 + } + #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub fn set_widbus(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize); + } + #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] + pub const fn negedge(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; val != 0 } - #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."] - pub fn set_fiforst(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] + pub fn set_negedge(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] + pub const fn hwfc_en(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] + pub fn set_hwfc_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] + pub const fn ddr(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] + pub fn set_ddr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub const fn busspeed(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub fn set_busspeed(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub const fn selclkrx(&self) -> u8 { + let val = (self.0 >> 20usize) & 0x03; + val as u8 + } + #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub fn set_selclkrx(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize); } } - impl Default for Dctrl { - fn default() -> Dctrl { - Dctrl(0) + impl Default for Clkcr { + fn default() -> Clkcr { + Clkcr(0) } } - #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."] + #[doc = "SDMMC power control register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Icr(pub u32); - impl Icr { - #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] - pub const fn ccrcfailc(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 + pub struct Power(pub u32); + impl Power { + #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."] + pub const fn pwrctrl(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x03; + val as u8 } - #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] - pub fn set_ccrcfailc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."] + pub fn set_pwrctrl(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); } - #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] - pub const fn dcrcfailc(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] - pub fn set_dcrcfailc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] - pub const fn ctimeoutc(&self) -> bool { + #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"] + pub const fn vswitch(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] - pub fn set_ctimeoutc(&mut self, val: bool) { + #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"] + pub fn set_vswitch(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] - pub const fn dtimeoutc(&self) -> bool { + #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"] + pub const fn vswitchen(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] - pub fn set_dtimeoutc(&mut self, val: bool) { + #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"] + pub fn set_vswitchen(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] - pub const fn txunderrc(&self) -> bool { + #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."] + pub const fn dirpol(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] - pub fn set_txunderrc(&mut self, val: bool) { + #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."] + pub fn set_dirpol(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] - pub const fn rxoverrc(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] - pub fn set_rxoverrc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] - pub const fn cmdrendc(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] - pub fn set_cmdrendc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] - pub const fn cmdsentc(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] - pub fn set_cmdsentc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] - pub const fn dataendc(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] - pub fn set_dataendc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] - pub const fn dholdc(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] - pub fn set_dholdc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] - pub const fn dbckendc(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] - pub fn set_dbckendc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] - pub const fn dabortc(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] - pub fn set_dabortc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] - pub const fn busyd0endc(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] - pub fn set_busyd0endc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] - pub const fn sdioitc(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] - pub fn set_sdioitc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] - pub const fn ackfailc(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] - pub fn set_ackfailc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] - pub const fn acktimeoutc(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] - pub fn set_acktimeoutc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] - pub const fn vswendc(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] - pub fn set_vswendc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] - pub const fn ckstopc(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] - pub fn set_ckstopc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] - pub const fn idmatec(&self) -> bool { - let val = (self.0 >> 27usize) & 0x01; - val != 0 - } - #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] - pub fn set_idmatec(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); - } - #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] - pub const fn idmabtcc(&self) -> bool { - let val = (self.0 >> 28usize) & 0x01; - val != 0 - } - #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] - pub fn set_idmabtcc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + impl Default for Power { + fn default() -> Power { + Power(0) } } - impl Default for Icr { - fn default() -> Icr { - Icr(0) + #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dcntr(pub u32); + impl Dcntr { + #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] + pub const fn datacount(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x01ff_ffff; + val as u32 + } + #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] + pub fn set_datacount(&mut self, val: u32) { + self.0 = + (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); + } + } + impl Default for Dcntr { + fn default() -> Dcntr { + Dcntr(0) } } #[doc = "SDMMC IP identification register"] @@ -409,67 +7361,27 @@ pub mod sdmmc_v2 { Id(0) } } - #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Resp2r(pub u32); - impl Resp2r { - #[doc = "see Table404."] - pub const fn cardstatus2(&self) -> u32 { + pub struct Idmabase1r(pub u32); + impl Idmabase1r { + #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] + pub const fn idmabase1(&self) -> u32 { let val = (self.0 >> 0usize) & 0xffff_ffff; val as u32 } - #[doc = "see Table404."] - pub fn set_cardstatus2(&mut self, val: u32) { + #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] + pub fn set_idmabase1(&mut self, val: u32) { self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); } } - impl Default for Resp2r { - fn default() -> Resp2r { - Resp2r(0) - } - } - #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Resp1r(pub u32); - impl Resp1r { - #[doc = "see Table 432"] - pub const fn cardstatus1(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "see Table 432"] - pub fn set_cardstatus1(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Resp1r { - fn default() -> Resp1r { - Resp1r(0) - } - } - #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Argr(pub u32); - impl Argr { - #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] - pub const fn cmdarg(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] - pub fn set_cmdarg(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Argr { - fn default() -> Argr { - Argr(0) + impl Default for Idmabase1r { + fn default() -> Idmabase1r { + Idmabase1r(0) } } #[doc = "SDMMC IP version register"] @@ -501,173 +7413,25 @@ pub mod sdmmc_v2 { Ver(0) } } - #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idmactrlr(pub u32); - impl Idmactrlr { - #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn idmaen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_idmaen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub const fn idmabmode(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] - pub fn set_idmabmode(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."] - pub const fn idmabact(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."] - pub fn set_idmabact(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - } - impl Default for Idmactrlr { - fn default() -> Idmactrlr { - Idmactrlr(0) - } - } #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Resp4r(pub u32); - impl Resp4r { - #[doc = "see Table404."] - pub const fn cardstatus4(&self) -> u32 { + pub struct Resp1r(pub u32); + impl Resp1r { + #[doc = "see Table 432"] + pub const fn cardstatus1(&self) -> u32 { let val = (self.0 >> 0usize) & 0xffff_ffff; val as u32 } - #[doc = "see Table404."] - pub fn set_cardstatus4(&mut self, val: u32) { + #[doc = "see Table 432"] + pub fn set_cardstatus1(&mut self, val: u32) { self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); } } - impl Default for Resp4r { - fn default() -> Resp4r { - Resp4r(0) - } - } - #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cmdr(pub u32); - impl Cmdr { - #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."] - pub const fn cmdindex(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; - val as u8 - } - #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."] - pub fn set_cmdindex(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); - } - #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."] - pub const fn cmdtrans(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."] - pub fn set_cmdtrans(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."] - pub const fn cmdstop(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."] - pub fn set_cmdstop(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."] - pub const fn waitresp(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x03; - val as u8 - } - #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."] - pub fn set_waitresp(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); - } - #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."] - pub const fn waitint(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."] - pub fn set_waitint(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."] - pub const fn waitpend(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."] - pub fn set_waitpend(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."] - pub const fn cpsmen(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."] - pub fn set_cpsmen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."] - pub const fn dthold(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."] - pub fn set_dthold(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"] - pub const fn bootmode(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"] - pub fn set_bootmode(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[doc = "Enable boot mode procedure."] - pub const fn booten(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[doc = "Enable boot mode procedure."] - pub fn set_booten(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } - #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."] - pub const fn cmdsuspend(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."] - pub fn set_cmdsuspend(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Cmdr { - fn default() -> Cmdr { - Cmdr(0) + impl Default for Resp1r { + fn default() -> Resp1r { + Resp1r(0) } } #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."] @@ -888,136 +7652,25 @@ pub mod sdmmc_v2 { Maskr(0) } } - #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."] + #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idmabase1r(pub u32); - impl Idmabase1r { - #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] -are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] - pub const fn idmabase1(&self) -> u32 { + pub struct Argr(pub u32); + impl Argr { + #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] + pub const fn cmdarg(&self) -> u32 { let val = (self.0 >> 0usize) & 0xffff_ffff; val as u32 } - #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] -are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] - pub fn set_idmabase1(&mut self, val: u32) { + #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] + pub fn set_cmdarg(&mut self, val: u32) { self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); } } - impl Default for Idmabase1r { - fn default() -> Idmabase1r { - Idmabase1r(0) - } - } - #[doc = "SDMMC power control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Power(pub u32); - impl Power { - #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."] - pub const fn pwrctrl(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x03; - val as u8 - } - #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."] - pub fn set_pwrctrl(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); - } - #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"] - pub const fn vswitch(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"] - pub fn set_vswitch(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"] - pub const fn vswitchen(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"] - pub fn set_vswitchen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."] - pub const fn dirpol(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."] - pub fn set_dirpol(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - } - impl Default for Power { - fn default() -> Power { - Power(0) - } - } - #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Acktimer(pub u32); - impl Acktimer { - #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] - pub const fn acktime(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x01ff_ffff; - val as u32 - } - #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] - pub fn set_acktime(&mut self, val: u32) { - self.0 = - (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); - } - } - impl Default for Acktimer { - fn default() -> Acktimer { - Acktimer(0) - } - } - #[doc = "SDMMC command response register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Respcmdr(pub u32); - impl Respcmdr { - #[doc = "Response command index"] - pub const fn respcmd(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; - val as u8 - } - #[doc = "Response command index"] - pub fn set_respcmd(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); - } - } - impl Default for Respcmdr { - fn default() -> Respcmdr { - Respcmdr(0) - } - } - #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Fifor(pub u32); - impl Fifor { - #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] - pub const fn fifodata(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] - pub fn set_fifodata(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Fifor { - fn default() -> Fifor { - Fifor(0) + impl Default for Argr { + fn default() -> Argr { + Argr(0) } } #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."] @@ -1041,6 +7694,260 @@ are always 0 and read only). This register can be written by firmware when DPSM Dlenr(0) } } + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Resp2r(pub u32); + impl Resp2r { + #[doc = "see Table404."] + pub const fn cardstatus2(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "see Table404."] + pub fn set_cardstatus2(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Resp2r { + fn default() -> Resp2r { + Resp2r(0) + } + } + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Resp3r(pub u32); + impl Resp3r { + #[doc = "see Table404."] + pub const fn cardstatus3(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "see Table404."] + pub fn set_cardstatus3(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Resp3r { + fn default() -> Resp3r { + Resp3r(0) + } + } + #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Icr(pub u32); + impl Icr { + #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] + pub const fn ccrcfailc(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] + pub fn set_ccrcfailc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] + pub const fn dcrcfailc(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] + pub fn set_dcrcfailc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] + pub const fn ctimeoutc(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] + pub fn set_ctimeoutc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] + pub const fn dtimeoutc(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] + pub fn set_dtimeoutc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] + pub const fn txunderrc(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] + pub fn set_txunderrc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] + pub const fn rxoverrc(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] + pub fn set_rxoverrc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] + pub const fn cmdrendc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] + pub fn set_cmdrendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] + pub const fn cmdsentc(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] + pub fn set_cmdsentc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] + pub const fn dataendc(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] + pub fn set_dataendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] + pub const fn dholdc(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] + pub fn set_dholdc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] + pub const fn dbckendc(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] + pub fn set_dbckendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] + pub const fn dabortc(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] + pub fn set_dabortc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] + pub const fn busyd0endc(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] + pub fn set_busyd0endc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] + pub const fn sdioitc(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] + pub fn set_sdioitc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] + pub const fn ackfailc(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] + pub fn set_ackfailc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] + pub const fn acktimeoutc(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] + pub fn set_acktimeoutc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] + pub const fn vswendc(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] + pub fn set_vswendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] + pub const fn ckstopc(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] + pub fn set_ckstopc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] + pub const fn idmatec(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] + pub fn set_idmatec(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] + pub const fn idmabtcc(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] + pub fn set_idmabtcc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + } + impl Default for Icr { + fn default() -> Icr { + Icr(0) + } + } + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Resp4r(pub u32); + impl Resp4r { + #[doc = "see Table404."] + pub const fn cardstatus4(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "see Table404."] + pub fn set_cardstatus4(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Resp4r { + fn default() -> Resp4r { + Resp4r(0) + } + } #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1061,6 +7968,276 @@ are always 0 and read only). This register can be written by firmware when DPSM Idmabsizer(0) } } + #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Acktimer(pub u32); + impl Acktimer { + #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] + pub const fn acktime(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x01ff_ffff; + val as u32 + } + #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] + pub fn set_acktime(&mut self, val: u32) { + self.0 = + (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); + } + } + impl Default for Acktimer { + fn default() -> Acktimer { + Acktimer(0) + } + } + #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idmactrlr(pub u32); + impl Idmactrlr { + #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn idmaen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_idmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn idmabmode(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_idmabmode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."] + pub const fn idmabact(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."] + pub fn set_idmabact(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + } + impl Default for Idmactrlr { + fn default() -> Idmactrlr { + Idmactrlr(0) + } + } + #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dctrl(pub u32); + impl Dctrl { + #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."] + pub const fn dten(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."] + pub fn set_dten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn dtdir(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_dtdir(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn dtmode(&self) -> u8 { + let val = (self.0 >> 2usize) & 0x03; + val as u8 + } + #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_dtmode(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize); + } + #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"] + pub const fn dblocksize(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"] + pub fn set_dblocksize(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + #[doc = "Read wait start. If this bit is set, read wait operation starts."] + pub const fn rwstart(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Read wait start. If this bit is set, read wait operation starts."] + pub fn set_rwstart(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."] + pub const fn rwstop(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."] + pub fn set_rwstop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn rwmod(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_rwmod(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."] + pub const fn sdioen(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."] + pub fn set_sdioen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn bootacken(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_bootacken(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."] + pub const fn fiforst(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."] + pub fn set_fiforst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + } + impl Default for Dctrl { + fn default() -> Dctrl { + Dctrl(0) + } + } + #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cmdr(pub u32); + impl Cmdr { + #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."] + pub const fn cmdindex(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x3f; + val as u8 + } + #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."] + pub fn set_cmdindex(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); + } + #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."] + pub const fn cmdtrans(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."] + pub fn set_cmdtrans(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."] + pub const fn cmdstop(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."] + pub fn set_cmdstop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."] + pub const fn waitresp(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x03; + val as u8 + } + #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."] + pub fn set_waitresp(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); + } + #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."] + pub const fn waitint(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."] + pub fn set_waitint(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."] + pub const fn waitpend(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."] + pub fn set_waitpend(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."] + pub const fn cpsmen(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."] + pub fn set_cpsmen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."] + pub const fn dthold(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."] + pub fn set_dthold(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"] + pub const fn bootmode(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"] + pub fn set_bootmode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Enable boot mode procedure."] + pub const fn booten(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Enable boot mode procedure."] + pub fn set_booten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."] + pub const fn cmdsuspend(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."] + pub fn set_cmdsuspend(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Cmdr { + fn default() -> Cmdr { + Cmdr(0) + } + } #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1333,87 +8510,45 @@ are always 0 and read only). This register can be written by firmware when DPSM Star(0) } } - #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."] + #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Clkcr(pub u32); - impl Clkcr { - #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] - pub const fn clkdiv(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x03ff; - val as u16 + pub struct Fifor(pub u32); + impl Fifor { + #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] + pub const fn fifodata(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 } - #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] - pub fn set_clkdiv(&mut self, val: u16) { - self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize); - } - #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] - pub const fn pwrsav(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] - pub fn set_pwrsav(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub const fn widbus(&self) -> u8 { - let val = (self.0 >> 14usize) & 0x03; - val as u8 - } - #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub fn set_widbus(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize); - } - #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] - pub const fn negedge(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] - pub fn set_negedge(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] - pub const fn hwfc_en(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] - pub fn set_hwfc_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] - pub const fn ddr(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] - pub fn set_ddr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub const fn busspeed(&self) -> bool { - let val = (self.0 >> 19usize) & 0x01; - val != 0 - } - #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub fn set_busspeed(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); - } - #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub const fn selclkrx(&self) -> u8 { - let val = (self.0 >> 20usize) & 0x03; - val as u8 - } - #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] - pub fn set_selclkrx(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize); + #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] + pub fn set_fifodata(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); } } - impl Default for Clkcr { - fn default() -> Clkcr { - Clkcr(0) + impl Default for Fifor { + fn default() -> Fifor { + Fifor(0) + } + } + #[doc = "SDMMC command response register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Respcmdr(pub u32); + impl Respcmdr { + #[doc = "Response command index"] + pub const fn respcmd(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x3f; + val as u8 + } + #[doc = "Response command index"] + pub fn set_respcmd(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); + } + } + impl Default for Respcmdr { + fn default() -> Respcmdr { + Respcmdr(0) } } #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."] @@ -1439,2063 +8574,6 @@ are always 0 and read only). This register can be written by firmware when DPSM Idmabase0r(0) } } - #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dcntr(pub u32); - impl Dcntr { - #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] - pub const fn datacount(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x01ff_ffff; - val as u32 - } - #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] - pub fn set_datacount(&mut self, val: u32) { - self.0 = - (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); - } - } - impl Default for Dcntr { - fn default() -> Dcntr { - Dcntr(0) - } - } - #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Resp3r(pub u32); - impl Resp3r { - #[doc = "see Table404."] - pub const fn cardstatus3(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "see Table404."] - pub fn set_cardstatus3(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Resp3r { - fn default() -> Resp3r { - Resp3r(0) - } - } - #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dtimer(pub u32); - impl Dtimer { - #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] - pub const fn datatime(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] - pub fn set_datatime(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Dtimer { - fn default() -> Dtimer { - Dtimer(0) - } - } - } -} -pub mod timer_v1 { - use crate::generic::*; - #[doc = "General purpose 32-bit timer"] - #[derive(Copy, Clone)] - pub struct TimGp32(pub *mut u8); - unsafe impl Send for TimGp32 {} - unsafe impl Sync for TimGp32 {} - impl TimGp32 { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "slave mode control register"] - pub fn smcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "DMA/Interrupt enable register"] - pub fn dier(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "event generation register"] - pub fn egr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "capture/compare mode register 1 (input mode)"] - pub fn ccmr_input(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare mode register 1 (output mode)"] - pub fn ccmr_output(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare enable register"] - pub fn ccer(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(32usize)) } - } - #[doc = "counter"] - pub fn cnt(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - #[doc = "prescaler"] - pub fn psc(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(40usize)) } - } - #[doc = "auto-reload register"] - pub fn arr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(44usize)) } - } - #[doc = "capture/compare register"] - pub fn ccr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } - } - #[doc = "DMA control register"] - pub fn dcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(72usize)) } - } - #[doc = "DMA address for full transfer"] - pub fn dmar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(76usize)) } - } - } - #[doc = "Basic timer"] - #[derive(Copy, Clone)] - pub struct TimBasic(pub *mut u8); - unsafe impl Send for TimBasic {} - unsafe impl Sync for TimBasic {} - impl TimBasic { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "DMA/Interrupt enable register"] - pub fn dier(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "event generation register"] - pub fn egr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "counter"] - pub fn cnt(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - #[doc = "prescaler"] - pub fn psc(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(40usize)) } - } - #[doc = "auto-reload register"] - pub fn arr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(44usize)) } - } - } - #[doc = "General purpose 16-bit timer"] - #[derive(Copy, Clone)] - pub struct TimGp16(pub *mut u8); - unsafe impl Send for TimGp16 {} - unsafe impl Sync for TimGp16 {} - impl TimGp16 { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "slave mode control register"] - pub fn smcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "DMA/Interrupt enable register"] - pub fn dier(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "event generation register"] - pub fn egr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "capture/compare mode register 1 (input mode)"] - pub fn ccmr_input(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare mode register 1 (output mode)"] - pub fn ccmr_output(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare enable register"] - pub fn ccer(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(32usize)) } - } - #[doc = "counter"] - pub fn cnt(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - #[doc = "prescaler"] - pub fn psc(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(40usize)) } - } - #[doc = "auto-reload register"] - pub fn arr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(44usize)) } - } - #[doc = "capture/compare register"] - pub fn ccr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } - } - #[doc = "DMA control register"] - pub fn dcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(72usize)) } - } - #[doc = "DMA address for full transfer"] - pub fn dmar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(76usize)) } - } - } - #[doc = "Advanced-timers"] - #[derive(Copy, Clone)] - pub struct TimAdv(pub *mut u8); - unsafe impl Send for TimAdv {} - unsafe impl Sync for TimAdv {} - impl TimAdv { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "slave mode control register"] - pub fn smcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "DMA/Interrupt enable register"] - pub fn dier(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "event generation register"] - pub fn egr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "capture/compare mode register 1 (input mode)"] - pub fn ccmr_input(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare mode register 1 (output mode)"] - pub fn ccmr_output(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } - } - #[doc = "capture/compare enable register"] - pub fn ccer(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(32usize)) } - } - #[doc = "counter"] - pub fn cnt(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - #[doc = "prescaler"] - pub fn psc(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(40usize)) } - } - #[doc = "auto-reload register"] - pub fn arr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(44usize)) } - } - #[doc = "repetition counter register"] - pub fn rcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(48usize)) } - } - #[doc = "capture/compare register"] - pub fn ccr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } - } - #[doc = "break and dead-time register"] - pub fn bdtr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(68usize)) } - } - #[doc = "DMA control register"] - pub fn dcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(72usize)) } - } - #[doc = "DMA address for full transfer"] - pub fn dmar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(76usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2Gp(pub u32); - impl Cr2Gp { - #[doc = "Capture/compare DMA selection"] - pub const fn ccds(&self) -> super::vals::Ccds { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Ccds(val as u8) - } - #[doc = "Capture/compare DMA selection"] - pub fn set_ccds(&mut self, val: super::vals::Ccds) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Master mode selection"] - pub const fn mms(&self) -> super::vals::Mms { - let val = (self.0 >> 4usize) & 0x07; - super::vals::Mms(val as u8) - } - #[doc = "Master mode selection"] - pub fn set_mms(&mut self, val: super::vals::Mms) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); - } - #[doc = "TI1 selection"] - pub const fn ti1s(&self) -> super::vals::Tis { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Tis(val as u8) - } - #[doc = "TI1 selection"] - pub fn set_ti1s(&mut self, val: super::vals::Tis) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - } - impl Default for Cr2Gp { - fn default() -> Cr2Gp { - Cr2Gp(0) - } - } - #[doc = "capture/compare mode register 1 (input mode)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcmrInput(pub u32); - impl CcmrInput { - #[doc = "Capture/Compare 1 selection"] - pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs { - assert!(n < 2usize); - let offs = 0usize + n * 8usize; - let val = (self.0 >> offs) & 0x03; - super::vals::CcmrInputCcs(val as u8) - } - #[doc = "Capture/Compare 1 selection"] - pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) { - assert!(n < 2usize); - let offs = 0usize + n * 8usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - #[doc = "Input capture 1 prescaler"] - pub fn icpsc(&self, n: usize) -> u8 { - assert!(n < 2usize); - let offs = 2usize + n * 8usize; - let val = (self.0 >> offs) & 0x03; - val as u8 - } - #[doc = "Input capture 1 prescaler"] - pub fn set_icpsc(&mut self, n: usize, val: u8) { - assert!(n < 2usize); - let offs = 2usize + n * 8usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs); - } - #[doc = "Input capture 1 filter"] - pub fn icf(&self, n: usize) -> super::vals::Icf { - assert!(n < 2usize); - let offs = 4usize + n * 8usize; - let val = (self.0 >> offs) & 0x0f; - super::vals::Icf(val as u8) - } - #[doc = "Input capture 1 filter"] - pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) { - assert!(n < 2usize); - let offs = 4usize + n * 8usize; - self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); - } - } - impl Default for CcmrInput { - fn default() -> CcmrInput { - CcmrInput(0) - } - } - #[doc = "DMA/Interrupt enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct DierAdv(pub u32); - impl DierAdv { - #[doc = "Update interrupt enable"] - pub const fn uie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt enable"] - pub fn set_uie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/Compare 1 interrupt enable"] - pub fn ccie(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 interrupt enable"] - pub fn set_ccie(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "COM interrupt enable"] - pub const fn comie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "COM interrupt enable"] - pub fn set_comie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger interrupt enable"] - pub const fn tie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger interrupt enable"] - pub fn set_tie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break interrupt enable"] - pub const fn bie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break interrupt enable"] - pub fn set_bie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Update DMA request enable"] - pub const fn ude(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Update DMA request enable"] - pub fn set_ude(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Capture/Compare 1 DMA request enable"] - pub fn ccde(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 DMA request enable"] - pub fn set_ccde(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "COM DMA request enable"] - pub const fn comde(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "COM DMA request enable"] - pub fn set_comde(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[doc = "Trigger DMA request enable"] - pub const fn tde(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Trigger DMA request enable"] - pub fn set_tde(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - } - impl Default for DierAdv { - fn default() -> DierAdv { - DierAdv(0) - } - } - #[doc = "prescaler"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Psc(pub u32); - impl Psc { - #[doc = "Prescaler value"] - pub const fn psc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Prescaler value"] - pub fn set_psc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Psc { - fn default() -> Psc { - Psc(0) - } - } - #[doc = "event generation register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct EgrAdv(pub u32); - impl EgrAdv { - #[doc = "Update generation"] - pub const fn ug(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update generation"] - pub fn set_ug(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare 1 generation"] - pub fn ccg(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/compare 1 generation"] - pub fn set_ccg(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare control update generation"] - pub const fn comg(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Capture/Compare control update generation"] - pub fn set_comg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger generation"] - pub const fn tg(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger generation"] - pub fn set_tg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break generation"] - pub const fn bg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break generation"] - pub fn set_bg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - } - impl Default for EgrAdv { - fn default() -> EgrAdv { - EgrAdv(0) - } - } - #[doc = "capture/compare mode register 2 (output mode)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcmrOutput(pub u32); - impl CcmrOutput { - #[doc = "Capture/Compare 3 selection"] - pub fn ccs(&self, n: usize) -> super::vals::CcmrOutputCcs { - assert!(n < 2usize); - let offs = 0usize + n * 8usize; - let val = (self.0 >> offs) & 0x03; - super::vals::CcmrOutputCcs(val as u8) - } - #[doc = "Capture/Compare 3 selection"] - pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrOutputCcs) { - assert!(n < 2usize); - let offs = 0usize + n * 8usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - #[doc = "Output compare 3 fast enable"] - pub fn ocfe(&self, n: usize) -> bool { - assert!(n < 2usize); - let offs = 2usize + n * 8usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Output compare 3 fast enable"] - pub fn set_ocfe(&mut self, n: usize, val: bool) { - assert!(n < 2usize); - let offs = 2usize + n * 8usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Output compare 3 preload enable"] - pub fn ocpe(&self, n: usize) -> super::vals::Ocpe { - assert!(n < 2usize); - let offs = 3usize + n * 8usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Ocpe(val as u8) - } - #[doc = "Output compare 3 preload enable"] - pub fn set_ocpe(&mut self, n: usize, val: super::vals::Ocpe) { - assert!(n < 2usize); - let offs = 3usize + n * 8usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - #[doc = "Output compare 3 mode"] - pub fn ocm(&self, n: usize) -> super::vals::Ocm { - assert!(n < 2usize); - let offs = 4usize + n * 8usize; - let val = (self.0 >> offs) & 0x07; - super::vals::Ocm(val as u8) - } - #[doc = "Output compare 3 mode"] - pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) { - assert!(n < 2usize); - let offs = 4usize + n * 8usize; - self.0 = (self.0 & !(0x07 << offs)) | (((val.0 as u32) & 0x07) << offs); - } - #[doc = "Output compare 3 clear enable"] - pub fn occe(&self, n: usize) -> bool { - assert!(n < 2usize); - let offs = 7usize + n * 8usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Output compare 3 clear enable"] - pub fn set_occe(&mut self, n: usize, val: bool) { - assert!(n < 2usize); - let offs = 7usize + n * 8usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for CcmrOutput { - fn default() -> CcmrOutput { - CcmrOutput(0) - } - } - #[doc = "auto-reload register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Arr32(pub u32); - impl Arr32 { - #[doc = "Auto-reload value"] - pub const fn arr(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Auto-reload value"] - pub fn set_arr(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Arr32 { - fn default() -> Arr32 { - Arr32(0) - } - } - #[doc = "control register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1Basic(pub u32); - impl Cr1Basic { - #[doc = "Counter enable"] - pub const fn cen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Counter enable"] - pub fn set_cen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Update disable"] - pub const fn udis(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Update disable"] - pub fn set_udis(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Update request source"] - pub const fn urs(&self) -> super::vals::Urs { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Urs(val as u8) - } - #[doc = "Update request source"] - pub fn set_urs(&mut self, val: super::vals::Urs) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "One-pulse mode"] - pub const fn opm(&self) -> super::vals::Opm { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Opm(val as u8) - } - #[doc = "One-pulse mode"] - pub fn set_opm(&mut self, val: super::vals::Opm) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Auto-reload preload enable"] - pub const fn arpe(&self) -> super::vals::Arpe { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Arpe(val as u8) - } - #[doc = "Auto-reload preload enable"] - pub fn set_arpe(&mut self, val: super::vals::Arpe) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - } - impl Default for Cr1Basic { - fn default() -> Cr1Basic { - Cr1Basic(0) - } - } - #[doc = "DMA control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dcr(pub u32); - impl Dcr { - #[doc = "DMA base address"] - pub const fn dba(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x1f; - val as u8 - } - #[doc = "DMA base address"] - pub fn set_dba(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); - } - #[doc = "DMA burst length"] - pub const fn dbl(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x1f; - val as u8 - } - #[doc = "DMA burst length"] - pub fn set_dbl(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); - } - } - impl Default for Dcr { - fn default() -> Dcr { - Dcr(0) - } - } - #[doc = "slave mode control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Smcr(pub u32); - impl Smcr { - #[doc = "Slave mode selection"] - pub const fn sms(&self) -> super::vals::Sms { - let val = (self.0 >> 0usize) & 0x07; - super::vals::Sms(val as u8) - } - #[doc = "Slave mode selection"] - pub fn set_sms(&mut self, val: super::vals::Sms) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize); - } - #[doc = "Trigger selection"] - pub const fn ts(&self) -> super::vals::Ts { - let val = (self.0 >> 4usize) & 0x07; - super::vals::Ts(val as u8) - } - #[doc = "Trigger selection"] - pub fn set_ts(&mut self, val: super::vals::Ts) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); - } - #[doc = "Master/Slave mode"] - pub const fn msm(&self) -> super::vals::Msm { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Msm(val as u8) - } - #[doc = "Master/Slave mode"] - pub fn set_msm(&mut self, val: super::vals::Msm) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "External trigger filter"] - pub const fn etf(&self) -> super::vals::Etf { - let val = (self.0 >> 8usize) & 0x0f; - super::vals::Etf(val as u8) - } - #[doc = "External trigger filter"] - pub fn set_etf(&mut self, val: super::vals::Etf) { - self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); - } - #[doc = "External trigger prescaler"] - pub const fn etps(&self) -> super::vals::Etps { - let val = (self.0 >> 12usize) & 0x03; - super::vals::Etps(val as u8) - } - #[doc = "External trigger prescaler"] - pub fn set_etps(&mut self, val: super::vals::Etps) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); - } - #[doc = "External clock enable"] - pub const fn ece(&self) -> super::vals::Ece { - let val = (self.0 >> 14usize) & 0x01; - super::vals::Ece(val as u8) - } - #[doc = "External clock enable"] - pub fn set_ece(&mut self, val: super::vals::Ece) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); - } - #[doc = "External trigger polarity"] - pub const fn etp(&self) -> super::vals::Etp { - let val = (self.0 >> 15usize) & 0x01; - super::vals::Etp(val as u8) - } - #[doc = "External trigger polarity"] - pub fn set_etp(&mut self, val: super::vals::Etp) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); - } - } - impl Default for Smcr { - fn default() -> Smcr { - Smcr(0) - } - } - #[doc = "counter"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cnt32(pub u32); - impl Cnt32 { - #[doc = "counter value"] - pub const fn cnt(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "counter value"] - pub fn set_cnt(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Cnt32 { - fn default() -> Cnt32 { - Cnt32(0) - } - } - #[doc = "control register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1Gp(pub u32); - impl Cr1Gp { - #[doc = "Counter enable"] - pub const fn cen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Counter enable"] - pub fn set_cen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Update disable"] - pub const fn udis(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Update disable"] - pub fn set_udis(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Update request source"] - pub const fn urs(&self) -> super::vals::Urs { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Urs(val as u8) - } - #[doc = "Update request source"] - pub fn set_urs(&mut self, val: super::vals::Urs) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "One-pulse mode"] - pub const fn opm(&self) -> super::vals::Opm { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Opm(val as u8) - } - #[doc = "One-pulse mode"] - pub fn set_opm(&mut self, val: super::vals::Opm) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Direction"] - pub const fn dir(&self) -> super::vals::Dir { - let val = (self.0 >> 4usize) & 0x01; - super::vals::Dir(val as u8) - } - #[doc = "Direction"] - pub fn set_dir(&mut self, val: super::vals::Dir) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); - } - #[doc = "Center-aligned mode selection"] - pub const fn cms(&self) -> super::vals::Cms { - let val = (self.0 >> 5usize) & 0x03; - super::vals::Cms(val as u8) - } - #[doc = "Center-aligned mode selection"] - pub fn set_cms(&mut self, val: super::vals::Cms) { - self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize); - } - #[doc = "Auto-reload preload enable"] - pub const fn arpe(&self) -> super::vals::Arpe { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Arpe(val as u8) - } - #[doc = "Auto-reload preload enable"] - pub fn set_arpe(&mut self, val: super::vals::Arpe) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Clock division"] - pub const fn ckd(&self) -> super::vals::Ckd { - let val = (self.0 >> 8usize) & 0x03; - super::vals::Ckd(val as u8) - } - #[doc = "Clock division"] - pub fn set_ckd(&mut self, val: super::vals::Ckd) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); - } - } - impl Default for Cr1Gp { - fn default() -> Cr1Gp { - Cr1Gp(0) - } - } - #[doc = "DMA address for full transfer"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dmar(pub u32); - impl Dmar { - #[doc = "DMA register for burst accesses"] - pub const fn dmab(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "DMA register for burst accesses"] - pub fn set_dmab(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Dmar { - fn default() -> Dmar { - Dmar(0) - } - } - #[doc = "counter"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cnt16(pub u32); - impl Cnt16 { - #[doc = "counter value"] - pub const fn cnt(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "counter value"] - pub fn set_cnt(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Cnt16 { - fn default() -> Cnt16 { - Cnt16(0) - } - } - #[doc = "event generation register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct EgrBasic(pub u32); - impl EgrBasic { - #[doc = "Update generation"] - pub const fn ug(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update generation"] - pub fn set_ug(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for EgrBasic { - fn default() -> EgrBasic { - EgrBasic(0) - } - } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct SrGp(pub u32); - impl SrGp { - #[doc = "Update interrupt flag"] - pub const fn uif(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt flag"] - pub fn set_uif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare 1 interrupt flag"] - pub fn ccif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/compare 1 interrupt flag"] - pub fn set_ccif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "COM interrupt flag"] - pub const fn comif(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "COM interrupt flag"] - pub fn set_comif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger interrupt flag"] - pub const fn tif(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger interrupt flag"] - pub fn set_tif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break interrupt flag"] - pub const fn bif(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break interrupt flag"] - pub fn set_bif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Capture/Compare 1 overcapture flag"] - pub fn ccof(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 overcapture flag"] - pub fn set_ccof(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for SrGp { - fn default() -> SrGp { - SrGp(0) - } - } - #[doc = "control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2Basic(pub u32); - impl Cr2Basic { - #[doc = "Master mode selection"] - pub const fn mms(&self) -> super::vals::Mms { - let val = (self.0 >> 4usize) & 0x07; - super::vals::Mms(val as u8) - } - #[doc = "Master mode selection"] - pub fn set_mms(&mut self, val: super::vals::Mms) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); - } - } - impl Default for Cr2Basic { - fn default() -> Cr2Basic { - Cr2Basic(0) - } - } - #[doc = "control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2Adv(pub u32); - impl Cr2Adv { - #[doc = "Capture/compare preloaded control"] - pub const fn ccpc(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Capture/compare preloaded control"] - pub fn set_ccpc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare control update selection"] - pub const fn ccus(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Capture/compare control update selection"] - pub fn set_ccus(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Capture/compare DMA selection"] - pub const fn ccds(&self) -> super::vals::Ccds { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Ccds(val as u8) - } - #[doc = "Capture/compare DMA selection"] - pub fn set_ccds(&mut self, val: super::vals::Ccds) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Master mode selection"] - pub const fn mms(&self) -> super::vals::Mms { - let val = (self.0 >> 4usize) & 0x07; - super::vals::Mms(val as u8) - } - #[doc = "Master mode selection"] - pub fn set_mms(&mut self, val: super::vals::Mms) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); - } - #[doc = "TI1 selection"] - pub const fn ti1s(&self) -> super::vals::Tis { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Tis(val as u8) - } - #[doc = "TI1 selection"] - pub fn set_ti1s(&mut self, val: super::vals::Tis) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Output Idle state 1"] - pub fn ois(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 8usize + n * 2usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Output Idle state 1"] - pub fn set_ois(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 8usize + n * 2usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Output Idle state 1"] - pub const fn ois1n(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Output Idle state 1"] - pub fn set_ois1n(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Output Idle state 2"] - pub const fn ois2n(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "Output Idle state 2"] - pub fn set_ois2n(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "Output Idle state 3"] - pub const fn ois3n(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "Output Idle state 3"] - pub fn set_ois3n(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - } - impl Default for Cr2Adv { - fn default() -> Cr2Adv { - Cr2Adv(0) - } - } - #[doc = "DMA/Interrupt enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct DierGp(pub u32); - impl DierGp { - #[doc = "Update interrupt enable"] - pub const fn uie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt enable"] - pub fn set_uie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/Compare 1 interrupt enable"] - pub fn ccie(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 interrupt enable"] - pub fn set_ccie(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Trigger interrupt enable"] - pub const fn tie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger interrupt enable"] - pub fn set_tie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Update DMA request enable"] - pub const fn ude(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Update DMA request enable"] - pub fn set_ude(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Capture/Compare 1 DMA request enable"] - pub fn ccde(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 DMA request enable"] - pub fn set_ccde(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Trigger DMA request enable"] - pub const fn tde(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Trigger DMA request enable"] - pub fn set_tde(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - } - impl Default for DierGp { - fn default() -> DierGp { - DierGp(0) - } - } - #[doc = "auto-reload register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Arr16(pub u32); - impl Arr16 { - #[doc = "Auto-reload value"] - pub const fn arr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Auto-reload value"] - pub fn set_arr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Arr16 { - fn default() -> Arr16 { - Arr16(0) - } - } - #[doc = "capture/compare enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcerGp(pub u32); - impl CcerGp { - #[doc = "Capture/Compare 1 output enable"] - pub fn cce(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output enable"] - pub fn set_cce(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn ccp(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn set_ccp(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn ccnp(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 3usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn set_ccnp(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 3usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for CcerGp { - fn default() -> CcerGp { - CcerGp(0) - } - } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct SrAdv(pub u32); - impl SrAdv { - #[doc = "Update interrupt flag"] - pub const fn uif(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt flag"] - pub fn set_uif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare 1 interrupt flag"] - pub fn ccif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/compare 1 interrupt flag"] - pub fn set_ccif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "COM interrupt flag"] - pub const fn comif(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "COM interrupt flag"] - pub fn set_comif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger interrupt flag"] - pub const fn tif(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger interrupt flag"] - pub fn set_tif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break interrupt flag"] - pub const fn bif(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break interrupt flag"] - pub fn set_bif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Capture/Compare 1 overcapture flag"] - pub fn ccof(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 overcapture flag"] - pub fn set_ccof(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 9usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for SrAdv { - fn default() -> SrAdv { - SrAdv(0) - } - } - #[doc = "capture/compare register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ccr16(pub u32); - impl Ccr16 { - #[doc = "Capture/Compare 1 value"] - pub const fn ccr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Capture/Compare 1 value"] - pub fn set_ccr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Ccr16 { - fn default() -> Ccr16 { - Ccr16(0) - } - } - #[doc = "repetition counter register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Rcr(pub u32); - impl Rcr { - #[doc = "Repetition counter value"] - pub const fn rep(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Repetition counter value"] - pub fn set_rep(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - } - impl Default for Rcr { - fn default() -> Rcr { - Rcr(0) - } - } - #[doc = "break and dead-time register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Bdtr(pub u32); - impl Bdtr { - #[doc = "Dead-time generator setup"] - pub const fn dtg(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Dead-time generator setup"] - pub fn set_dtg(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - #[doc = "Lock configuration"] - pub const fn lock(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x03; - val as u8 - } - #[doc = "Lock configuration"] - pub fn set_lock(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); - } - #[doc = "Off-state selection for Idle mode"] - pub const fn ossi(&self) -> super::vals::Ossi { - let val = (self.0 >> 10usize) & 0x01; - super::vals::Ossi(val as u8) - } - #[doc = "Off-state selection for Idle mode"] - pub fn set_ossi(&mut self, val: super::vals::Ossi) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); - } - #[doc = "Off-state selection for Run mode"] - pub const fn ossr(&self) -> super::vals::Ossr { - let val = (self.0 >> 11usize) & 0x01; - super::vals::Ossr(val as u8) - } - #[doc = "Off-state selection for Run mode"] - pub fn set_ossr(&mut self, val: super::vals::Ossr) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); - } - #[doc = "Break enable"] - pub const fn bke(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[doc = "Break enable"] - pub fn set_bke(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[doc = "Break polarity"] - pub const fn bkp(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "Break polarity"] - pub fn set_bkp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[doc = "Automatic output enable"] - pub const fn aoe(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "Automatic output enable"] - pub fn set_aoe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - #[doc = "Main output enable"] - pub const fn moe(&self) -> bool { - let val = (self.0 >> 15usize) & 0x01; - val != 0 - } - #[doc = "Main output enable"] - pub fn set_moe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); - } - } - impl Default for Bdtr { - fn default() -> Bdtr { - Bdtr(0) - } - } - #[doc = "DMA/Interrupt enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct DierBasic(pub u32); - impl DierBasic { - #[doc = "Update interrupt enable"] - pub const fn uie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt enable"] - pub fn set_uie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Update DMA request enable"] - pub const fn ude(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Update DMA request enable"] - pub fn set_ude(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for DierBasic { - fn default() -> DierBasic { - DierBasic(0) - } - } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct SrBasic(pub u32); - impl SrBasic { - #[doc = "Update interrupt flag"] - pub const fn uif(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update interrupt flag"] - pub fn set_uif(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for SrBasic { - fn default() -> SrBasic { - SrBasic(0) - } - } - #[doc = "capture/compare enable register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcerAdv(pub u32); - impl CcerAdv { - #[doc = "Capture/Compare 1 output enable"] - pub fn cce(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output enable"] - pub fn set_cce(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn ccp(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn set_ccp(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 complementary output enable"] - pub fn ccne(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 2usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 complementary output enable"] - pub fn set_ccne(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 2usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn ccnp(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 3usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/Compare 1 output Polarity"] - pub fn set_ccnp(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 3usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for CcerAdv { - fn default() -> CcerAdv { - CcerAdv(0) - } - } - #[doc = "event generation register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct EgrGp(pub u32); - impl EgrGp { - #[doc = "Update generation"] - pub const fn ug(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Update generation"] - pub fn set_ug(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Capture/compare 1 generation"] - pub fn ccg(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Capture/compare 1 generation"] - pub fn set_ccg(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 1usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Capture/Compare control update generation"] - pub const fn comg(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Capture/Compare control update generation"] - pub fn set_comg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Trigger generation"] - pub const fn tg(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Trigger generation"] - pub fn set_tg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Break generation"] - pub const fn bg(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Break generation"] - pub fn set_bg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - } - impl Default for EgrGp { - fn default() -> EgrGp { - EgrGp(0) - } - } - #[doc = "capture/compare register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ccr32(pub u32); - impl Ccr32 { - #[doc = "Capture/Compare 1 value"] - pub const fn ccr(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Capture/Compare 1 value"] - pub fn set_ccr(&mut self, val: u32) { - self.0 = - (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Ccr32 { - fn default() -> Ccr32 { - Ccr32(0) - } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Etf(pub u8); - impl Etf { - #[doc = "No filter, sampling is done at fDTS"] - pub const NOFILTER: Self = Self(0); - #[doc = "fSAMPLING=fCK_INT, N=2"] - pub const FCK_INT_N2: Self = Self(0x01); - #[doc = "fSAMPLING=fCK_INT, N=4"] - pub const FCK_INT_N4: Self = Self(0x02); - #[doc = "fSAMPLING=fCK_INT, N=8"] - pub const FCK_INT_N8: Self = Self(0x03); - #[doc = "fSAMPLING=fDTS/2, N=6"] - pub const FDTS_DIV2_N6: Self = Self(0x04); - #[doc = "fSAMPLING=fDTS/2, N=8"] - pub const FDTS_DIV2_N8: Self = Self(0x05); - #[doc = "fSAMPLING=fDTS/4, N=6"] - pub const FDTS_DIV4_N6: Self = Self(0x06); - #[doc = "fSAMPLING=fDTS/4, N=8"] - pub const FDTS_DIV4_N8: Self = Self(0x07); - #[doc = "fSAMPLING=fDTS/8, N=6"] - pub const FDTS_DIV8_N6: Self = Self(0x08); - #[doc = "fSAMPLING=fDTS/8, N=8"] - pub const FDTS_DIV8_N8: Self = Self(0x09); - #[doc = "fSAMPLING=fDTS/16, N=5"] - pub const FDTS_DIV16_N5: Self = Self(0x0a); - #[doc = "fSAMPLING=fDTS/16, N=6"] - pub const FDTS_DIV16_N6: Self = Self(0x0b); - #[doc = "fSAMPLING=fDTS/16, N=8"] - pub const FDTS_DIV16_N8: Self = Self(0x0c); - #[doc = "fSAMPLING=fDTS/32, N=5"] - pub const FDTS_DIV32_N5: Self = Self(0x0d); - #[doc = "fSAMPLING=fDTS/32, N=6"] - pub const FDTS_DIV32_N6: Self = Self(0x0e); - #[doc = "fSAMPLING=fDTS/32, N=8"] - pub const FDTS_DIV32_N8: Self = Self(0x0f); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Tis(pub u8); - impl Tis { - #[doc = "The TIMx_CH1 pin is connected to TI1 input"] - pub const NORMAL: Self = Self(0); - #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"] - pub const XOR: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ccds(pub u8); - impl Ccds { - #[doc = "CCx DMA request sent when CCx event occurs"] - pub const ONCOMPARE: Self = Self(0); - #[doc = "CCx DMA request sent when update event occurs"] - pub const ONUPDATE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Sms(pub u8); - impl Sms { - #[doc = "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] - pub const DISABLED: Self = Self(0); - #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."] - pub const ENCODER_MODE_1: Self = Self(0x01); - #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."] - pub const ENCODER_MODE_2: Self = Self(0x02); - #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."] - pub const ENCODER_MODE_3: Self = Self(0x03); - #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."] - pub const RESET_MODE: Self = Self(0x04); - #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."] - pub const GATED_MODE: Self = Self(0x05); - #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."] - pub const TRIGGER_MODE: Self = Self(0x06); - #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."] - pub const EXT_CLOCK_MODE: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dir(pub u8); - impl Dir { - #[doc = "Counter used as upcounter"] - pub const UP: Self = Self(0); - #[doc = "Counter used as downcounter"] - pub const DOWN: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mms(pub u8); - impl Mms { - #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"] - pub const RESET: Self = Self(0); - #[doc = "The counter enable signal, CNT_EN, is used as trigger output"] - pub const ENABLE: Self = Self(0x01); - #[doc = "The update event is selected as trigger output"] - pub const UPDATE: Self = Self(0x02); - #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"] - pub const COMPAREPULSE: Self = Self(0x03); - #[doc = "OC1REF signal is used as trigger output"] - pub const COMPAREOC1: Self = Self(0x04); - #[doc = "OC2REF signal is used as trigger output"] - pub const COMPAREOC2: Self = Self(0x05); - #[doc = "OC3REF signal is used as trigger output"] - pub const COMPAREOC3: Self = Self(0x06); - #[doc = "OC4REF signal is used as trigger output"] - pub const COMPAREOC4: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ossi(pub u8); - impl Ossi { - #[doc = "When inactive, OC/OCN outputs are disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "When inactive, OC/OCN outputs are forced to idle level"] - pub const IDLELEVEL: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Urs(pub u8); - impl Urs { - #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"] - pub const ANYEVENT: Self = Self(0); - #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"] - pub const COUNTERONLY: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct CcmrOutputCcs(pub u8); - impl CcmrOutputCcs { - #[doc = "CCx channel is configured as output"] - pub const OUTPUT: Self = Self(0); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ossr(pub u8); - impl Ossr { - #[doc = "When inactive, OC/OCN outputs are disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"] - pub const IDLELEVEL: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cms(pub u8); - impl Cms { - #[doc = "The counter counts up or down depending on the direction bit"] - pub const EDGEALIGNED: Self = Self(0); - #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] - pub const CENTERALIGNED1: Self = Self(0x01); - #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] - pub const CENTERALIGNED2: Self = Self(0x02); - #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] - pub const CENTERALIGNED3: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct CcmrInputCcs(pub u8); - impl CcmrInputCcs { - #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"] - pub const TI4: Self = Self(0x01); - #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"] - pub const TI3: Self = Self(0x02); - #[doc = "CCx channel is configured as input, ICx is mapped on TRC"] - pub const TRC: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ts(pub u8); - impl Ts { - #[doc = "Internal Trigger 0 (ITR0)"] - pub const ITR0: Self = Self(0); - #[doc = "Internal Trigger 1 (ITR1)"] - pub const ITR1: Self = Self(0x01); - #[doc = "Internal Trigger 2 (ITR2)"] - pub const ITR2: Self = Self(0x02); - #[doc = "TI1 Edge Detector (TI1F_ED)"] - pub const TI1F_ED: Self = Self(0x04); - #[doc = "Filtered Timer Input 1 (TI1FP1)"] - pub const TI1FP1: Self = Self(0x05); - #[doc = "Filtered Timer Input 2 (TI2FP2)"] - pub const TI2FP2: Self = Self(0x06); - #[doc = "External Trigger input (ETRF)"] - pub const ETRF: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ocm(pub u8); - impl Ocm { - #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] - pub const FROZEN: Self = Self(0); - #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] - pub const ACTIVEONMATCH: Self = Self(0x01); - #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] - pub const INACTIVEONMATCH: Self = Self(0x02); - #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] - pub const TOGGLE: Self = Self(0x03); - #[doc = "OCyREF is forced low"] - pub const FORCEINACTIVE: Self = Self(0x04); - #[doc = "OCyREF is forced high"] - pub const FORCEACTIVE: Self = Self(0x05); - #[doc = "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active"] - pub const PWMMODE1: Self = Self(0x06); - #[doc = "Inversely to PwmMode1"] - pub const PWMMODE2: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ckd(pub u8); - impl Ckd { - #[doc = "t_DTS = t_CK_INT"] - pub const DIV1: Self = Self(0); - #[doc = "t_DTS = 2 × t_CK_INT"] - pub const DIV2: Self = Self(0x01); - #[doc = "t_DTS = 4 × t_CK_INT"] - pub const DIV4: Self = Self(0x02); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ece(pub u8); - impl Ece { - #[doc = "External clock mode 2 disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Msm(pub u8); - impl Msm { - #[doc = "No action"] - pub const NOSYNC: Self = Self(0); - #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."] - pub const SYNC: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Etps(pub u8); - impl Etps { - #[doc = "Prescaler OFF"] - pub const DIV1: Self = Self(0); - #[doc = "ETRP frequency divided by 2"] - pub const DIV2: Self = Self(0x01); - #[doc = "ETRP frequency divided by 4"] - pub const DIV4: Self = Self(0x02); - #[doc = "ETRP frequency divided by 8"] - pub const DIV8: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ocpe(pub u8); - impl Ocpe { - #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"] - pub const DISABLED: Self = Self(0); - #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Arpe(pub u8); - impl Arpe { - #[doc = "TIMx_APRR register is not buffered"] - pub const DISABLED: Self = Self(0); - #[doc = "TIMx_APRR register is buffered"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Icf(pub u8); - impl Icf { - #[doc = "No filter, sampling is done at fDTS"] - pub const NOFILTER: Self = Self(0); - #[doc = "fSAMPLING=fCK_INT, N=2"] - pub const FCK_INT_N2: Self = Self(0x01); - #[doc = "fSAMPLING=fCK_INT, N=4"] - pub const FCK_INT_N4: Self = Self(0x02); - #[doc = "fSAMPLING=fCK_INT, N=8"] - pub const FCK_INT_N8: Self = Self(0x03); - #[doc = "fSAMPLING=fDTS/2, N=6"] - pub const FDTS_DIV2_N6: Self = Self(0x04); - #[doc = "fSAMPLING=fDTS/2, N=8"] - pub const FDTS_DIV2_N8: Self = Self(0x05); - #[doc = "fSAMPLING=fDTS/4, N=6"] - pub const FDTS_DIV4_N6: Self = Self(0x06); - #[doc = "fSAMPLING=fDTS/4, N=8"] - pub const FDTS_DIV4_N8: Self = Self(0x07); - #[doc = "fSAMPLING=fDTS/8, N=6"] - pub const FDTS_DIV8_N6: Self = Self(0x08); - #[doc = "fSAMPLING=fDTS/8, N=8"] - pub const FDTS_DIV8_N8: Self = Self(0x09); - #[doc = "fSAMPLING=fDTS/16, N=5"] - pub const FDTS_DIV16_N5: Self = Self(0x0a); - #[doc = "fSAMPLING=fDTS/16, N=6"] - pub const FDTS_DIV16_N6: Self = Self(0x0b); - #[doc = "fSAMPLING=fDTS/16, N=8"] - pub const FDTS_DIV16_N8: Self = Self(0x0c); - #[doc = "fSAMPLING=fDTS/32, N=5"] - pub const FDTS_DIV32_N5: Self = Self(0x0d); - #[doc = "fSAMPLING=fDTS/32, N=6"] - pub const FDTS_DIV32_N6: Self = Self(0x0e); - #[doc = "fSAMPLING=fDTS/32, N=8"] - pub const FDTS_DIV32_N8: Self = Self(0x0f); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Opm(pub u8); - impl Opm { - #[doc = "Counter is not stopped at update event"] - pub const DISABLED: Self = Self(0); - #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Etp(pub u8); - impl Etp { - #[doc = "ETR is noninverted, active at high level or rising edge"] - pub const NOTINVERTED: Self = Self(0); - #[doc = "ETR is inverted, active at low level or falling edge"] - pub const INVERTED: Self = Self(0x01); - } } } pub mod gpio_v1 { @@ -3536,12 +8614,29 @@ pub mod gpio_v1 { use crate::generic::*; #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Odr(pub u8); - impl Odr { - #[doc = "Set output to logic low"] - pub const LOW: Self = Self(0); - #[doc = "Set output to logic high"] - pub const HIGH: Self = Self(0x01); + pub struct Cnf(pub u8); + impl Cnf { + #[doc = "Analog mode / Push-Pull mode"] + pub const PUSHPULL: Self = Self(0); + #[doc = "Floating input (reset state) / Open Drain-Mode"] + pub const OPENDRAIN: Self = Self(0x01); + #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"] + pub const ALTPUSHPULL: Self = Self(0x02); + #[doc = "Alternate Function Open-Drain Mode"] + pub const ALTOPENDRAIN: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mode(pub u8); + impl Mode { + #[doc = "Input mode (reset state)"] + pub const INPUT: Self = Self(0); + #[doc = "Output mode 10 MHz"] + pub const OUTPUT: Self = Self(0x01); + #[doc = "Output mode 2 MHz"] + pub const OUTPUT2: Self = Self(0x02); + #[doc = "Output mode 50 MHz"] + pub const OUTPUT50: Self = Self(0x03); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] @@ -3554,16 +8649,12 @@ pub mod gpio_v1 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cnf(pub u8); - impl Cnf { - #[doc = "Analog mode / Push-Pull mode"] - pub const PUSHPULL: Self = Self(0); - #[doc = "Floating input (reset state) / Open Drain-Mode"] - pub const OPENDRAIN: Self = Self(0x01); - #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"] - pub const ALTPUSHPULL: Self = Self(0x02); - #[doc = "Alternate Function Open-Drain Mode"] - pub const ALTOPENDRAIN: Self = Self(0x03); + pub struct Lck(pub u8); + impl Lck { + #[doc = "Port configuration not locked"] + pub const UNLOCKED: Self = Self(0); + #[doc = "Port configuration locked"] + pub const LOCKED: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] @@ -3594,75 +8685,51 @@ pub mod gpio_v1 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mode(pub u8); - impl Mode { - #[doc = "Input mode (reset state)"] - pub const INPUT: Self = Self(0); - #[doc = "Output mode 10 MHz"] - pub const OUTPUT: Self = Self(0x01); - #[doc = "Output mode 2 MHz"] - pub const OUTPUT2: Self = Self(0x02); - #[doc = "Output mode 50 MHz"] - pub const OUTPUT50: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lck(pub u8); - impl Lck { - #[doc = "Port configuration not locked"] - pub const UNLOCKED: Self = Self(0); - #[doc = "Port configuration locked"] - pub const LOCKED: Self = Self(0x01); + pub struct Odr(pub u8); + impl Odr { + #[doc = "Set output to logic low"] + pub const LOW: Self = Self(0); + #[doc = "Set output to logic high"] + pub const HIGH: Self = Self(0x01); } } pub mod regs { use crate::generic::*; - #[doc = "Port bit reset register (GPIOn_BRR)"] + #[doc = "Port bit set/reset register (GPIOn_BSRR)"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Brr(pub u32); - impl Brr { + pub struct Bsrr(pub u32); + impl Bsrr { + #[doc = "Set bit"] + pub fn bs(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Set bit"] + pub fn set_bs(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } #[doc = "Reset bit"] pub fn br(&self, n: usize) -> bool { assert!(n < 16usize); - let offs = 0usize + n * 1usize; + let offs = 16usize + n * 1usize; let val = (self.0 >> offs) & 0x01; val != 0 } #[doc = "Reset bit"] pub fn set_br(&mut self, n: usize, val: bool) { assert!(n < 16usize); - let offs = 0usize + n * 1usize; + let offs = 16usize + n * 1usize; self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } } - impl Default for Brr { - fn default() -> Brr { - Brr(0) - } - } - #[doc = "Port input data register (GPIOn_IDR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idr(pub u32); - impl Idr { - #[doc = "Port input data"] - pub fn idr(&self, n: usize) -> super::vals::Idr { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Idr(val as u8) - } - #[doc = "Port input data"] - pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Idr { - fn default() -> Idr { - Idr(0) + impl Default for Bsrr { + fn default() -> Bsrr { + Bsrr(0) } } #[doc = "Port configuration register (GPIOn_CRx)"] @@ -3702,6 +8769,54 @@ pub mod gpio_v1 { Cr(0) } } + #[doc = "Port input data register (GPIOn_IDR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idr(pub u32); + impl Idr { + #[doc = "Port input data"] + pub fn idr(&self, n: usize) -> super::vals::Idr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Idr(val as u8) + } + #[doc = "Port input data"] + pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Idr { + fn default() -> Idr { + Idr(0) + } + } + #[doc = "Port output data register (GPIOn_ODR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Odr(pub u32); + impl Odr { + #[doc = "Port output data"] + pub fn odr(&self, n: usize) -> super::vals::Odr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Odr(val as u8) + } + #[doc = "Port output data"] + pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Odr { + fn default() -> Odr { + Odr(0) + } + } #[doc = "Port configuration lock register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -3735,609 +8850,30 @@ pub mod gpio_v1 { Lckr(0) } } - #[doc = "Port bit set/reset register (GPIOn_BSRR)"] + #[doc = "Port bit reset register (GPIOn_BRR)"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Bsrr(pub u32); - impl Bsrr { - #[doc = "Set bit"] - pub fn bs(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Set bit"] - pub fn set_bs(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } + pub struct Brr(pub u32); + impl Brr { #[doc = "Reset bit"] pub fn br(&self, n: usize) -> bool { assert!(n < 16usize); - let offs = 16usize + n * 1usize; + let offs = 0usize + n * 1usize; let val = (self.0 >> offs) & 0x01; val != 0 } #[doc = "Reset bit"] pub fn set_br(&mut self, n: usize, val: bool) { assert!(n < 16usize); - let offs = 16usize + n * 1usize; + let offs = 0usize + n * 1usize; self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } } - impl Default for Bsrr { - fn default() -> Bsrr { - Bsrr(0) + impl Default for Brr { + fn default() -> Brr { + Brr(0) } } - #[doc = "Port output data register (GPIOn_ODR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Odr(pub u32); - impl Odr { - #[doc = "Port output data"] - pub fn odr(&self, n: usize) -> super::vals::Odr { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Odr(val as u8) - } - #[doc = "Port output data"] - pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Odr { - fn default() -> Odr { - Odr(0) - } - } - } -} -pub mod spi_v1 { - use crate::generic::*; - #[doc = "Serial peripheral interface"] - #[derive(Copy, Clone)] - pub struct Spi(pub *mut u8); - unsafe impl Send for Spi {} - unsafe impl Sync for Spi {} - impl Spi { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "data register"] - pub fn dr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "CRC polynomial register"] - pub fn crcpr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "RX CRC register"] - pub fn rxcrcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "TX CRC register"] - pub fn txcrcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "TX CRC register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Txcrcr(pub u32); - impl Txcrcr { - #[doc = "Tx CRC register"] - pub const fn tx_crc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Tx CRC register"] - pub fn set_tx_crc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Txcrcr { - fn default() -> Txcrcr { - Txcrcr(0) - } - } - #[doc = "RX CRC register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Rxcrcr(pub u32); - impl Rxcrcr { - #[doc = "Rx CRC register"] - pub const fn rx_crc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Rx CRC register"] - pub fn set_rx_crc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Rxcrcr { - fn default() -> Rxcrcr { - Rxcrcr(0) - } - } - #[doc = "control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2(pub u32); - impl Cr2 { - #[doc = "Rx buffer DMA enable"] - pub const fn rxdmaen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Rx buffer DMA enable"] - pub fn set_rxdmaen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Tx buffer DMA enable"] - pub const fn txdmaen(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Tx buffer DMA enable"] - pub fn set_txdmaen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "SS output enable"] - pub const fn ssoe(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "SS output enable"] - pub fn set_ssoe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Frame format"] - pub const fn frf(&self) -> super::vals::Frf { - let val = (self.0 >> 4usize) & 0x01; - super::vals::Frf(val as u8) - } - #[doc = "Frame format"] - pub fn set_frf(&mut self, val: super::vals::Frf) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); - } - #[doc = "Error interrupt enable"] - pub const fn errie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Error interrupt enable"] - pub fn set_errie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "RX buffer not empty interrupt enable"] - pub const fn rxneie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "RX buffer not empty interrupt enable"] - pub fn set_rxneie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Tx buffer empty interrupt enable"] - pub const fn txeie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Tx buffer empty interrupt enable"] - pub fn set_txeie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - } - impl Default for Cr2 { - fn default() -> Cr2 { - Cr2(0) - } - } - #[doc = "control register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1(pub u32); - impl Cr1 { - #[doc = "Clock phase"] - pub const fn cpha(&self) -> super::vals::Cpha { - let val = (self.0 >> 0usize) & 0x01; - super::vals::Cpha(val as u8) - } - #[doc = "Clock phase"] - pub fn set_cpha(&mut self, val: super::vals::Cpha) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); - } - #[doc = "Clock polarity"] - pub const fn cpol(&self) -> super::vals::Cpol { - let val = (self.0 >> 1usize) & 0x01; - super::vals::Cpol(val as u8) - } - #[doc = "Clock polarity"] - pub fn set_cpol(&mut self, val: super::vals::Cpol) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); - } - #[doc = "Master selection"] - pub const fn mstr(&self) -> super::vals::Mstr { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Mstr(val as u8) - } - #[doc = "Master selection"] - pub fn set_mstr(&mut self, val: super::vals::Mstr) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "Baud rate control"] - pub const fn br(&self) -> super::vals::Br { - let val = (self.0 >> 3usize) & 0x07; - super::vals::Br(val as u8) - } - #[doc = "Baud rate control"] - pub fn set_br(&mut self, val: super::vals::Br) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); - } - #[doc = "SPI enable"] - pub const fn spe(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "SPI enable"] - pub fn set_spe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Frame format"] - pub const fn lsbfirst(&self) -> super::vals::Lsbfirst { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Lsbfirst(val as u8) - } - #[doc = "Frame format"] - pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Internal slave select"] - pub const fn ssi(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Internal slave select"] - pub fn set_ssi(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Software slave management"] - pub const fn ssm(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Software slave management"] - pub fn set_ssm(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Receive only"] - pub const fn rxonly(&self) -> super::vals::Rxonly { - let val = (self.0 >> 10usize) & 0x01; - super::vals::Rxonly(val as u8) - } - #[doc = "Receive only"] - pub fn set_rxonly(&mut self, val: super::vals::Rxonly) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); - } - #[doc = "Data frame format"] - pub const fn dff(&self) -> super::vals::Dff { - let val = (self.0 >> 11usize) & 0x01; - super::vals::Dff(val as u8) - } - #[doc = "Data frame format"] - pub fn set_dff(&mut self, val: super::vals::Dff) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); - } - #[doc = "CRC transfer next"] - pub const fn crcnext(&self) -> super::vals::Crcnext { - let val = (self.0 >> 12usize) & 0x01; - super::vals::Crcnext(val as u8) - } - #[doc = "CRC transfer next"] - pub fn set_crcnext(&mut self, val: super::vals::Crcnext) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); - } - #[doc = "Hardware CRC calculation enable"] - pub const fn crcen(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "Hardware CRC calculation enable"] - pub fn set_crcen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[doc = "Output enable in bidirectional mode"] - pub const fn bidioe(&self) -> super::vals::Bidioe { - let val = (self.0 >> 14usize) & 0x01; - super::vals::Bidioe(val as u8) - } - #[doc = "Output enable in bidirectional mode"] - pub fn set_bidioe(&mut self, val: super::vals::Bidioe) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); - } - #[doc = "Bidirectional data mode enable"] - pub const fn bidimode(&self) -> super::vals::Bidimode { - let val = (self.0 >> 15usize) & 0x01; - super::vals::Bidimode(val as u8) - } - #[doc = "Bidirectional data mode enable"] - pub fn set_bidimode(&mut self, val: super::vals::Bidimode) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); - } - } - impl Default for Cr1 { - fn default() -> Cr1 { - Cr1(0) - } - } - #[doc = "data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dr(pub u32); - impl Dr { - #[doc = "Data register"] - pub const fn dr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Data register"] - pub fn set_dr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Dr { - fn default() -> Dr { - Dr(0) - } - } - #[doc = "CRC polynomial register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Crcpr(pub u32); - impl Crcpr { - #[doc = "CRC polynomial register"] - pub const fn crcpoly(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "CRC polynomial register"] - pub fn set_crcpoly(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Crcpr { - fn default() -> Crcpr { - Crcpr(0) - } - } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Sr(pub u32); - impl Sr { - #[doc = "Receive buffer not empty"] - pub const fn rxne(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Receive buffer not empty"] - pub fn set_rxne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Transmit buffer empty"] - pub const fn txe(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Transmit buffer empty"] - pub fn set_txe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "CRC error flag"] - pub const fn crcerr(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "CRC error flag"] - pub fn set_crcerr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Mode fault"] - pub const fn modf(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Mode fault"] - pub fn set_modf(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Overrun flag"] - pub const fn ovr(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Overrun flag"] - pub fn set_ovr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Busy flag"] - pub const fn bsy(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Busy flag"] - pub fn set_bsy(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "TI frame format error"] - pub const fn fre(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "TI frame format error"] - pub fn set_fre(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for Sr { - fn default() -> Sr { - Sr(0) - } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frf(pub u8); - impl Frf { - #[doc = "SPI Motorola mode"] - pub const MOTOROLA: Self = Self(0); - #[doc = "SPI TI mode"] - pub const TI: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Iscfg(pub u8); - impl Iscfg { - #[doc = "Slave - transmit"] - pub const SLAVETX: Self = Self(0); - #[doc = "Slave - receive"] - pub const SLAVERX: Self = Self(0x01); - #[doc = "Master - transmit"] - pub const MASTERTX: Self = Self(0x02); - #[doc = "Master - receive"] - pub const MASTERRX: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bidioe(pub u8); - impl Bidioe { - #[doc = "Output disabled (receive-only mode)"] - pub const OUTPUTDISABLED: Self = Self(0); - #[doc = "Output enabled (transmit-only mode)"] - pub const OUTPUTENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dff(pub u8); - impl Dff { - #[doc = "8-bit data frame format is selected for transmission/reception"] - pub const EIGHTBIT: Self = Self(0); - #[doc = "16-bit data frame format is selected for transmission/reception"] - pub const SIXTEENBIT: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bidimode(pub u8); - impl Bidimode { - #[doc = "2-line unidirectional data mode selected"] - pub const UNIDIRECTIONAL: Self = Self(0); - #[doc = "1-line bidirectional data mode selected"] - pub const BIDIRECTIONAL: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpha(pub u8); - impl Cpha { - #[doc = "The first clock transition is the first data capture edge"] - pub const FIRSTEDGE: Self = Self(0); - #[doc = "The second clock transition is the first data capture edge"] - pub const SECONDEDGE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Rxonly(pub u8); - impl Rxonly { - #[doc = "Full duplex (Transmit and receive)"] - pub const FULLDUPLEX: Self = Self(0); - #[doc = "Output disabled (Receive-only mode)"] - pub const OUTPUTDISABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lsbfirst(pub u8); - impl Lsbfirst { - #[doc = "Data is transmitted/received with the MSB first"] - pub const MSBFIRST: Self = Self(0); - #[doc = "Data is transmitted/received with the LSB first"] - pub const LSBFIRST: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frer(pub u8); - impl Frer { - #[doc = "No frame format error"] - pub const NOERROR: Self = Self(0); - #[doc = "A frame format error occurred"] - pub const ERROR: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Crcnext(pub u8); - impl Crcnext { - #[doc = "Next transmit value is from Tx buffer"] - pub const TXBUFFER: Self = Self(0); - #[doc = "Next transmit value is from Tx CRC register"] - pub const CRC: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Br(pub u8); - impl Br { - #[doc = "f_PCLK / 2"] - pub const DIV2: Self = Self(0); - #[doc = "f_PCLK / 4"] - pub const DIV4: Self = Self(0x01); - #[doc = "f_PCLK / 8"] - pub const DIV8: Self = Self(0x02); - #[doc = "f_PCLK / 16"] - pub const DIV16: Self = Self(0x03); - #[doc = "f_PCLK / 32"] - pub const DIV32: Self = Self(0x04); - #[doc = "f_PCLK / 64"] - pub const DIV64: Self = Self(0x05); - #[doc = "f_PCLK / 128"] - pub const DIV128: Self = Self(0x06); - #[doc = "f_PCLK / 256"] - pub const DIV256: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpol(pub u8); - impl Cpol { - #[doc = "CK to 0 when idle"] - pub const IDLELOW: Self = Self(0); - #[doc = "CK to 1 when idle"] - pub const IDLEHIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mstr(pub u8); - impl Mstr { - #[doc = "Slave configuration"] - pub const SLAVE: Self = Self(0); - #[doc = "Master configuration"] - pub const MASTER: Self = Self(0x01); - } } } pub mod exti_v1 { @@ -4373,52 +8909,56 @@ pub mod exti_v1 { unsafe { Reg::from_ptr(self.0.add(20usize)) } } } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Tr(pub u8); - impl Tr { - #[doc = "Falling edge trigger is disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Falling edge trigger is enabled"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Swierw(pub u8); - impl Swierw { - #[doc = "Generates an interrupt request"] - pub const PEND: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mr(pub u8); - impl Mr { - #[doc = "Interrupt request line is masked"] - pub const MASKED: Self = Self(0); - #[doc = "Interrupt request line is unmasked"] - pub const UNMASKED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Prr(pub u8); - impl Prr { - #[doc = "No trigger request occurred"] - pub const NOTPENDING: Self = Self(0); - #[doc = "Selected trigger request occurred"] - pub const PENDING: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Prw(pub u8); - impl Prw { - #[doc = "Clears pending bit"] - pub const CLEAR: Self = Self(0x01); - } - } pub mod regs { use crate::generic::*; + #[doc = "Interrupt mask register (EXTI_IMR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Imr(pub u32); + impl Imr { + #[doc = "Interrupt Mask on line 0"] + pub fn mr(&self, n: usize) -> super::vals::Mr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Mr(val as u8) + } + #[doc = "Interrupt Mask on line 0"] + pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Imr { + fn default() -> Imr { + Imr(0) + } + } + #[doc = "Software interrupt event register (EXTI_SWIER)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Swier(pub u32); + impl Swier { + #[doc = "Software Interrupt on line 0"] + pub fn swier(&self, n: usize) -> bool { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Software Interrupt on line 0"] + pub fn set_swier(&mut self, n: usize, val: bool) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Swier { + fn default() -> Swier { + Swier(0) + } + } #[doc = "Falling Trigger selection register (EXTI_FTSR)"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -4467,54 +9007,6 @@ pub mod exti_v1 { Rtsr(0) } } - #[doc = "Event mask register (EXTI_EMR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Emr(pub u32); - impl Emr { - #[doc = "Event Mask on line 0"] - pub fn mr(&self, n: usize) -> super::vals::Mr { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Mr(val as u8) - } - #[doc = "Event Mask on line 0"] - pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Emr { - fn default() -> Emr { - Emr(0) - } - } - #[doc = "Interrupt mask register (EXTI_IMR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Imr(pub u32); - impl Imr { - #[doc = "Interrupt Mask on line 0"] - pub fn mr(&self, n: usize) -> super::vals::Mr { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Mr(val as u8) - } - #[doc = "Interrupt Mask on line 0"] - pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { - assert!(n < 23usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Imr { - fn default() -> Imr { - Imr(0) - } - } #[doc = "Pending register (EXTI_PR)"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -4539,1812 +9031,28 @@ pub mod exti_v1 { Pr(0) } } - #[doc = "Software interrupt event register (EXTI_SWIER)"] + #[doc = "Event mask register (EXTI_EMR)"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Swier(pub u32); - impl Swier { - #[doc = "Software Interrupt on line 0"] - pub fn swier(&self, n: usize) -> bool { + pub struct Emr(pub u32); + impl Emr { + #[doc = "Event Mask on line 0"] + pub fn mr(&self, n: usize) -> super::vals::Mr { assert!(n < 23usize); let offs = 0usize + n * 1usize; let val = (self.0 >> offs) & 0x01; - val != 0 + super::vals::Mr(val as u8) } - #[doc = "Software Interrupt on line 0"] - pub fn set_swier(&mut self, n: usize, val: bool) { + #[doc = "Event Mask on line 0"] + pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { assert!(n < 23usize); let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Swier { - fn default() -> Swier { - Swier(0) - } - } - } -} -pub mod dma_v1 { - use crate::generic::*; - #[doc = "DMA controller"] - #[derive(Copy, Clone)] - pub struct Dma(pub *mut u8); - unsafe impl Send for Dma {} - unsafe impl Sync for Dma {} - impl Dma { - #[doc = "DMA interrupt status register (DMA_ISR)"] - pub fn isr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] - pub fn ifcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] - pub fn ch(self, n: usize) -> Ch { - assert!(n < 7usize); - unsafe { Ch(self.0.add(8usize + n * 20usize)) } - } - } - #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] - #[derive(Copy, Clone)] - pub struct Ch(pub *mut u8); - unsafe impl Send for Ch {} - unsafe impl Sync for Ch {} - impl Ch { - #[doc = "DMA channel configuration register (DMA_CCR)"] - pub fn cr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "DMA channel 1 number of data register"] - pub fn ndtr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "DMA channel 1 peripheral address register"] - pub fn par(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "DMA channel 1 memory address register"] - pub fn mar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pl(pub u8); - impl Pl { - #[doc = "Low priority"] - pub const LOW: Self = Self(0); - #[doc = "Medium priority"] - pub const MEDIUM: Self = Self(0x01); - #[doc = "High priority"] - pub const HIGH: Self = Self(0x02); - #[doc = "Very high priority"] - pub const VERYHIGH: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dir(pub u8); - impl Dir { - #[doc = "Read from peripheral"] - pub const FROMPERIPHERAL: Self = Self(0); - #[doc = "Read from memory"] - pub const FROMMEMORY: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Size(pub u8); - impl Size { - #[doc = "8-bit size"] - pub const BITS8: Self = Self(0); - #[doc = "16-bit size"] - pub const BITS16: Self = Self(0x01); - #[doc = "32-bit size"] - pub const BITS32: Self = Self(0x02); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Memmem(pub u8); - impl Memmem { - #[doc = "Memory to memory mode disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Memory to memory mode enabled"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Circ(pub u8); - impl Circ { - #[doc = "Circular buffer disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Circular buffer enabled"] - pub const ENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Inc(pub u8); - impl Inc { - #[doc = "Increment mode disabled"] - pub const DISABLED: Self = Self(0); - #[doc = "Increment mode enabled"] - pub const ENABLED: Self = Self(0x01); - } - } - pub mod regs { - use crate::generic::*; - #[doc = "DMA interrupt status register (DMA_ISR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Isr(pub u32); - impl Isr { - #[doc = "Channel 1 Global interrupt flag"] - pub fn gif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Global interrupt flag"] - pub fn set_gif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Transfer Complete flag"] - pub fn tcif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 1usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Transfer Complete flag"] - pub fn set_tcif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 1usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Half Transfer Complete flag"] - pub fn htif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 2usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Half Transfer Complete flag"] - pub fn set_htif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 2usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Transfer Error flag"] - pub fn teif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 3usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Transfer Error flag"] - pub fn set_teif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 3usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Isr { - fn default() -> Isr { - Isr(0) - } - } - #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ifcr(pub u32); - impl Ifcr { - #[doc = "Channel 1 Global interrupt clear"] - pub fn cgif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Global interrupt clear"] - pub fn set_cgif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Transfer Complete clear"] - pub fn ctcif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 1usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Transfer Complete clear"] - pub fn set_ctcif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 1usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Half Transfer clear"] - pub fn chtif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 2usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Half Transfer clear"] - pub fn set_chtif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 2usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Channel 1 Transfer Error clear"] - pub fn cteif(&self, n: usize) -> bool { - assert!(n < 7usize); - let offs = 3usize + n * 4usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Channel 1 Transfer Error clear"] - pub fn set_cteif(&mut self, n: usize, val: bool) { - assert!(n < 7usize); - let offs = 3usize + n * 4usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Ifcr { - fn default() -> Ifcr { - Ifcr(0) - } - } - #[doc = "DMA channel configuration register (DMA_CCR)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr(pub u32); - impl Cr { - #[doc = "Channel enable"] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Channel enable"] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Transfer complete interrupt enable"] - pub const fn tcie(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Transfer complete interrupt enable"] - pub fn set_tcie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Half Transfer interrupt enable"] - pub const fn htie(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Half Transfer interrupt enable"] - pub fn set_htie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Transfer error interrupt enable"] - pub const fn teie(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Transfer error interrupt enable"] - pub fn set_teie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Data transfer direction"] - pub const fn dir(&self) -> super::vals::Dir { - let val = (self.0 >> 4usize) & 0x01; - super::vals::Dir(val as u8) - } - #[doc = "Data transfer direction"] - pub fn set_dir(&mut self, val: super::vals::Dir) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); - } - #[doc = "Circular mode"] - pub const fn circ(&self) -> super::vals::Circ { - let val = (self.0 >> 5usize) & 0x01; - super::vals::Circ(val as u8) - } - #[doc = "Circular mode"] - pub fn set_circ(&mut self, val: super::vals::Circ) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); - } - #[doc = "Peripheral increment mode"] - pub const fn pinc(&self) -> super::vals::Inc { - let val = (self.0 >> 6usize) & 0x01; - super::vals::Inc(val as u8) - } - #[doc = "Peripheral increment mode"] - pub fn set_pinc(&mut self, val: super::vals::Inc) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize); - } - #[doc = "Memory increment mode"] - pub const fn minc(&self) -> super::vals::Inc { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Inc(val as u8) - } - #[doc = "Memory increment mode"] - pub fn set_minc(&mut self, val: super::vals::Inc) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Peripheral size"] - pub const fn psize(&self) -> super::vals::Size { - let val = (self.0 >> 8usize) & 0x03; - super::vals::Size(val as u8) - } - #[doc = "Peripheral size"] - pub fn set_psize(&mut self, val: super::vals::Size) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); - } - #[doc = "Memory size"] - pub const fn msize(&self) -> super::vals::Size { - let val = (self.0 >> 10usize) & 0x03; - super::vals::Size(val as u8) - } - #[doc = "Memory size"] - pub fn set_msize(&mut self, val: super::vals::Size) { - self.0 = (self.0 & !(0x03 << 10usize)) | (((val.0 as u32) & 0x03) << 10usize); - } - #[doc = "Channel Priority level"] - pub const fn pl(&self) -> super::vals::Pl { - let val = (self.0 >> 12usize) & 0x03; - super::vals::Pl(val as u8) - } - #[doc = "Channel Priority level"] - pub fn set_pl(&mut self, val: super::vals::Pl) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); - } - #[doc = "Memory to memory mode"] - pub const fn mem2mem(&self) -> super::vals::Memmem { - let val = (self.0 >> 14usize) & 0x01; - super::vals::Memmem(val as u8) - } - #[doc = "Memory to memory mode"] - pub fn set_mem2mem(&mut self, val: super::vals::Memmem) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); - } - } - impl Default for Cr { - fn default() -> Cr { - Cr(0) - } - } - #[doc = "DMA channel 1 number of data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ndtr(pub u32); - impl Ndtr { - #[doc = "Number of data to transfer"] - pub const fn ndt(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Number of data to transfer"] - pub fn set_ndt(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Ndtr { - fn default() -> Ndtr { - Ndtr(0) - } - } - } -} -pub mod rng_v1 { - use crate::generic::*; - #[doc = "Random number generator"] - #[derive(Copy, Clone)] - pub struct Rng(pub *mut u8); - unsafe impl Send for Rng {} - unsafe impl Sync for Rng {} - impl Rng { - #[doc = "control register"] - pub fn cr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "data register"] - pub fn dr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Sr(pub u32); - impl Sr { - #[doc = "Data ready"] - pub const fn drdy(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Data ready"] - pub fn set_drdy(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Clock error current status"] - pub const fn cecs(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Clock error current status"] - pub fn set_cecs(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Seed error current status"] - pub const fn secs(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Seed error current status"] - pub fn set_secs(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Clock error interrupt status"] - pub const fn ceis(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Clock error interrupt status"] - pub fn set_ceis(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Seed error interrupt status"] - pub const fn seis(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Seed error interrupt status"] - pub fn set_seis(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - } - impl Default for Sr { - fn default() -> Sr { - Sr(0) - } - } - #[doc = "control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr(pub u32); - impl Cr { - #[doc = "Random number generator enable"] - pub const fn rngen(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Random number generator enable"] - pub fn set_rngen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Interrupt enable"] - pub const fn ie(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Interrupt enable"] - pub fn set_ie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - } - impl Default for Cr { - fn default() -> Cr { - Cr(0) - } - } - } -} -pub mod gpio_v2 { - use crate::generic::*; - #[doc = "General-purpose I/Os"] - #[derive(Copy, Clone)] - pub struct Gpio(pub *mut u8); - unsafe impl Send for Gpio {} - unsafe impl Sync for Gpio {} - impl Gpio { - #[doc = "GPIO port mode register"] - pub fn moder(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "GPIO port output type register"] - pub fn otyper(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "GPIO port output speed register"] - pub fn ospeedr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "GPIO port pull-up/pull-down register"] - pub fn pupdr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "GPIO port input data register"] - pub fn idr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "GPIO port output data register"] - pub fn odr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "GPIO port bit set/reset register"] - pub fn bsrr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } - } - #[doc = "GPIO port configuration lock register"] - pub fn lckr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(28usize)) } - } - #[doc = "GPIO alternate function register (low, high)"] - pub fn afr(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(32usize + n * 4usize)) } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ot(pub u8); - impl Ot { - #[doc = "Output push-pull (reset state)"] - pub const PUSHPULL: Self = Self(0); - #[doc = "Output open-drain"] - pub const OPENDRAIN: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pupdr(pub u8); - impl Pupdr { - #[doc = "No pull-up, pull-down"] - pub const FLOATING: Self = Self(0); - #[doc = "Pull-up"] - pub const PULLUP: Self = Self(0x01); - #[doc = "Pull-down"] - pub const PULLDOWN: Self = Self(0x02); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Afr(pub u8); - impl Afr { - #[doc = "AF0"] - pub const AF0: Self = Self(0); - #[doc = "AF1"] - pub const AF1: Self = Self(0x01); - #[doc = "AF2"] - pub const AF2: Self = Self(0x02); - #[doc = "AF3"] - pub const AF3: Self = Self(0x03); - #[doc = "AF4"] - pub const AF4: Self = Self(0x04); - #[doc = "AF5"] - pub const AF5: Self = Self(0x05); - #[doc = "AF6"] - pub const AF6: Self = Self(0x06); - #[doc = "AF7"] - pub const AF7: Self = Self(0x07); - #[doc = "AF8"] - pub const AF8: Self = Self(0x08); - #[doc = "AF9"] - pub const AF9: Self = Self(0x09); - #[doc = "AF10"] - pub const AF10: Self = Self(0x0a); - #[doc = "AF11"] - pub const AF11: Self = Self(0x0b); - #[doc = "AF12"] - pub const AF12: Self = Self(0x0c); - #[doc = "AF13"] - pub const AF13: Self = Self(0x0d); - #[doc = "AF14"] - pub const AF14: Self = Self(0x0e); - #[doc = "AF15"] - pub const AF15: Self = Self(0x0f); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Moder(pub u8); - impl Moder { - #[doc = "Input mode (reset state)"] - pub const INPUT: Self = Self(0); - #[doc = "General purpose output mode"] - pub const OUTPUT: Self = Self(0x01); - #[doc = "Alternate function mode"] - pub const ALTERNATE: Self = Self(0x02); - #[doc = "Analog mode"] - pub const ANALOG: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ospeedr(pub u8); - impl Ospeedr { - #[doc = "Low speed"] - pub const LOWSPEED: Self = Self(0); - #[doc = "Medium speed"] - pub const MEDIUMSPEED: Self = Self(0x01); - #[doc = "High speed"] - pub const HIGHSPEED: Self = Self(0x02); - #[doc = "Very high speed"] - pub const VERYHIGHSPEED: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Idr(pub u8); - impl Idr { - #[doc = "Input is logic low"] - pub const LOW: Self = Self(0); - #[doc = "Input is logic high"] - pub const HIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Odr(pub u8); - impl Odr { - #[doc = "Set output to logic low"] - pub const LOW: Self = Self(0); - #[doc = "Set output to logic high"] - pub const HIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Brw(pub u8); - impl Brw { - #[doc = "Resets the corresponding ODRx bit"] - pub const RESET: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bsw(pub u8); - impl Bsw { - #[doc = "Sets the corresponding ODRx bit"] - pub const SET: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lckk(pub u8); - impl Lckk { - #[doc = "Port configuration lock key not active"] - pub const NOTACTIVE: Self = Self(0); - #[doc = "Port configuration lock key active"] - pub const ACTIVE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lck(pub u8); - impl Lck { - #[doc = "Port configuration not locked"] - pub const UNLOCKED: Self = Self(0); - #[doc = "Port configuration locked"] - pub const LOCKED: Self = Self(0x01); - } - } - pub mod regs { - use crate::generic::*; - #[doc = "GPIO alternate function register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Afr(pub u32); - impl Afr { - #[doc = "Alternate function selection for port x bit y (y = 0..15)"] - pub fn afr(&self, n: usize) -> super::vals::Afr { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x0f; - super::vals::Afr(val as u8) - } - #[doc = "Alternate function selection for port x bit y (y = 0..15)"] - pub fn set_afr(&mut self, n: usize, val: super::vals::Afr) { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); - } - } - impl Default for Afr { - fn default() -> Afr { - Afr(0) - } - } - #[doc = "GPIO port configuration lock register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Lckr(pub u32); - impl Lckr { - #[doc = "Port x lock bit y (y= 0..15)"] - pub fn lck(&self, n: usize) -> super::vals::Lck { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Lck(val as u8) - } - #[doc = "Port x lock bit y (y= 0..15)"] - pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - #[doc = "Port x lock bit y (y= 0..15)"] - pub const fn lckk(&self) -> super::vals::Lckk { - let val = (self.0 >> 16usize) & 0x01; - super::vals::Lckk(val as u8) - } - #[doc = "Port x lock bit y (y= 0..15)"] - pub fn set_lckk(&mut self, val: super::vals::Lckk) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); - } - } - impl Default for Lckr { - fn default() -> Lckr { - Lckr(0) - } - } - #[doc = "GPIO port output speed register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ospeedr(pub u32); - impl Ospeedr { - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Ospeedr(val as u8) - } - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - } - impl Default for Ospeedr { - fn default() -> Ospeedr { - Ospeedr(0) - } - } - #[doc = "GPIO port input data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Idr(pub u32); - impl Idr { - #[doc = "Port input data (y = 0..15)"] - pub fn idr(&self, n: usize) -> super::vals::Idr { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Idr(val as u8) - } - #[doc = "Port input data (y = 0..15)"] - pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); } } - impl Default for Idr { - fn default() -> Idr { - Idr(0) - } - } - #[doc = "GPIO port bit set/reset register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Bsrr(pub u32); - impl Bsrr { - #[doc = "Port x set bit y (y= 0..15)"] - pub fn bs(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Port x set bit y (y= 0..15)"] - pub fn set_bs(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Port x set bit y (y= 0..15)"] - pub fn br(&self, n: usize) -> bool { - assert!(n < 16usize); - let offs = 16usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Port x set bit y (y= 0..15)"] - pub fn set_br(&mut self, n: usize, val: bool) { - assert!(n < 16usize); - let offs = 16usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Bsrr { - fn default() -> Bsrr { - Bsrr(0) - } - } - #[doc = "GPIO port output type register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Otyper(pub u32); - impl Otyper { - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn ot(&self, n: usize) -> super::vals::Ot { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Ot(val as u8) - } - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn set_ot(&mut self, n: usize, val: super::vals::Ot) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Otyper { - fn default() -> Otyper { - Otyper(0) - } - } - #[doc = "GPIO port mode register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Moder(pub u32); - impl Moder { - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn moder(&self, n: usize) -> super::vals::Moder { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Moder(val as u8) - } - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - } - impl Default for Moder { - fn default() -> Moder { - Moder(0) - } - } - #[doc = "GPIO port pull-up/pull-down register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pupdr(pub u32); - impl Pupdr { - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn pupdr(&self, n: usize) -> super::vals::Pupdr { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - let val = (self.0 >> offs) & 0x03; - super::vals::Pupdr(val as u8) - } - #[doc = "Port x configuration bits (y = 0..15)"] - pub fn set_pupdr(&mut self, n: usize, val: super::vals::Pupdr) { - assert!(n < 16usize); - let offs = 0usize + n * 2usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); - } - } - impl Default for Pupdr { - fn default() -> Pupdr { - Pupdr(0) - } - } - #[doc = "GPIO port output data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Odr(pub u32); - impl Odr { - #[doc = "Port output data (y = 0..15)"] - pub fn odr(&self, n: usize) -> super::vals::Odr { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - super::vals::Odr(val as u8) - } - #[doc = "Port output data (y = 0..15)"] - pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { - assert!(n < 16usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); - } - } - impl Default for Odr { - fn default() -> Odr { - Odr(0) - } - } - } -} -pub mod syscfg_l4 { - use crate::generic::*; - #[doc = "System configuration controller"] - #[derive(Copy, Clone)] - pub struct Syscfg(pub *mut u8); - unsafe impl Send for Syscfg {} - unsafe impl Sync for Syscfg {} - impl Syscfg { - #[doc = "memory remap register"] - pub fn memrmp(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "configuration register 1"] - pub fn cfgr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "external interrupt configuration register 1"] - pub fn exticr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } - } - #[doc = "SCSR"] - pub fn scsr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } - } - #[doc = "CFGR2"] - pub fn cfgr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(28usize)) } - } - #[doc = "SWPR"] - pub fn swpr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(32usize)) } - } - #[doc = "SKR"] - pub fn skr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "CFGR2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cfgr2(pub u32); - impl Cfgr2 { - #[doc = "Cortex LOCKUP (Hardfault) output enable bit"] - pub const fn cll(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Cortex LOCKUP (Hardfault) output enable bit"] - pub fn set_cll(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "SRAM2 parity lock bit"] - pub const fn spl(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "SRAM2 parity lock bit"] - pub fn set_spl(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "PVD lock enable bit"] - pub const fn pvdl(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "PVD lock enable bit"] - pub fn set_pvdl(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "ECC Lock"] - pub const fn eccl(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "ECC Lock"] - pub fn set_eccl(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "SRAM2 parity error flag"] - pub const fn spf(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "SRAM2 parity error flag"] - pub fn set_spf(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for Cfgr2 { - fn default() -> Cfgr2 { - Cfgr2(0) - } - } - #[doc = "configuration register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cfgr1(pub u32); - impl Cfgr1 { - #[doc = "Firewall disable"] - pub const fn fwdis(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Firewall disable"] - pub fn set_fwdis(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "I/O analog switch voltage booster enable"] - pub const fn boosten(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "I/O analog switch voltage booster enable"] - pub fn set_boosten(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"] - pub const fn i2c_pb6_fmp(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"] - pub fn set_i2c_pb6_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"] - pub const fn i2c_pb7_fmp(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"] - pub fn set_i2c_pb7_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"] - pub const fn i2c_pb8_fmp(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"] - pub fn set_i2c_pb8_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"] - pub const fn i2c_pb9_fmp(&self) -> bool { - let val = (self.0 >> 19usize) & 0x01; - val != 0 - } - #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"] - pub fn set_i2c_pb9_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); - } - #[doc = "I2C1 Fast-mode Plus driving capability activation"] - pub const fn i2c1_fmp(&self) -> bool { - let val = (self.0 >> 20usize) & 0x01; - val != 0 - } - #[doc = "I2C1 Fast-mode Plus driving capability activation"] - pub fn set_i2c1_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); - } - #[doc = "I2C2 Fast-mode Plus driving capability activation"] - pub const fn i2c2_fmp(&self) -> bool { - let val = (self.0 >> 21usize) & 0x01; - val != 0 - } - #[doc = "I2C2 Fast-mode Plus driving capability activation"] - pub fn set_i2c2_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); - } - #[doc = "I2C3 Fast-mode Plus driving capability activation"] - pub const fn i2c3_fmp(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; - val != 0 - } - #[doc = "I2C3 Fast-mode Plus driving capability activation"] - pub fn set_i2c3_fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); - } - #[doc = "Floating Point Unit interrupts enable bits"] - pub const fn fpu_ie(&self) -> u8 { - let val = (self.0 >> 26usize) & 0x3f; - val as u8 - } - #[doc = "Floating Point Unit interrupts enable bits"] - pub fn set_fpu_ie(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 26usize)) | (((val as u32) & 0x3f) << 26usize); - } - } - impl Default for Cfgr1 { - fn default() -> Cfgr1 { - Cfgr1(0) - } - } - #[doc = "external interrupt configuration register 4"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Exticr(pub u32); - impl Exticr { - #[doc = "EXTI12 configuration bits"] - pub fn exti(&self, n: usize) -> u8 { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x0f; - val as u8 - } - #[doc = "EXTI12 configuration bits"] - pub fn set_exti(&mut self, n: usize, val: u8) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); - } - } - impl Default for Exticr { - fn default() -> Exticr { - Exticr(0) - } - } - #[doc = "memory remap register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Memrmp(pub u32); - impl Memrmp { - #[doc = "Memory mapping selection"] - pub const fn mem_mode(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Memory mapping selection"] - pub fn set_mem_mode(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "QUADSPI memory mapping swap"] - pub const fn qfs(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "QUADSPI memory mapping swap"] - pub fn set_qfs(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Flash Bank mode selection"] - pub const fn fb_mode(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Flash Bank mode selection"] - pub fn set_fb_mode(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for Memrmp { - fn default() -> Memrmp { - Memrmp(0) - } - } - #[doc = "SKR"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Skr(pub u32); - impl Skr { - #[doc = "SRAM2 write protection key for software erase"] - pub const fn key(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "SRAM2 write protection key for software erase"] - pub fn set_key(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - } - impl Default for Skr { - fn default() -> Skr { - Skr(0) - } - } - #[doc = "SCSR"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Scsr(pub u32); - impl Scsr { - #[doc = "SRAM2 Erase"] - pub const fn sram2er(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "SRAM2 Erase"] - pub fn set_sram2er(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "SRAM2 busy by erase operation"] - pub const fn sram2bsy(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "SRAM2 busy by erase operation"] - pub fn set_sram2bsy(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - } - impl Default for Scsr { - fn default() -> Scsr { - Scsr(0) - } - } - #[doc = "SWPR"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Swpr(pub u32); - impl Swpr { - #[doc = "SRAWM2 write protection."] - pub fn pwp(&self, n: usize) -> bool { - assert!(n < 32usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "SRAWM2 write protection."] - pub fn set_pwp(&mut self, n: usize, val: bool) { - assert!(n < 32usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Swpr { - fn default() -> Swpr { - Swpr(0) - } - } - } -} -pub mod generic { - use core::marker::PhantomData; - #[derive(Copy, Clone)] - pub struct RW; - #[derive(Copy, Clone)] - pub struct R; - #[derive(Copy, Clone)] - pub struct W; - mod sealed { - use super::*; - pub trait Access {} - impl Access for R {} - impl Access for W {} - impl Access for RW {} - } - pub trait Access: sealed::Access + Copy {} - impl Access for R {} - impl Access for W {} - impl Access for RW {} - pub trait Read: Access {} - impl Read for RW {} - impl Read for R {} - pub trait Write: Access {} - impl Write for RW {} - impl Write for W {} - #[derive(Copy, Clone)] - pub struct Reg { - ptr: *mut u8, - phantom: PhantomData<*mut (T, A)>, - } - unsafe impl Send for Reg {} - unsafe impl Sync for Reg {} - impl Reg { - pub fn from_ptr(ptr: *mut u8) -> Self { - Self { - ptr, - phantom: PhantomData, - } - } - pub fn ptr(&self) -> *mut T { - self.ptr as _ - } - } - impl Reg { - pub unsafe fn read(&self) -> T { - (self.ptr as *mut T).read_volatile() - } - } - impl Reg { - pub unsafe fn write_value(&self, val: T) { - (self.ptr as *mut T).write_volatile(val) - } - } - impl Reg { - pub unsafe fn write(&self, f: impl FnOnce(&mut T) -> R) -> R { - let mut val = Default::default(); - let res = f(&mut val); - self.write_value(val); - res - } - } - impl Reg { - pub unsafe fn modify(&self, f: impl FnOnce(&mut T) -> R) -> R { - let mut val = self.read(); - let res = f(&mut val); - self.write_value(val); - res - } - } -} -pub mod spi_v2 { - use crate::generic::*; - #[doc = "Serial peripheral interface"] - #[derive(Copy, Clone)] - pub struct Spi(pub *mut u8); - unsafe impl Send for Spi {} - unsafe impl Sync for Spi {} - impl Spi { - #[doc = "control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "data register"] - pub fn dr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "CRC polynomial register"] - pub fn crcpr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "RX CRC register"] - pub fn rxcrcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "TX CRC register"] - pub fn txcrcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "TX CRC register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Txcrcr(pub u32); - impl Txcrcr { - #[doc = "Tx CRC register"] - pub const fn tx_crc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Tx CRC register"] - pub fn set_tx_crc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Txcrcr { - fn default() -> Txcrcr { - Txcrcr(0) - } - } - #[doc = "control register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1(pub u32); - impl Cr1 { - #[doc = "Clock phase"] - pub const fn cpha(&self) -> super::vals::Cpha { - let val = (self.0 >> 0usize) & 0x01; - super::vals::Cpha(val as u8) - } - #[doc = "Clock phase"] - pub fn set_cpha(&mut self, val: super::vals::Cpha) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); - } - #[doc = "Clock polarity"] - pub const fn cpol(&self) -> super::vals::Cpol { - let val = (self.0 >> 1usize) & 0x01; - super::vals::Cpol(val as u8) - } - #[doc = "Clock polarity"] - pub fn set_cpol(&mut self, val: super::vals::Cpol) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); - } - #[doc = "Master selection"] - pub const fn mstr(&self) -> super::vals::Mstr { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Mstr(val as u8) - } - #[doc = "Master selection"] - pub fn set_mstr(&mut self, val: super::vals::Mstr) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "Baud rate control"] - pub const fn br(&self) -> super::vals::Br { - let val = (self.0 >> 3usize) & 0x07; - super::vals::Br(val as u8) - } - #[doc = "Baud rate control"] - pub fn set_br(&mut self, val: super::vals::Br) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); - } - #[doc = "SPI enable"] - pub const fn spe(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "SPI enable"] - pub fn set_spe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Frame format"] - pub const fn lsbfirst(&self) -> super::vals::Lsbfirst { - let val = (self.0 >> 7usize) & 0x01; - super::vals::Lsbfirst(val as u8) - } - #[doc = "Frame format"] - pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); - } - #[doc = "Internal slave select"] - pub const fn ssi(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Internal slave select"] - pub fn set_ssi(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Software slave management"] - pub const fn ssm(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Software slave management"] - pub fn set_ssm(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Receive only"] - pub const fn rxonly(&self) -> super::vals::Rxonly { - let val = (self.0 >> 10usize) & 0x01; - super::vals::Rxonly(val as u8) - } - #[doc = "Receive only"] - pub fn set_rxonly(&mut self, val: super::vals::Rxonly) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); - } - #[doc = "CRC length"] - pub const fn crcl(&self) -> super::vals::Crcl { - let val = (self.0 >> 11usize) & 0x01; - super::vals::Crcl(val as u8) - } - #[doc = "CRC length"] - pub fn set_crcl(&mut self, val: super::vals::Crcl) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); - } - #[doc = "CRC transfer next"] - pub const fn crcnext(&self) -> super::vals::Crcnext { - let val = (self.0 >> 12usize) & 0x01; - super::vals::Crcnext(val as u8) - } - #[doc = "CRC transfer next"] - pub fn set_crcnext(&mut self, val: super::vals::Crcnext) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); - } - #[doc = "Hardware CRC calculation enable"] - pub const fn crcen(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "Hardware CRC calculation enable"] - pub fn set_crcen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - #[doc = "Output enable in bidirectional mode"] - pub const fn bidioe(&self) -> super::vals::Bidioe { - let val = (self.0 >> 14usize) & 0x01; - super::vals::Bidioe(val as u8) - } - #[doc = "Output enable in bidirectional mode"] - pub fn set_bidioe(&mut self, val: super::vals::Bidioe) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); - } - #[doc = "Bidirectional data mode enable"] - pub const fn bidimode(&self) -> super::vals::Bidimode { - let val = (self.0 >> 15usize) & 0x01; - super::vals::Bidimode(val as u8) - } - #[doc = "Bidirectional data mode enable"] - pub fn set_bidimode(&mut self, val: super::vals::Bidimode) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); - } - } - impl Default for Cr1 { - fn default() -> Cr1 { - Cr1(0) - } - } - #[doc = "CRC polynomial register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Crcpr(pub u32); - impl Crcpr { - #[doc = "CRC polynomial register"] - pub const fn crcpoly(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "CRC polynomial register"] - pub fn set_crcpoly(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Crcpr { - fn default() -> Crcpr { - Crcpr(0) - } - } - #[doc = "RX CRC register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Rxcrcr(pub u32); - impl Rxcrcr { - #[doc = "Rx CRC register"] - pub const fn rx_crc(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Rx CRC register"] - pub fn set_rx_crc(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Rxcrcr { - fn default() -> Rxcrcr { - Rxcrcr(0) - } - } - #[doc = "data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dr(pub u32); - impl Dr { - #[doc = "Data register"] - pub const fn dr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Data register"] - pub fn set_dr(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Dr { - fn default() -> Dr { - Dr(0) - } - } - #[doc = "status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Sr(pub u32); - impl Sr { - #[doc = "Receive buffer not empty"] - pub const fn rxne(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Receive buffer not empty"] - pub fn set_rxne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Transmit buffer empty"] - pub const fn txe(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Transmit buffer empty"] - pub fn set_txe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "CRC error flag"] - pub const fn crcerr(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "CRC error flag"] - pub fn set_crcerr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Mode fault"] - pub const fn modf(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Mode fault"] - pub fn set_modf(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Overrun flag"] - pub const fn ovr(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Overrun flag"] - pub fn set_ovr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Busy flag"] - pub const fn bsy(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Busy flag"] - pub fn set_bsy(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Frame format error"] - pub const fn fre(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Frame format error"] - pub fn set_fre(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "FIFO reception level"] - pub const fn frlvl(&self) -> u8 { - let val = (self.0 >> 9usize) & 0x03; - val as u8 - } - #[doc = "FIFO reception level"] - pub fn set_frlvl(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 9usize)) | (((val as u32) & 0x03) << 9usize); - } - #[doc = "FIFO Transmission Level"] - pub const fn ftlvl(&self) -> u8 { - let val = (self.0 >> 11usize) & 0x03; - val as u8 - } - #[doc = "FIFO Transmission Level"] - pub fn set_ftlvl(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 11usize)) | (((val as u32) & 0x03) << 11usize); - } - } - impl Default for Sr { - fn default() -> Sr { - Sr(0) - } - } - #[doc = "control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2(pub u32); - impl Cr2 { - #[doc = "Rx buffer DMA enable"] - pub const fn rxdmaen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Rx buffer DMA enable"] - pub fn set_rxdmaen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Tx buffer DMA enable"] - pub const fn txdmaen(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Tx buffer DMA enable"] - pub fn set_txdmaen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "SS output enable"] - pub const fn ssoe(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "SS output enable"] - pub fn set_ssoe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "NSS pulse management"] - pub const fn nssp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "NSS pulse management"] - pub fn set_nssp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Frame format"] - pub const fn frf(&self) -> super::vals::Frf { - let val = (self.0 >> 4usize) & 0x01; - super::vals::Frf(val as u8) - } - #[doc = "Frame format"] - pub fn set_frf(&mut self, val: super::vals::Frf) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); - } - #[doc = "Error interrupt enable"] - pub const fn errie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Error interrupt enable"] - pub fn set_errie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "RX buffer not empty interrupt enable"] - pub const fn rxneie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "RX buffer not empty interrupt enable"] - pub fn set_rxneie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Tx buffer empty interrupt enable"] - pub const fn txeie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Tx buffer empty interrupt enable"] - pub fn set_txeie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Data size"] - pub const fn ds(&self) -> super::vals::Ds { - let val = (self.0 >> 8usize) & 0x0f; - super::vals::Ds(val as u8) - } - #[doc = "Data size"] - pub fn set_ds(&mut self, val: super::vals::Ds) { - self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); - } - #[doc = "FIFO reception threshold"] - pub const fn frxth(&self) -> super::vals::Frxth { - let val = (self.0 >> 12usize) & 0x01; - super::vals::Frxth(val as u8) - } - #[doc = "FIFO reception threshold"] - pub fn set_frxth(&mut self, val: super::vals::Frxth) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); - } - #[doc = "Last DMA transfer for reception"] - pub const fn ldma_rx(&self) -> super::vals::LdmaRx { - let val = (self.0 >> 13usize) & 0x01; - super::vals::LdmaRx(val as u8) - } - #[doc = "Last DMA transfer for reception"] - pub fn set_ldma_rx(&mut self, val: super::vals::LdmaRx) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val.0 as u32) & 0x01) << 13usize); - } - #[doc = "Last DMA transfer for transmission"] - pub const fn ldma_tx(&self) -> super::vals::LdmaTx { - let val = (self.0 >> 14usize) & 0x01; - super::vals::LdmaTx(val as u8) - } - #[doc = "Last DMA transfer for transmission"] - pub fn set_ldma_tx(&mut self, val: super::vals::LdmaTx) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); - } - } - impl Default for Cr2 { - fn default() -> Cr2 { - Cr2(0) + impl Default for Emr { + fn default() -> Emr { + Emr(0) } } } @@ -6352,2752 +9060,44 @@ pub mod spi_v2 { use crate::generic::*; #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ds(pub u8); - impl Ds { - #[doc = "4-bit"] - pub const FOURBIT: Self = Self(0x03); - #[doc = "5-bit"] - pub const FIVEBIT: Self = Self(0x04); - #[doc = "6-bit"] - pub const SIXBIT: Self = Self(0x05); - #[doc = "7-bit"] - pub const SEVENBIT: Self = Self(0x06); - #[doc = "8-bit"] - pub const EIGHTBIT: Self = Self(0x07); - #[doc = "9-bit"] - pub const NINEBIT: Self = Self(0x08); - #[doc = "10-bit"] - pub const TENBIT: Self = Self(0x09); - #[doc = "11-bit"] - pub const ELEVENBIT: Self = Self(0x0a); - #[doc = "12-bit"] - pub const TWELVEBIT: Self = Self(0x0b); - #[doc = "13-bit"] - pub const THIRTEENBIT: Self = Self(0x0c); - #[doc = "14-bit"] - pub const FOURTEENBIT: Self = Self(0x0d); - #[doc = "15-bit"] - pub const FIFTEENBIT: Self = Self(0x0e); - #[doc = "16-bit"] - pub const SIXTEENBIT: Self = Self(0x0f); + pub struct Prw(pub u8); + impl Prw { + #[doc = "Clears pending bit"] + pub const CLEAR: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpha(pub u8); - impl Cpha { - #[doc = "The first clock transition is the first data capture edge"] - pub const FIRSTEDGE: Self = Self(0); - #[doc = "The second clock transition is the first data capture edge"] - pub const SECONDEDGE: Self = Self(0x01); + pub struct Swierw(pub u8); + impl Swierw { + #[doc = "Generates an interrupt request"] + pub const PEND: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct LdmaTx(pub u8); - impl LdmaTx { - #[doc = "Number of data to transfer for transmit is even"] - pub const EVEN: Self = Self(0); - #[doc = "Number of data to transfer for transmit is odd"] - pub const ODD: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frxth(pub u8); - impl Frxth { - #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"] - pub const HALF: Self = Self(0); - #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"] - pub const QUARTER: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpol(pub u8); - impl Cpol { - #[doc = "CK to 0 when idle"] - pub const IDLELOW: Self = Self(0); - #[doc = "CK to 1 when idle"] - pub const IDLEHIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frf(pub u8); - impl Frf { - #[doc = "SPI Motorola mode"] - pub const MOTOROLA: Self = Self(0); - #[doc = "SPI TI mode"] - pub const TI: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Crcl(pub u8); - impl Crcl { - #[doc = "8-bit CRC length"] - pub const EIGHTBIT: Self = Self(0); - #[doc = "16-bit CRC length"] - pub const SIXTEENBIT: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bidimode(pub u8); - impl Bidimode { - #[doc = "2-line unidirectional data mode selected"] - pub const UNIDIRECTIONAL: Self = Self(0); - #[doc = "1-line bidirectional data mode selected"] - pub const BIDIRECTIONAL: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Mstr(pub u8); - impl Mstr { - #[doc = "Slave configuration"] - pub const SLAVE: Self = Self(0); - #[doc = "Master configuration"] - pub const MASTER: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct LdmaRx(pub u8); - impl LdmaRx { - #[doc = "Number of data to transfer for receive is even"] - pub const EVEN: Self = Self(0); - #[doc = "Number of data to transfer for receive is odd"] - pub const ODD: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ftlvlr(pub u8); - impl Ftlvlr { - #[doc = "Tx FIFO Empty"] - pub const EMPTY: Self = Self(0); - #[doc = "Tx 1/4 FIFO"] - pub const QUARTER: Self = Self(0x01); - #[doc = "Tx 1/2 FIFO"] - pub const HALF: Self = Self(0x02); - #[doc = "Tx FIFO full"] - pub const FULL: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Br(pub u8); - impl Br { - #[doc = "f_PCLK / 2"] - pub const DIV2: Self = Self(0); - #[doc = "f_PCLK / 4"] - pub const DIV4: Self = Self(0x01); - #[doc = "f_PCLK / 8"] - pub const DIV8: Self = Self(0x02); - #[doc = "f_PCLK / 16"] - pub const DIV16: Self = Self(0x03); - #[doc = "f_PCLK / 32"] - pub const DIV32: Self = Self(0x04); - #[doc = "f_PCLK / 64"] - pub const DIV64: Self = Self(0x05); - #[doc = "f_PCLK / 128"] - pub const DIV128: Self = Self(0x06); - #[doc = "f_PCLK / 256"] - pub const DIV256: Self = Self(0x07); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Crcnext(pub u8); - impl Crcnext { - #[doc = "Next transmit value is from Tx buffer"] - pub const TXBUFFER: Self = Self(0); - #[doc = "Next transmit value is from Tx CRC register"] - pub const CRC: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Bidioe(pub u8); - impl Bidioe { - #[doc = "Output disabled (receive-only mode)"] - pub const OUTPUTDISABLED: Self = Self(0); - #[doc = "Output enabled (transmit-only mode)"] - pub const OUTPUTENABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frer(pub u8); - impl Frer { - #[doc = "No frame format error"] - pub const NOERROR: Self = Self(0); - #[doc = "A frame format error occurred"] - pub const ERROR: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lsbfirst(pub u8); - impl Lsbfirst { - #[doc = "Data is transmitted/received with the MSB first"] - pub const MSBFIRST: Self = Self(0); - #[doc = "Data is transmitted/received with the LSB first"] - pub const LSBFIRST: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Frlvlr(pub u8); - impl Frlvlr { - #[doc = "Rx FIFO Empty"] - pub const EMPTY: Self = Self(0); - #[doc = "Rx 1/4 FIFO"] - pub const QUARTER: Self = Self(0x01); - #[doc = "Rx 1/2 FIFO"] - pub const HALF: Self = Self(0x02); - #[doc = "Rx FIFO full"] - pub const FULL: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Rxonly(pub u8); - impl Rxonly { - #[doc = "Full duplex (Transmit and receive)"] - pub const FULLDUPLEX: Self = Self(0); - #[doc = "Output disabled (Receive-only mode)"] - pub const OUTPUTDISABLED: Self = Self(0x01); - } - } -} -pub mod usart_v1 { - use crate::generic::*; - #[doc = "Universal asynchronous receiver transmitter"] - #[derive(Copy, Clone)] - pub struct Uart(pub *mut u8); - unsafe impl Send for Uart {} - unsafe impl Sync for Uart {} - impl Uart { - #[doc = "Status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "Data register"] - pub fn dr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "Baud rate register"] - pub fn brr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "Control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "Control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "Control register 3"] - pub fn cr3(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - } - #[doc = "Universal synchronous asynchronous receiver transmitter"] - #[derive(Copy, Clone)] - pub struct Usart(pub *mut u8); - unsafe impl Send for Usart {} - unsafe impl Sync for Usart {} - impl Usart { - #[doc = "Status register"] - pub fn sr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "Data register"] - pub fn dr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "Baud rate register"] - pub fn brr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "Control register 1"] - pub fn cr1(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "Control register 2"] - pub fn cr2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "Control register 3"] - pub fn cr3(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - #[doc = "Guard time and prescaler register"] - pub fn gtpr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(24usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "Status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Sr(pub u32); - impl Sr { - #[doc = "Parity error"] - pub const fn pe(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Parity error"] - pub fn set_pe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Framing error"] - pub const fn fe(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Framing error"] - pub fn set_fe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Noise error flag"] - pub const fn ne(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Noise error flag"] - pub fn set_ne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Overrun error"] - pub const fn ore(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Overrun error"] - pub fn set_ore(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "IDLE line detected"] - pub const fn idle(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "IDLE line detected"] - pub fn set_idle(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Read data register not empty"] - pub const fn rxne(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Read data register not empty"] - pub fn set_rxne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Transmission complete"] - pub const fn tc(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Transmission complete"] - pub fn set_tc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Transmit data register empty"] - pub const fn txe(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Transmit data register empty"] - pub fn set_txe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "LIN break detection flag"] - pub const fn lbd(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "LIN break detection flag"] - pub fn set_lbd(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for Sr { - fn default() -> Sr { - Sr(0) - } - } - #[doc = "Control register 3"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr3(pub u32); - impl Cr3 { - #[doc = "Error interrupt enable"] - pub const fn eie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Error interrupt enable"] - pub fn set_eie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "IrDA mode enable"] - pub const fn iren(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "IrDA mode enable"] - pub fn set_iren(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "IrDA low-power"] - pub const fn irlp(&self) -> super::vals::Irlp { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Irlp(val as u8) - } - #[doc = "IrDA low-power"] - pub fn set_irlp(&mut self, val: super::vals::Irlp) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "Half-duplex selection"] - pub const fn hdsel(&self) -> super::vals::Hdsel { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Hdsel(val as u8) - } - #[doc = "Half-duplex selection"] - pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "DMA enable receiver"] - pub const fn dmar(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "DMA enable receiver"] - pub fn set_dmar(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "DMA enable transmitter"] - pub const fn dmat(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "DMA enable transmitter"] - pub fn set_dmat(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - } - impl Default for Cr3 { - fn default() -> Cr3 { - Cr3(0) - } - } - #[doc = "Status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct SrUsart(pub u32); - impl SrUsart { - #[doc = "Parity error"] - pub const fn pe(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Parity error"] - pub fn set_pe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Framing error"] - pub const fn fe(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Framing error"] - pub fn set_fe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Noise error flag"] - pub const fn ne(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Noise error flag"] - pub fn set_ne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Overrun error"] - pub const fn ore(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Overrun error"] - pub fn set_ore(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "IDLE line detected"] - pub const fn idle(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "IDLE line detected"] - pub fn set_idle(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Read data register not empty"] - pub const fn rxne(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Read data register not empty"] - pub fn set_rxne(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Transmission complete"] - pub const fn tc(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Transmission complete"] - pub fn set_tc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Transmit data register empty"] - pub const fn txe(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Transmit data register empty"] - pub fn set_txe(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "LIN break detection flag"] - pub const fn lbd(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "LIN break detection flag"] - pub fn set_lbd(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "CTS flag"] - pub const fn cts(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "CTS flag"] - pub fn set_cts(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - } - impl Default for SrUsart { - fn default() -> SrUsart { - SrUsart(0) - } - } - #[doc = "Control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2Usart(pub u32); - impl Cr2Usart { - #[doc = "Address of the USART node"] - pub const fn add(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Address of the USART node"] - pub fn set_add(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "lin break detection length"] - pub const fn lbdl(&self) -> super::vals::Lbdl { - let val = (self.0 >> 5usize) & 0x01; - super::vals::Lbdl(val as u8) - } - #[doc = "lin break detection length"] - pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); - } - #[doc = "LIN break detection interrupt enable"] - pub const fn lbdie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "LIN break detection interrupt enable"] - pub fn set_lbdie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Last bit clock pulse"] - pub const fn lbcl(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Last bit clock pulse"] - pub fn set_lbcl(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Clock phase"] - pub const fn cpha(&self) -> super::vals::Cpha { - let val = (self.0 >> 9usize) & 0x01; - super::vals::Cpha(val as u8) - } - #[doc = "Clock phase"] - pub fn set_cpha(&mut self, val: super::vals::Cpha) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); - } - #[doc = "Clock polarity"] - pub const fn cpol(&self) -> super::vals::Cpol { - let val = (self.0 >> 10usize) & 0x01; - super::vals::Cpol(val as u8) - } - #[doc = "Clock polarity"] - pub fn set_cpol(&mut self, val: super::vals::Cpol) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); - } - #[doc = "Clock enable"] - pub const fn clken(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 - } - #[doc = "Clock enable"] - pub fn set_clken(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); - } - #[doc = "STOP bits"] - pub const fn stop(&self) -> super::vals::Stop { - let val = (self.0 >> 12usize) & 0x03; - super::vals::Stop(val as u8) - } - #[doc = "STOP bits"] - pub fn set_stop(&mut self, val: super::vals::Stop) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); - } - #[doc = "LIN mode enable"] - pub const fn linen(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "LIN mode enable"] - pub fn set_linen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - } - impl Default for Cr2Usart { - fn default() -> Cr2Usart { - Cr2Usart(0) - } - } - #[doc = "Control register 3"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr3Usart(pub u32); - impl Cr3Usart { - #[doc = "Error interrupt enable"] - pub const fn eie(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Error interrupt enable"] - pub fn set_eie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "IrDA mode enable"] - pub const fn iren(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "IrDA mode enable"] - pub fn set_iren(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "IrDA low-power"] - pub const fn irlp(&self) -> super::vals::Irlp { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Irlp(val as u8) - } - #[doc = "IrDA low-power"] - pub fn set_irlp(&mut self, val: super::vals::Irlp) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "Half-duplex selection"] - pub const fn hdsel(&self) -> super::vals::Hdsel { - let val = (self.0 >> 3usize) & 0x01; - super::vals::Hdsel(val as u8) - } - #[doc = "Half-duplex selection"] - pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); - } - #[doc = "Smartcard NACK enable"] - pub const fn nack(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "Smartcard NACK enable"] - pub fn set_nack(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Smartcard mode enable"] - pub const fn scen(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Smartcard mode enable"] - pub fn set_scen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "DMA enable receiver"] - pub const fn dmar(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "DMA enable receiver"] - pub fn set_dmar(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "DMA enable transmitter"] - pub const fn dmat(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "DMA enable transmitter"] - pub fn set_dmat(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "RTS enable"] - pub const fn rtse(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "RTS enable"] - pub fn set_rtse(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "CTS enable"] - pub const fn ctse(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "CTS enable"] - pub fn set_ctse(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "CTS interrupt enable"] - pub const fn ctsie(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "CTS interrupt enable"] - pub fn set_ctsie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - } - impl Default for Cr3Usart { - fn default() -> Cr3Usart { - Cr3Usart(0) - } - } - #[doc = "Data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Dr(pub u32); - impl Dr { - #[doc = "Data value"] - pub const fn dr(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x01ff; - val as u16 - } - #[doc = "Data value"] - pub fn set_dr(&mut self, val: u16) { - self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize); - } - } - impl Default for Dr { - fn default() -> Dr { - Dr(0) - } - } - #[doc = "Control register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr2(pub u32); - impl Cr2 { - #[doc = "Address of the USART node"] - pub const fn add(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Address of the USART node"] - pub fn set_add(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "lin break detection length"] - pub const fn lbdl(&self) -> super::vals::Lbdl { - let val = (self.0 >> 5usize) & 0x01; - super::vals::Lbdl(val as u8) - } - #[doc = "lin break detection length"] - pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); - } - #[doc = "LIN break detection interrupt enable"] - pub const fn lbdie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "LIN break detection interrupt enable"] - pub fn set_lbdie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "STOP bits"] - pub const fn stop(&self) -> super::vals::Stop { - let val = (self.0 >> 12usize) & 0x03; - super::vals::Stop(val as u8) - } - #[doc = "STOP bits"] - pub fn set_stop(&mut self, val: super::vals::Stop) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); - } - #[doc = "LIN mode enable"] - pub const fn linen(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 - } - #[doc = "LIN mode enable"] - pub fn set_linen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); - } - } - impl Default for Cr2 { - fn default() -> Cr2 { - Cr2(0) - } - } - #[doc = "Baud rate register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Brr(pub u32); - impl Brr { - #[doc = "fraction of USARTDIV"] - pub const fn div_fraction(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "fraction of USARTDIV"] - pub fn set_div_fraction(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "mantissa of USARTDIV"] - pub const fn div_mantissa(&self) -> u16 { - let val = (self.0 >> 4usize) & 0x0fff; - val as u16 - } - #[doc = "mantissa of USARTDIV"] - pub fn set_div_mantissa(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize); - } - } - impl Default for Brr { - fn default() -> Brr { - Brr(0) - } - } - #[doc = "Control register 1"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr1(pub u32); - impl Cr1 { - #[doc = "Send break"] - pub const fn sbk(&self) -> super::vals::Sbk { - let val = (self.0 >> 0usize) & 0x01; - super::vals::Sbk(val as u8) - } - #[doc = "Send break"] - pub fn set_sbk(&mut self, val: super::vals::Sbk) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); - } - #[doc = "Receiver wakeup"] - pub const fn rwu(&self) -> super::vals::Rwu { - let val = (self.0 >> 1usize) & 0x01; - super::vals::Rwu(val as u8) - } - #[doc = "Receiver wakeup"] - pub fn set_rwu(&mut self, val: super::vals::Rwu) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); - } - #[doc = "Receiver enable"] - pub const fn re(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Receiver enable"] - pub fn set_re(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Transmitter enable"] - pub const fn te(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Transmitter enable"] - pub fn set_te(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "IDLE interrupt enable"] - pub const fn idleie(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "IDLE interrupt enable"] - pub fn set_idleie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "RXNE interrupt enable"] - pub const fn rxneie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "RXNE interrupt enable"] - pub fn set_rxneie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Transmission complete interrupt enable"] - pub const fn tcie(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Transmission complete interrupt enable"] - pub fn set_tcie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "TXE interrupt enable"] - pub const fn txeie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "TXE interrupt enable"] - pub fn set_txeie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "PE interrupt enable"] - pub const fn peie(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "PE interrupt enable"] - pub fn set_peie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Parity selection"] - pub const fn ps(&self) -> super::vals::Ps { - let val = (self.0 >> 9usize) & 0x01; - super::vals::Ps(val as u8) - } - #[doc = "Parity selection"] - pub fn set_ps(&mut self, val: super::vals::Ps) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); - } - #[doc = "Parity control enable"] - pub const fn pce(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 - } - #[doc = "Parity control enable"] - pub fn set_pce(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); - } - #[doc = "Wakeup method"] - pub const fn wake(&self) -> super::vals::Wake { - let val = (self.0 >> 11usize) & 0x01; - super::vals::Wake(val as u8) - } - #[doc = "Wakeup method"] - pub fn set_wake(&mut self, val: super::vals::Wake) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); - } - #[doc = "Word length"] - pub const fn m(&self) -> super::vals::M { - let val = (self.0 >> 12usize) & 0x01; - super::vals::M(val as u8) - } - #[doc = "Word length"] - pub fn set_m(&mut self, val: super::vals::M) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); - } - #[doc = "USART enable"] - pub const fn ue(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 - } - #[doc = "USART enable"] - pub fn set_ue(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); - } - } - impl Default for Cr1 { - fn default() -> Cr1 { - Cr1(0) - } - } - #[doc = "Guard time and prescaler register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Gtpr(pub u32); - impl Gtpr { - #[doc = "Prescaler value"] - pub const fn psc(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Prescaler value"] - pub fn set_psc(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - #[doc = "Guard time value"] - pub const fn gt(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Guard time value"] - pub fn set_gt(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - } - impl Default for Gtpr { - fn default() -> Gtpr { - Gtpr(0) - } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Wake(pub u8); - impl Wake { - #[doc = "USART wakeup on idle line"] - pub const IDLELINE: Self = Self(0); - #[doc = "USART wakeup on address mark"] - pub const ADDRESSMARK: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct M(pub u8); - impl M { - #[doc = "8 data bits"] - pub const M8: Self = Self(0); - #[doc = "9 data bits"] - pub const M9: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ps(pub u8); - impl Ps { - #[doc = "Even parity"] - pub const EVEN: Self = Self(0); - #[doc = "Odd parity"] - pub const ODD: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Sbk(pub u8); - impl Sbk { - #[doc = "No break character is transmitted"] - pub const NOBREAK: Self = Self(0); - #[doc = "Break character transmitted"] - pub const BREAK: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Hdsel(pub u8); - impl Hdsel { - #[doc = "Half duplex mode is not selected"] - pub const FULLDUPLEX: Self = Self(0); - #[doc = "Half duplex mode is selected"] - pub const HALFDUPLEX: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Rwu(pub u8); - impl Rwu { - #[doc = "Receiver in active mode"] - pub const ACTIVE: Self = Self(0); - #[doc = "Receiver in mute mode"] - pub const MUTE: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpol(pub u8); - impl Cpol { - #[doc = "Steady low value on CK pin outside transmission window"] - pub const LOW: Self = Self(0); - #[doc = "Steady high value on CK pin outside transmission window"] - pub const HIGH: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Stop(pub u8); - impl Stop { - #[doc = "1 stop bit"] - pub const STOP1: Self = Self(0); - #[doc = "0.5 stop bits"] - pub const STOP0P5: Self = Self(0x01); - #[doc = "2 stop bits"] - pub const STOP2: Self = Self(0x02); - #[doc = "1.5 stop bits"] - pub const STOP1P5: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Cpha(pub u8); - impl Cpha { - #[doc = "The first clock transition is the first data capture edge"] - pub const FIRST: Self = Self(0); - #[doc = "The second clock transition is the first data capture edge"] - pub const SECOND: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Irlp(pub u8); - impl Irlp { - #[doc = "Normal mode"] - pub const NORMAL: Self = Self(0); - #[doc = "Low-power mode"] - pub const LOWPOWER: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Lbdl(pub u8); - impl Lbdl { - #[doc = "10-bit break detection"] - pub const LBDL10: Self = Self(0); - #[doc = "11-bit break detection"] - pub const LBDL11: Self = Self(0x01); - } - } -} -pub mod syscfg_f4 { - use crate::generic::*; - #[doc = "System configuration controller"] - #[derive(Copy, Clone)] - pub struct Syscfg(pub *mut u8); - unsafe impl Send for Syscfg {} - unsafe impl Sync for Syscfg {} - impl Syscfg { - #[doc = "memory remap register"] - pub fn memrm(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "peripheral mode configuration register"] - pub fn pmc(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "external interrupt configuration register"] - pub fn exticr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } - } - #[doc = "Compensation cell control register"] - pub fn cmpcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(32usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "memory remap register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Memrm(pub u32); - impl Memrm { - #[doc = "Memory mapping selection"] - pub const fn mem_mode(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - #[doc = "Memory mapping selection"] - pub fn set_mem_mode(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); - } - #[doc = "Flash bank mode selection"] - pub const fn fb_mode(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Flash bank mode selection"] - pub fn set_fb_mode(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "FMC memory mapping swap"] - pub const fn swp_fmc(&self) -> u8 { - let val = (self.0 >> 10usize) & 0x03; - val as u8 - } - #[doc = "FMC memory mapping swap"] - pub fn set_swp_fmc(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize); - } - } - impl Default for Memrm { - fn default() -> Memrm { - Memrm(0) - } - } - #[doc = "peripheral mode configuration register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pmc(pub u32); - impl Pmc { - #[doc = "ADC1DC2"] - pub const fn adc1dc2(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "ADC1DC2"] - pub fn set_adc1dc2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - #[doc = "ADC2DC2"] - pub const fn adc2dc2(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 - } - #[doc = "ADC2DC2"] - pub fn set_adc2dc2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); - } - #[doc = "ADC3DC2"] - pub const fn adc3dc2(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[doc = "ADC3DC2"] - pub fn set_adc3dc2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); - } - #[doc = "Ethernet PHY interface selection"] - pub const fn mii_rmii_sel(&self) -> bool { - let val = (self.0 >> 23usize) & 0x01; - val != 0 - } - #[doc = "Ethernet PHY interface selection"] - pub fn set_mii_rmii_sel(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); - } - } - impl Default for Pmc { - fn default() -> Pmc { - Pmc(0) - } - } - #[doc = "external interrupt configuration register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Exticr(pub u32); - impl Exticr { - #[doc = "EXTI x configuration"] - pub fn exti(&self, n: usize) -> u8 { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x0f; - val as u8 - } - #[doc = "EXTI x configuration"] - pub fn set_exti(&mut self, n: usize, val: u8) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); - } - } - impl Default for Exticr { - fn default() -> Exticr { - Exticr(0) - } - } - #[doc = "Compensation cell control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cmpcr(pub u32); - impl Cmpcr { - #[doc = "Compensation cell power-down"] - pub const fn cmp_pd(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Compensation cell power-down"] - pub fn set_cmp_pd(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "READY"] - pub const fn ready(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "READY"] - pub fn set_ready(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - } - impl Default for Cmpcr { - fn default() -> Cmpcr { - Cmpcr(0) - } - } - } -} -pub mod dma_v2 { - use crate::generic::*; - #[doc = "DMA controller"] - #[derive(Copy, Clone)] - pub struct Dma(pub *mut u8); - unsafe impl Send for Dma {} - unsafe impl Sync for Dma {} - impl Dma { - #[doc = "low interrupt status register"] - pub fn isr(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) } - } - #[doc = "low interrupt flag clear register"] - pub fn ifcr(self, n: usize) -> Reg { - assert!(n < 2usize); - unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } - } - #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"] - pub fn st(self, n: usize) -> St { - assert!(n < 8usize); - unsafe { St(self.0.add(16usize + n * 24usize)) } - } - } - #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"] - #[derive(Copy, Clone)] - pub struct St(pub *mut u8); - unsafe impl Send for St {} - unsafe impl Sync for St {} - impl St { - #[doc = "stream x configuration register"] - pub fn cr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(0usize)) } - } - #[doc = "stream x number of data register"] - pub fn ndtr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "stream x peripheral address register"] - pub fn par(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(8usize)) } - } - #[doc = "stream x memory 0 address register"] - pub fn m0ar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(12usize)) } - } - #[doc = "stream x memory 1 address register"] - pub fn m1ar(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(16usize)) } - } - #[doc = "stream x FIFO control register"] - pub fn fcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(20usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "stream x number of data register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ndtr(pub u32); - impl Ndtr { - #[doc = "Number of data items to transfer"] - pub const fn ndt(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Number of data items to transfer"] - pub fn set_ndt(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - } - impl Default for Ndtr { - fn default() -> Ndtr { - Ndtr(0) - } - } - #[doc = "stream x FIFO control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Fcr(pub u32); - impl Fcr { - #[doc = "FIFO threshold selection"] - pub const fn fth(&self) -> super::vals::Fth { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Fth(val as u8) - } - #[doc = "FIFO threshold selection"] - pub fn set_fth(&mut self, val: super::vals::Fth) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize); - } - #[doc = "Direct mode disable"] - pub const fn dmdis(&self) -> super::vals::Dmdis { - let val = (self.0 >> 2usize) & 0x01; - super::vals::Dmdis(val as u8) - } - #[doc = "Direct mode disable"] - pub fn set_dmdis(&mut self, val: super::vals::Dmdis) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); - } - #[doc = "FIFO status"] - pub const fn fs(&self) -> super::vals::Fs { - let val = (self.0 >> 3usize) & 0x07; - super::vals::Fs(val as u8) - } - #[doc = "FIFO status"] - pub fn set_fs(&mut self, val: super::vals::Fs) { - self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); - } - #[doc = "FIFO error interrupt enable"] - pub const fn feie(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "FIFO error interrupt enable"] - pub fn set_feie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - } - impl Default for Fcr { - fn default() -> Fcr { - Fcr(0) - } - } - #[doc = "low interrupt flag clear register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ifcr(pub u32); - impl Ifcr { - #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"] - pub fn cfeif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"] - pub fn set_cfeif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"] - pub fn cdmeif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"] - pub fn set_cdmeif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"] - pub fn cteif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"] - pub fn set_cteif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"] - pub fn chtif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"] - pub fn set_chtif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"] - pub fn ctcif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"] - pub fn set_ctcif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Ifcr { - fn default() -> Ifcr { - Ifcr(0) - } - } - #[doc = "stream x configuration register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cr(pub u32); - impl Cr { - #[doc = "Stream enable / flag stream ready when read low"] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Stream enable / flag stream ready when read low"] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Direct mode error interrupt enable"] - pub const fn dmeie(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Direct mode error interrupt enable"] - pub fn set_dmeie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Transfer error interrupt enable"] - pub const fn teie(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Transfer error interrupt enable"] - pub fn set_teie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Half transfer interrupt enable"] - pub const fn htie(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Half transfer interrupt enable"] - pub fn set_htie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Transfer complete interrupt enable"] - pub const fn tcie(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "Transfer complete interrupt enable"] - pub fn set_tcie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Peripheral flow controller"] - pub const fn pfctrl(&self) -> super::vals::Pfctrl { - let val = (self.0 >> 5usize) & 0x01; - super::vals::Pfctrl(val as u8) - } - #[doc = "Peripheral flow controller"] - pub fn set_pfctrl(&mut self, val: super::vals::Pfctrl) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); - } - #[doc = "Data transfer direction"] - pub const fn dir(&self) -> super::vals::Dir { - let val = (self.0 >> 6usize) & 0x03; - super::vals::Dir(val as u8) - } - #[doc = "Data transfer direction"] - pub fn set_dir(&mut self, val: super::vals::Dir) { - self.0 = (self.0 & !(0x03 << 6usize)) | (((val.0 as u32) & 0x03) << 6usize); - } - #[doc = "Circular mode"] - pub const fn circ(&self) -> super::vals::Circ { - let val = (self.0 >> 8usize) & 0x01; - super::vals::Circ(val as u8) - } - #[doc = "Circular mode"] - pub fn set_circ(&mut self, val: super::vals::Circ) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize); - } - #[doc = "Peripheral increment mode"] - pub const fn pinc(&self) -> super::vals::Inc { - let val = (self.0 >> 9usize) & 0x01; - super::vals::Inc(val as u8) - } - #[doc = "Peripheral increment mode"] - pub fn set_pinc(&mut self, val: super::vals::Inc) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); - } - #[doc = "Memory increment mode"] - pub const fn minc(&self) -> super::vals::Inc { - let val = (self.0 >> 10usize) & 0x01; - super::vals::Inc(val as u8) - } - #[doc = "Memory increment mode"] - pub fn set_minc(&mut self, val: super::vals::Inc) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); - } - #[doc = "Peripheral data size"] - pub const fn psize(&self) -> super::vals::Size { - let val = (self.0 >> 11usize) & 0x03; - super::vals::Size(val as u8) - } - #[doc = "Peripheral data size"] - pub fn set_psize(&mut self, val: super::vals::Size) { - self.0 = (self.0 & !(0x03 << 11usize)) | (((val.0 as u32) & 0x03) << 11usize); - } - #[doc = "Memory data size"] - pub const fn msize(&self) -> super::vals::Size { - let val = (self.0 >> 13usize) & 0x03; - super::vals::Size(val as u8) - } - #[doc = "Memory data size"] - pub fn set_msize(&mut self, val: super::vals::Size) { - self.0 = (self.0 & !(0x03 << 13usize)) | (((val.0 as u32) & 0x03) << 13usize); - } - #[doc = "Peripheral increment offset size"] - pub const fn pincos(&self) -> super::vals::Pincos { - let val = (self.0 >> 15usize) & 0x01; - super::vals::Pincos(val as u8) - } - #[doc = "Peripheral increment offset size"] - pub fn set_pincos(&mut self, val: super::vals::Pincos) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); - } - #[doc = "Priority level"] - pub const fn pl(&self) -> super::vals::Pl { - let val = (self.0 >> 16usize) & 0x03; - super::vals::Pl(val as u8) - } - #[doc = "Priority level"] - pub fn set_pl(&mut self, val: super::vals::Pl) { - self.0 = (self.0 & !(0x03 << 16usize)) | (((val.0 as u32) & 0x03) << 16usize); - } - #[doc = "Double buffer mode"] - pub const fn dbm(&self) -> super::vals::Dbm { - let val = (self.0 >> 18usize) & 0x01; - super::vals::Dbm(val as u8) - } - #[doc = "Double buffer mode"] - pub fn set_dbm(&mut self, val: super::vals::Dbm) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize); - } - #[doc = "Current target (only in double buffer mode)"] - pub const fn ct(&self) -> super::vals::Ct { - let val = (self.0 >> 19usize) & 0x01; - super::vals::Ct(val as u8) - } - #[doc = "Current target (only in double buffer mode)"] - pub fn set_ct(&mut self, val: super::vals::Ct) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize); - } - #[doc = "Peripheral burst transfer configuration"] - pub const fn pburst(&self) -> super::vals::Burst { - let val = (self.0 >> 21usize) & 0x03; - super::vals::Burst(val as u8) - } - #[doc = "Peripheral burst transfer configuration"] - pub fn set_pburst(&mut self, val: super::vals::Burst) { - self.0 = (self.0 & !(0x03 << 21usize)) | (((val.0 as u32) & 0x03) << 21usize); - } - #[doc = "Memory burst transfer configuration"] - pub const fn mburst(&self) -> super::vals::Burst { - let val = (self.0 >> 23usize) & 0x03; - super::vals::Burst(val as u8) - } - #[doc = "Memory burst transfer configuration"] - pub fn set_mburst(&mut self, val: super::vals::Burst) { - self.0 = (self.0 & !(0x03 << 23usize)) | (((val.0 as u32) & 0x03) << 23usize); - } - #[doc = "Channel selection"] - pub const fn chsel(&self) -> u8 { - let val = (self.0 >> 25usize) & 0x0f; - val as u8 - } - #[doc = "Channel selection"] - pub fn set_chsel(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 25usize)) | (((val as u32) & 0x0f) << 25usize); - } - } - impl Default for Cr { - fn default() -> Cr { - Cr(0) - } - } - #[doc = "low interrupt status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Isr(pub u32); - impl Isr { - #[doc = "Stream x FIFO error interrupt flag (x=3..0)"] - pub fn feif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x FIFO error interrupt flag (x=3..0)"] - pub fn set_feif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x direct mode error interrupt flag (x=3..0)"] - pub fn dmeif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x direct mode error interrupt flag (x=3..0)"] - pub fn set_dmeif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x transfer error interrupt flag (x=3..0)"] - pub fn teif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x transfer error interrupt flag (x=3..0)"] - pub fn set_teif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x half transfer interrupt flag (x=3..0)"] - pub fn htif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x half transfer interrupt flag (x=3..0)"] - pub fn set_htif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"] - pub fn tcif(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"] - pub fn set_tcif(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Isr { - fn default() -> Isr { - Isr(0) - } - } - } - pub mod vals { - use crate::generic::*; - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dmdis(pub u8); - impl Dmdis { - #[doc = "Direct mode is enabled"] - pub const ENABLED: Self = Self(0); - #[doc = "Direct mode is disabled"] - pub const DISABLED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Size(pub u8); - impl Size { - #[doc = "Byte (8-bit)"] - pub const BITS8: Self = Self(0); - #[doc = "Half-word (16-bit)"] - pub const BITS16: Self = Self(0x01); - #[doc = "Word (32-bit)"] - pub const BITS32: Self = Self(0x02); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Inc(pub u8); - impl Inc { - #[doc = "Address pointer is fixed"] - pub const FIXED: Self = Self(0); - #[doc = "Address pointer is incremented after each data transfer"] - pub const INCREMENTED: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pfctrl(pub u8); - impl Pfctrl { - #[doc = "The DMA is the flow controller"] - pub const DMA: Self = Self(0); - #[doc = "The peripheral is the flow controller"] - pub const PERIPHERAL: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Circ(pub u8); - impl Circ { - #[doc = "Circular mode disabled"] + pub struct Tr(pub u8); + impl Tr { + #[doc = "Falling edge trigger is disabled"] pub const DISABLED: Self = Self(0); - #[doc = "Circular mode enabled"] + #[doc = "Falling edge trigger is enabled"] pub const ENABLED: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Burst(pub u8); - impl Burst { - #[doc = "Single transfer"] - pub const SINGLE: Self = Self(0); - #[doc = "Incremental burst of 4 beats"] - pub const INCR4: Self = Self(0x01); - #[doc = "Incremental burst of 8 beats"] - pub const INCR8: Self = Self(0x02); - #[doc = "Incremental burst of 16 beats"] - pub const INCR16: Self = Self(0x03); + pub struct Prr(pub u8); + impl Prr { + #[doc = "No trigger request occurred"] + pub const NOTPENDING: Self = Self(0); + #[doc = "Selected trigger request occurred"] + pub const PENDING: Self = Self(0x01); } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dir(pub u8); - impl Dir { - #[doc = "Peripheral-to-memory"] - pub const PERIPHERALTOMEMORY: Self = Self(0); - #[doc = "Memory-to-peripheral"] - pub const MEMORYTOPERIPHERAL: Self = Self(0x01); - #[doc = "Memory-to-memory"] - pub const MEMORYTOMEMORY: Self = Self(0x02); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pl(pub u8); - impl Pl { - #[doc = "Low"] - pub const LOW: Self = Self(0); - #[doc = "Medium"] - pub const MEDIUM: Self = Self(0x01); - #[doc = "High"] - pub const HIGH: Self = Self(0x02); - #[doc = "Very high"] - pub const VERYHIGH: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Fs(pub u8); - impl Fs { - #[doc = "0 < fifo_level < 1/4"] - pub const QUARTER1: Self = Self(0); - #[doc = "1/4 <= fifo_level < 1/2"] - pub const QUARTER2: Self = Self(0x01); - #[doc = "1/2 <= fifo_level < 3/4"] - pub const QUARTER3: Self = Self(0x02); - #[doc = "3/4 <= fifo_level < full"] - pub const QUARTER4: Self = Self(0x03); - #[doc = "FIFO is empty"] - pub const EMPTY: Self = Self(0x04); - #[doc = "FIFO is full"] - pub const FULL: Self = Self(0x05); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Fth(pub u8); - impl Fth { - #[doc = "1/4 full FIFO"] - pub const QUARTER: Self = Self(0); - #[doc = "1/2 full FIFO"] - pub const HALF: Self = Self(0x01); - #[doc = "3/4 full FIFO"] - pub const THREEQUARTERS: Self = Self(0x02); - #[doc = "Full FIFO"] - pub const FULL: Self = Self(0x03); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Pincos(pub u8); - impl Pincos { - #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] - pub const PSIZE: Self = Self(0); - #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] - pub const FIXED4: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Ct(pub u8); - impl Ct { - #[doc = "The current target memory is Memory 0"] - pub const MEMORY0: Self = Self(0); - #[doc = "The current target memory is Memory 1"] - pub const MEMORY1: Self = Self(0x01); - } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Dbm(pub u8); - impl Dbm { - #[doc = "No buffer switching at the end of transfer"] - pub const DISABLED: Self = Self(0); - #[doc = "Memory target switched at the end of the DMA transfer"] - pub const ENABLED: Self = Self(0x01); - } - } -} -pub mod syscfg_h7 { - use crate::generic::*; - #[doc = "System configuration controller"] - #[derive(Copy, Clone)] - pub struct Syscfg(pub *mut u8); - unsafe impl Send for Syscfg {} - unsafe impl Sync for Syscfg {} - impl Syscfg { - #[doc = "peripheral mode configuration register"] - pub fn pmcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(4usize)) } - } - #[doc = "external interrupt configuration register 1"] - pub fn exticr(self, n: usize) -> Reg { - assert!(n < 4usize); - unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } - } - #[doc = "compensation cell control/status register"] - pub fn cccsr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(32usize)) } - } - #[doc = "SYSCFG compensation cell value register"] - pub fn ccvr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(36usize)) } - } - #[doc = "SYSCFG compensation cell code register"] - pub fn cccr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(40usize)) } - } - #[doc = "SYSCFG power control register"] - pub fn pwrcr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(44usize)) } - } - #[doc = "SYSCFG package register"] - pub fn pkgr(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(292usize)) } - } - #[doc = "SYSCFG user register 0"] - pub fn ur0(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(768usize)) } - } - #[doc = "SYSCFG user register 2"] - pub fn ur2(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(776usize)) } - } - #[doc = "SYSCFG user register 3"] - pub fn ur3(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(780usize)) } - } - #[doc = "SYSCFG user register 4"] - pub fn ur4(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(784usize)) } - } - #[doc = "SYSCFG user register 5"] - pub fn ur5(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(788usize)) } - } - #[doc = "SYSCFG user register 6"] - pub fn ur6(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(792usize)) } - } - #[doc = "SYSCFG user register 7"] - pub fn ur7(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(796usize)) } - } - #[doc = "SYSCFG user register 8"] - pub fn ur8(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(800usize)) } - } - #[doc = "SYSCFG user register 9"] - pub fn ur9(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(804usize)) } - } - #[doc = "SYSCFG user register 10"] - pub fn ur10(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(808usize)) } - } - #[doc = "SYSCFG user register 11"] - pub fn ur11(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(812usize)) } - } - #[doc = "SYSCFG user register 12"] - pub fn ur12(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(816usize)) } - } - #[doc = "SYSCFG user register 13"] - pub fn ur13(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(820usize)) } - } - #[doc = "SYSCFG user register 14"] - pub fn ur14(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(824usize)) } - } - #[doc = "SYSCFG user register 15"] - pub fn ur15(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(828usize)) } - } - #[doc = "SYSCFG user register 16"] - pub fn ur16(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(832usize)) } - } - #[doc = "SYSCFG user register 17"] - pub fn ur17(self) -> Reg { - unsafe { Reg::from_ptr(self.0.add(836usize)) } - } - } - pub mod regs { - use crate::generic::*; - #[doc = "SYSCFG user register 16"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur16(pub u32); - impl Ur16 { - #[doc = "Freeze independent watchdog in Stop mode"] - pub const fn fziwdgstp(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Freeze independent watchdog in Stop mode"] - pub fn set_fziwdgstp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Private key programmed"] - pub const fn pkp(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Private key programmed"] - pub fn set_pkp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur16 { - fn default() -> Ur16 { - Ur16(0) - } - } - #[doc = "SYSCFG user register 0"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur0(pub u32); - impl Ur0 { - #[doc = "Bank Swap"] - pub const fn bks(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Bank Swap"] - pub fn set_bks(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Readout protection"] - pub const fn rdp(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Readout protection"] - pub fn set_rdp(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } - } - impl Default for Ur0 { - fn default() -> Ur0 { - Ur0(0) - } - } - #[doc = "SYSCFG compensation cell value register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ccvr(pub u32); - impl Ccvr { - #[doc = "NMOS compensation value"] - pub const fn ncv(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "NMOS compensation value"] - pub fn set_ncv(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "PMOS compensation value"] - pub const fn pcv(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 - } - #[doc = "PMOS compensation value"] - pub fn set_pcv(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); - } - } - impl Default for Ccvr { - fn default() -> Ccvr { - Ccvr(0) - } - } - #[doc = "SYSCFG user register 7"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur7(pub u32); - impl Ur7 { - #[doc = "Secured area start address for bank 1"] - pub const fn sa_beg_1(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Secured area start address for bank 1"] - pub fn set_sa_beg_1(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Secured area end address for bank 1"] - pub const fn sa_end_1(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x0fff; - val as u16 - } - #[doc = "Secured area end address for bank 1"] - pub fn set_sa_end_1(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); - } - } - impl Default for Ur7 { - fn default() -> Ur7 { - Ur7(0) - } - } - #[doc = "SYSCFG user register 13"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur13(pub u32); - impl Ur13 { - #[doc = "Secured DTCM RAM Size"] - pub const fn sdrs(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x03; - val as u8 - } - #[doc = "Secured DTCM RAM Size"] - pub fn set_sdrs(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); - } - #[doc = "D1 Standby reset"] - pub const fn d1sbrst(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "D1 Standby reset"] - pub fn set_d1sbrst(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur13 { - fn default() -> Ur13 { - Ur13(0) - } - } - #[doc = "SYSCFG user register 4"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur4(pub u32); - impl Ur4 { - #[doc = "Mass Erase Protected Area Disabled for bank 1"] - pub const fn mepad_1(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Mass Erase Protected Area Disabled for bank 1"] - pub fn set_mepad_1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur4 { - fn default() -> Ur4 { - Ur4(0) - } - } - #[doc = "SYSCFG user register 10"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur10(pub u32); - impl Ur10 { - #[doc = "Protected area end address for bank 2"] - pub const fn pa_end_2(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Protected area end address for bank 2"] - pub fn set_pa_end_2(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Secured area start address for bank 2"] - pub const fn sa_beg_2(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x0fff; - val as u16 - } - #[doc = "Secured area start address for bank 2"] - pub fn set_sa_beg_2(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); - } - } - impl Default for Ur10 { - fn default() -> Ur10 { - Ur10(0) - } - } - #[doc = "SYSCFG user register 9"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur9(pub u32); - impl Ur9 { - #[doc = "Write protection for flash bank 2"] - pub const fn wrpn_2(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Write protection for flash bank 2"] - pub fn set_wrpn_2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - #[doc = "Protected area start address for bank 2"] - pub const fn pa_beg_2(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x0fff; - val as u16 - } - #[doc = "Protected area start address for bank 2"] - pub fn set_pa_beg_2(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); - } - } - impl Default for Ur9 { - fn default() -> Ur9 { - Ur9(0) - } - } - #[doc = "SYSCFG user register 12"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur12(pub u32); - impl Ur12 { - #[doc = "Secure mode"] - pub const fn secure(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Secure mode"] - pub fn set_secure(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur12 { - fn default() -> Ur12 { - Ur12(0) - } - } - #[doc = "peripheral mode configuration register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pmcr(pub u32); - impl Pmcr { - #[doc = "I2C1 Fm+"] - pub const fn i2c1fmp(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "I2C1 Fm+"] - pub fn set_i2c1fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "I2C2 Fm+"] - pub const fn i2c2fmp(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "I2C2 Fm+"] - pub fn set_i2c2fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "I2C3 Fm+"] - pub const fn i2c3fmp(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "I2C3 Fm+"] - pub fn set_i2c3fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "I2C4 Fm+"] - pub const fn i2c4fmp(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "I2C4 Fm+"] - pub fn set_i2c4fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "PB(6) Fm+"] - pub const fn pb6fmp(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "PB(6) Fm+"] - pub fn set_pb6fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "PB(7) Fast Mode Plus"] - pub const fn pb7fmp(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "PB(7) Fast Mode Plus"] - pub fn set_pb7fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "PB(8) Fast Mode Plus"] - pub const fn pb8fmp(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "PB(8) Fast Mode Plus"] - pub fn set_pb8fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "PB(9) Fm+"] - pub const fn pb9fmp(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "PB(9) Fm+"] - pub fn set_pb9fmp(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); - } - #[doc = "Booster Enable"] - pub const fn booste(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Booster Enable"] - pub fn set_booste(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "Analog switch supply voltage selection"] - pub const fn boostvddsel(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 - } - #[doc = "Analog switch supply voltage selection"] - pub fn set_boostvddsel(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); - } - #[doc = "Ethernet PHY Interface Selection"] - pub const fn epis(&self) -> u8 { - let val = (self.0 >> 21usize) & 0x07; - val as u8 - } - #[doc = "Ethernet PHY Interface Selection"] - pub fn set_epis(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 21usize)) | (((val as u32) & 0x07) << 21usize); - } - #[doc = "PA0 Switch Open"] - pub const fn pa0so(&self) -> bool { - let val = (self.0 >> 24usize) & 0x01; - val != 0 - } - #[doc = "PA0 Switch Open"] - pub fn set_pa0so(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); - } - #[doc = "PA1 Switch Open"] - pub const fn pa1so(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 - } - #[doc = "PA1 Switch Open"] - pub fn set_pa1so(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); - } - #[doc = "PC2 Switch Open"] - pub const fn pc2so(&self) -> bool { - let val = (self.0 >> 26usize) & 0x01; - val != 0 - } - #[doc = "PC2 Switch Open"] - pub fn set_pc2so(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); - } - #[doc = "PC3 Switch Open"] - pub const fn pc3so(&self) -> bool { - let val = (self.0 >> 27usize) & 0x01; - val != 0 - } - #[doc = "PC3 Switch Open"] - pub fn set_pc3so(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); - } - } - impl Default for Pmcr { - fn default() -> Pmcr { - Pmcr(0) - } - } - #[doc = "SYSCFG user register 6"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur6(pub u32); - impl Ur6 { - #[doc = "Protected area start address for bank 1"] - pub const fn pa_beg_1(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Protected area start address for bank 1"] - pub fn set_pa_beg_1(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Protected area end address for bank 1"] - pub const fn pa_end_1(&self) -> u16 { - let val = (self.0 >> 16usize) & 0x0fff; - val as u16 - } - #[doc = "Protected area end address for bank 1"] - pub fn set_pa_end_1(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); - } - } - impl Default for Ur6 { - fn default() -> Ur6 { - Ur6(0) - } - } - #[doc = "compensation cell control/status register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cccsr(pub u32); - impl Cccsr { - #[doc = "enable"] - pub const fn en(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "enable"] - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Code selection"] - pub const fn cs(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Code selection"] - pub fn set_cs(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Compensation cell ready flag"] - pub const fn ready(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 - } - #[doc = "Compensation cell ready flag"] - pub fn set_ready(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); - } - #[doc = "High-speed at low-voltage"] - pub const fn hslv(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "High-speed at low-voltage"] - pub fn set_hslv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Cccsr { - fn default() -> Cccsr { - Cccsr(0) - } - } - #[doc = "SYSCFG user register 5"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur5(pub u32); - impl Ur5 { - #[doc = "Mass erase secured area disabled for bank 1"] - pub const fn mesad_1(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Mass erase secured area disabled for bank 1"] - pub fn set_mesad_1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Write protection for flash bank 1"] - pub const fn wrpn_1(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Write protection for flash bank 1"] - pub fn set_wrpn_1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } - } - impl Default for Ur5 { - fn default() -> Ur5 { - Ur5(0) - } - } - #[doc = "SYSCFG user register 14"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur14(pub u32); - impl Ur14 { - #[doc = "D1 Stop Reset"] - pub const fn d1stprst(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "D1 Stop Reset"] - pub fn set_d1stprst(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for Ur14 { - fn default() -> Ur14 { - Ur14(0) - } - } - #[doc = "SYSCFG power control register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pwrcr(pub u32); - impl Pwrcr { - #[doc = "Overdrive enable"] - pub const fn oden(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Overdrive enable"] - pub fn set_oden(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - } - impl Default for Pwrcr { - fn default() -> Pwrcr { - Pwrcr(0) - } - } - #[doc = "SYSCFG package register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Pkgr(pub u32); - impl Pkgr { - #[doc = "Package"] - pub const fn pkg(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Package"] - pub fn set_pkg(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - } - impl Default for Pkgr { - fn default() -> Pkgr { - Pkgr(0) - } - } - #[doc = "SYSCFG user register 3"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur3(pub u32); - impl Ur3 { - #[doc = "Boot Address 1"] - pub const fn boot_add1(&self) -> u16 { - let val = (self.0 >> 16usize) & 0xffff; - val as u16 - } - #[doc = "Boot Address 1"] - pub fn set_boot_add1(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); - } - } - impl Default for Ur3 { - fn default() -> Ur3 { - Ur3(0) - } - } - #[doc = "SYSCFG user register 11"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur11(pub u32); - impl Ur11 { - #[doc = "Secured area end address for bank 2"] - pub const fn sa_end_2(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x0fff; - val as u16 - } - #[doc = "Secured area end address for bank 2"] - pub fn set_sa_end_2(&mut self, val: u16) { - self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); - } - #[doc = "Independent Watchdog 1 mode"] - pub const fn iwdg1m(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Independent Watchdog 1 mode"] - pub fn set_iwdg1m(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur11 { - fn default() -> Ur11 { - Ur11(0) - } - } - #[doc = "SYSCFG compensation cell code register"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cccr(pub u32); - impl Cccr { - #[doc = "NMOS compensation code"] - pub const fn ncc(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "NMOS compensation code"] - pub fn set_ncc(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "PMOS compensation code"] - pub const fn pcc(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 - } - #[doc = "PMOS compensation code"] - pub fn set_pcc(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); - } - } - impl Default for Cccr { - fn default() -> Cccr { - Cccr(0) - } - } - #[doc = "SYSCFG user register 15"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur15(pub u32); - impl Ur15 { - #[doc = "Freeze independent watchdog in Standby mode"] - pub const fn fziwdgstb(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Freeze independent watchdog in Standby mode"] - pub fn set_fziwdgstb(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur15 { - fn default() -> Ur15 { - Ur15(0) - } - } - #[doc = "SYSCFG user register 8"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur8(pub u32); - impl Ur8 { - #[doc = "Mass erase protected area disabled for bank 2"] - pub const fn mepad_2(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Mass erase protected area disabled for bank 2"] - pub fn set_mepad_2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Mass erase secured area disabled for bank 2"] - pub const fn mesad_2(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "Mass erase secured area disabled for bank 2"] - pub fn set_mesad_2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } - } - impl Default for Ur8 { - fn default() -> Ur8 { - Ur8(0) - } - } - #[doc = "external interrupt configuration register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Exticr(pub u32); - impl Exticr { - #[doc = "EXTI x configuration (x = 4 to 7)"] - pub fn exti(&self, n: usize) -> u8 { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x0f; - val as u8 - } - #[doc = "EXTI x configuration (x = 4 to 7)"] - pub fn set_exti(&mut self, n: usize, val: u8) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); - } - } - impl Default for Exticr { - fn default() -> Exticr { - Exticr(0) - } - } - #[doc = "SYSCFG user register 2"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur2(pub u32); - impl Ur2 { - #[doc = "BOR_LVL Brownout Reset Threshold Level"] - pub const fn borh(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x03; - val as u8 - } - #[doc = "BOR_LVL Brownout Reset Threshold Level"] - pub fn set_borh(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); - } - #[doc = "Boot Address 0"] - pub const fn boot_add0(&self) -> u16 { - let val = (self.0 >> 16usize) & 0xffff; - val as u16 - } - #[doc = "Boot Address 0"] - pub fn set_boot_add0(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); - } - } - impl Default for Ur2 { - fn default() -> Ur2 { - Ur2(0) - } - } - #[doc = "SYSCFG user register 17"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ur17(pub u32); - impl Ur17 { - #[doc = "I/O high speed / low voltage"] - pub const fn io_hslv(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "I/O high speed / low voltage"] - pub fn set_io_hslv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for Ur17 { - fn default() -> Ur17 { - Ur17(0) - } + pub struct Mr(pub u8); + impl Mr { + #[doc = "Interrupt request line is masked"] + pub const MASKED: Self = Self(0); + #[doc = "Interrupt request line is unmasked"] + pub const UNMASKED: Self = Self(0x01); } } } diff --git a/embassy-stm32/src/pac/stm32f401cb.rs b/embassy-stm32/src/pac/stm32f401cb.rs index 13e60e2e..34fa05d8 100644 --- a/embassy-stm32/src/pac/stm32f401cb.rs +++ b/embassy-stm32/src/pac/stm32f401cb.rs @@ -128,30 +128,30 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f401cc.rs b/embassy-stm32/src/pac/stm32f401cc.rs index 13e60e2e..34fa05d8 100644 --- a/embassy-stm32/src/pac/stm32f401cc.rs +++ b/embassy-stm32/src/pac/stm32f401cc.rs @@ -128,30 +128,30 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f401cd.rs b/embassy-stm32/src/pac/stm32f401cd.rs index 13e60e2e..34fa05d8 100644 --- a/embassy-stm32/src/pac/stm32f401cd.rs +++ b/embassy-stm32/src/pac/stm32f401cd.rs @@ -128,30 +128,30 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f401ce.rs b/embassy-stm32/src/pac/stm32f401ce.rs index 13e60e2e..34fa05d8 100644 --- a/embassy-stm32/src/pac/stm32f401ce.rs +++ b/embassy-stm32/src/pac/stm32f401ce.rs @@ -128,30 +128,30 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f401rb.rs b/embassy-stm32/src/pac/stm32f401rb.rs index 13e60e2e..34fa05d8 100644 --- a/embassy-stm32/src/pac/stm32f401rb.rs +++ b/embassy-stm32/src/pac/stm32f401rb.rs @@ -128,30 +128,30 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f401rc.rs b/embassy-stm32/src/pac/stm32f401rc.rs index 13e60e2e..34fa05d8 100644 --- a/embassy-stm32/src/pac/stm32f401rc.rs +++ b/embassy-stm32/src/pac/stm32f401rc.rs @@ -128,30 +128,30 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f401rd.rs b/embassy-stm32/src/pac/stm32f401rd.rs index 13e60e2e..34fa05d8 100644 --- a/embassy-stm32/src/pac/stm32f401rd.rs +++ b/embassy-stm32/src/pac/stm32f401rd.rs @@ -128,30 +128,30 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f401re.rs b/embassy-stm32/src/pac/stm32f401re.rs index 13e60e2e..34fa05d8 100644 --- a/embassy-stm32/src/pac/stm32f401re.rs +++ b/embassy-stm32/src/pac/stm32f401re.rs @@ -128,30 +128,30 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f401vb.rs b/embassy-stm32/src/pac/stm32f401vb.rs index 91263ba4..cc0e9bd8 100644 --- a/embassy-stm32/src/pac/stm32f401vb.rs +++ b/embassy-stm32/src/pac/stm32f401vb.rs @@ -128,38 +128,38 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f401vc.rs b/embassy-stm32/src/pac/stm32f401vc.rs index 91263ba4..cc0e9bd8 100644 --- a/embassy-stm32/src/pac/stm32f401vc.rs +++ b/embassy-stm32/src/pac/stm32f401vc.rs @@ -128,38 +128,38 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f401vd.rs b/embassy-stm32/src/pac/stm32f401vd.rs index 91263ba4..cc0e9bd8 100644 --- a/embassy-stm32/src/pac/stm32f401vd.rs +++ b/embassy-stm32/src/pac/stm32f401vd.rs @@ -128,38 +128,38 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f401ve.rs b/embassy-stm32/src/pac/stm32f401ve.rs index 91263ba4..cc0e9bd8 100644 --- a/embassy-stm32/src/pac/stm32f401ve.rs +++ b/embassy-stm32/src/pac/stm32f401ve.rs @@ -128,38 +128,38 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f405oe.rs b/embassy-stm32/src/pac/stm32f405oe.rs index f8ee073f..60eadd64 100644 --- a/embassy-stm32/src/pac/stm32f405oe.rs +++ b/embassy-stm32/src/pac/stm32f405oe.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f405og.rs b/embassy-stm32/src/pac/stm32f405og.rs index f8ee073f..60eadd64 100644 --- a/embassy-stm32/src/pac/stm32f405og.rs +++ b/embassy-stm32/src/pac/stm32f405og.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f405rg.rs b/embassy-stm32/src/pac/stm32f405rg.rs index f8ee073f..60eadd64 100644 --- a/embassy-stm32/src/pac/stm32f405rg.rs +++ b/embassy-stm32/src/pac/stm32f405rg.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f405vg.rs b/embassy-stm32/src/pac/stm32f405vg.rs index f8ee073f..60eadd64 100644 --- a/embassy-stm32/src/pac/stm32f405vg.rs +++ b/embassy-stm32/src/pac/stm32f405vg.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f405zg.rs b/embassy-stm32/src/pac/stm32f405zg.rs index f8ee073f..60eadd64 100644 --- a/embassy-stm32/src/pac/stm32f405zg.rs +++ b/embassy-stm32/src/pac/stm32f405zg.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f407ie.rs b/embassy-stm32/src/pac/stm32f407ie.rs index 7c839139..b02ca8d3 100644 --- a/embassy-stm32/src/pac/stm32f407ie.rs +++ b/embassy-stm32/src/pac/stm32f407ie.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f407ig.rs b/embassy-stm32/src/pac/stm32f407ig.rs index 7c839139..b02ca8d3 100644 --- a/embassy-stm32/src/pac/stm32f407ig.rs +++ b/embassy-stm32/src/pac/stm32f407ig.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f407ve.rs b/embassy-stm32/src/pac/stm32f407ve.rs index 7c839139..b02ca8d3 100644 --- a/embassy-stm32/src/pac/stm32f407ve.rs +++ b/embassy-stm32/src/pac/stm32f407ve.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f407vg.rs b/embassy-stm32/src/pac/stm32f407vg.rs index 7c839139..b02ca8d3 100644 --- a/embassy-stm32/src/pac/stm32f407vg.rs +++ b/embassy-stm32/src/pac/stm32f407vg.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f407ze.rs b/embassy-stm32/src/pac/stm32f407ze.rs index 7c839139..b02ca8d3 100644 --- a/embassy-stm32/src/pac/stm32f407ze.rs +++ b/embassy-stm32/src/pac/stm32f407ze.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f407zg.rs b/embassy-stm32/src/pac/stm32f407zg.rs index 7c839139..b02ca8d3 100644 --- a/embassy-stm32/src/pac/stm32f407zg.rs +++ b/embassy-stm32/src/pac/stm32f407zg.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f411cc.rs b/embassy-stm32/src/pac/stm32f411cc.rs index 325aee85..2f3f0f0b 100644 --- a/embassy-stm32/src/pac/stm32f411cc.rs +++ b/embassy-stm32/src/pac/stm32f411cc.rs @@ -128,55 +128,55 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f411ce.rs b/embassy-stm32/src/pac/stm32f411ce.rs index 325aee85..2f3f0f0b 100644 --- a/embassy-stm32/src/pac/stm32f411ce.rs +++ b/embassy-stm32/src/pac/stm32f411ce.rs @@ -128,55 +128,55 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f411rc.rs b/embassy-stm32/src/pac/stm32f411rc.rs index 325aee85..2f3f0f0b 100644 --- a/embassy-stm32/src/pac/stm32f411rc.rs +++ b/embassy-stm32/src/pac/stm32f411rc.rs @@ -128,55 +128,55 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f411re.rs b/embassy-stm32/src/pac/stm32f411re.rs index 325aee85..2f3f0f0b 100644 --- a/embassy-stm32/src/pac/stm32f411re.rs +++ b/embassy-stm32/src/pac/stm32f411re.rs @@ -128,55 +128,55 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f411vc.rs b/embassy-stm32/src/pac/stm32f411vc.rs index 325aee85..2f3f0f0b 100644 --- a/embassy-stm32/src/pac/stm32f411vc.rs +++ b/embassy-stm32/src/pac/stm32f411vc.rs @@ -128,55 +128,55 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f411ve.rs b/embassy-stm32/src/pac/stm32f411ve.rs index 325aee85..2f3f0f0b 100644 --- a/embassy-stm32/src/pac/stm32f411ve.rs +++ b/embassy-stm32/src/pac/stm32f411ve.rs @@ -128,55 +128,55 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f412ce.rs b/embassy-stm32/src/pac/stm32f412ce.rs index ae976e69..f3e125b7 100644 --- a/embassy-stm32/src/pac/stm32f412ce.rs +++ b/embassy-stm32/src/pac/stm32f412ce.rs @@ -96,41 +96,41 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f412cg.rs b/embassy-stm32/src/pac/stm32f412cg.rs index ae976e69..f3e125b7 100644 --- a/embassy-stm32/src/pac/stm32f412cg.rs +++ b/embassy-stm32/src/pac/stm32f412cg.rs @@ -96,41 +96,41 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f412re.rs b/embassy-stm32/src/pac/stm32f412re.rs index 819f0c06..c390cb26 100644 --- a/embassy-stm32/src/pac/stm32f412re.rs +++ b/embassy-stm32/src/pac/stm32f412re.rs @@ -113,43 +113,43 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f412rg.rs b/embassy-stm32/src/pac/stm32f412rg.rs index 819f0c06..c390cb26 100644 --- a/embassy-stm32/src/pac/stm32f412rg.rs +++ b/embassy-stm32/src/pac/stm32f412rg.rs @@ -113,43 +113,43 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f412ve.rs b/embassy-stm32/src/pac/stm32f412ve.rs index 9e109b61..e951dcd0 100644 --- a/embassy-stm32/src/pac/stm32f412ve.rs +++ b/embassy-stm32/src/pac/stm32f412ve.rs @@ -164,55 +164,55 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f412vg.rs b/embassy-stm32/src/pac/stm32f412vg.rs index 9e109b61..e951dcd0 100644 --- a/embassy-stm32/src/pac/stm32f412vg.rs +++ b/embassy-stm32/src/pac/stm32f412vg.rs @@ -164,55 +164,55 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f412ze.rs b/embassy-stm32/src/pac/stm32f412ze.rs index 9e109b61..e951dcd0 100644 --- a/embassy-stm32/src/pac/stm32f412ze.rs +++ b/embassy-stm32/src/pac/stm32f412ze.rs @@ -164,55 +164,55 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f412zg.rs b/embassy-stm32/src/pac/stm32f412zg.rs index 9e109b61..e951dcd0 100644 --- a/embassy-stm32/src/pac/stm32f412zg.rs +++ b/embassy-stm32/src/pac/stm32f412zg.rs @@ -164,55 +164,55 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f413cg.rs b/embassy-stm32/src/pac/stm32f413cg.rs index f74b0f40..d826ffc9 100644 --- a/embassy-stm32/src/pac/stm32f413cg.rs +++ b/embassy-stm32/src/pac/stm32f413cg.rs @@ -164,58 +164,58 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Mosi, PA10, 5); -impl_spi_pin!(SPI2, Miso, PA12, 5); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f413ch.rs b/embassy-stm32/src/pac/stm32f413ch.rs index f74b0f40..d826ffc9 100644 --- a/embassy-stm32/src/pac/stm32f413ch.rs +++ b/embassy-stm32/src/pac/stm32f413ch.rs @@ -164,58 +164,58 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Mosi, PA10, 5); -impl_spi_pin!(SPI2, Miso, PA12, 5); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f413mg.rs b/embassy-stm32/src/pac/stm32f413mg.rs index f2cd2b65..7064cf6d 100644 --- a/embassy-stm32/src/pac/stm32f413mg.rs +++ b/embassy-stm32/src/pac/stm32f413mg.rs @@ -164,58 +164,58 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Mosi, PA10, 5); -impl_spi_pin!(SPI2, Miso, PA12, 5); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f413mh.rs b/embassy-stm32/src/pac/stm32f413mh.rs index f2cd2b65..7064cf6d 100644 --- a/embassy-stm32/src/pac/stm32f413mh.rs +++ b/embassy-stm32/src/pac/stm32f413mh.rs @@ -164,58 +164,58 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Mosi, PA10, 5); -impl_spi_pin!(SPI2, Miso, PA12, 5); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f413rg.rs b/embassy-stm32/src/pac/stm32f413rg.rs index f2cd2b65..7064cf6d 100644 --- a/embassy-stm32/src/pac/stm32f413rg.rs +++ b/embassy-stm32/src/pac/stm32f413rg.rs @@ -164,58 +164,58 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Mosi, PA10, 5); -impl_spi_pin!(SPI2, Miso, PA12, 5); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f413rh.rs b/embassy-stm32/src/pac/stm32f413rh.rs index f2cd2b65..7064cf6d 100644 --- a/embassy-stm32/src/pac/stm32f413rh.rs +++ b/embassy-stm32/src/pac/stm32f413rh.rs @@ -164,58 +164,58 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Mosi, PA10, 5); -impl_spi_pin!(SPI2, Miso, PA12, 5); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f413vg.rs b/embassy-stm32/src/pac/stm32f413vg.rs index f2cd2b65..7064cf6d 100644 --- a/embassy-stm32/src/pac/stm32f413vg.rs +++ b/embassy-stm32/src/pac/stm32f413vg.rs @@ -164,58 +164,58 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Mosi, PA10, 5); -impl_spi_pin!(SPI2, Miso, PA12, 5); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f413vh.rs b/embassy-stm32/src/pac/stm32f413vh.rs index f2cd2b65..7064cf6d 100644 --- a/embassy-stm32/src/pac/stm32f413vh.rs +++ b/embassy-stm32/src/pac/stm32f413vh.rs @@ -164,58 +164,58 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Mosi, PA10, 5); -impl_spi_pin!(SPI2, Miso, PA12, 5); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f413zg.rs b/embassy-stm32/src/pac/stm32f413zg.rs index f2cd2b65..7064cf6d 100644 --- a/embassy-stm32/src/pac/stm32f413zg.rs +++ b/embassy-stm32/src/pac/stm32f413zg.rs @@ -164,58 +164,58 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Mosi, PA10, 5); -impl_spi_pin!(SPI2, Miso, PA12, 5); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f413zh.rs b/embassy-stm32/src/pac/stm32f413zh.rs index f2cd2b65..7064cf6d 100644 --- a/embassy-stm32/src/pac/stm32f413zh.rs +++ b/embassy-stm32/src/pac/stm32f413zh.rs @@ -164,58 +164,58 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Mosi, PA10, 5); -impl_spi_pin!(SPI2, Miso, PA12, 5); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f415og.rs b/embassy-stm32/src/pac/stm32f415og.rs index 490a8c54..212f6bef 100644 --- a/embassy-stm32/src/pac/stm32f415og.rs +++ b/embassy-stm32/src/pac/stm32f415og.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f415rg.rs b/embassy-stm32/src/pac/stm32f415rg.rs index 490a8c54..212f6bef 100644 --- a/embassy-stm32/src/pac/stm32f415rg.rs +++ b/embassy-stm32/src/pac/stm32f415rg.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f415vg.rs b/embassy-stm32/src/pac/stm32f415vg.rs index 490a8c54..212f6bef 100644 --- a/embassy-stm32/src/pac/stm32f415vg.rs +++ b/embassy-stm32/src/pac/stm32f415vg.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f415zg.rs b/embassy-stm32/src/pac/stm32f415zg.rs index 490a8c54..212f6bef 100644 --- a/embassy-stm32/src/pac/stm32f415zg.rs +++ b/embassy-stm32/src/pac/stm32f415zg.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f417ie.rs b/embassy-stm32/src/pac/stm32f417ie.rs index 04a3e952..4cdc36b6 100644 --- a/embassy-stm32/src/pac/stm32f417ie.rs +++ b/embassy-stm32/src/pac/stm32f417ie.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f417ig.rs b/embassy-stm32/src/pac/stm32f417ig.rs index 04a3e952..4cdc36b6 100644 --- a/embassy-stm32/src/pac/stm32f417ig.rs +++ b/embassy-stm32/src/pac/stm32f417ig.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f417ve.rs b/embassy-stm32/src/pac/stm32f417ve.rs index 04a3e952..4cdc36b6 100644 --- a/embassy-stm32/src/pac/stm32f417ve.rs +++ b/embassy-stm32/src/pac/stm32f417ve.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f417vg.rs b/embassy-stm32/src/pac/stm32f417vg.rs index 04a3e952..4cdc36b6 100644 --- a/embassy-stm32/src/pac/stm32f417vg.rs +++ b/embassy-stm32/src/pac/stm32f417vg.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f417ze.rs b/embassy-stm32/src/pac/stm32f417ze.rs index 04a3e952..4cdc36b6 100644 --- a/embassy-stm32/src/pac/stm32f417ze.rs +++ b/embassy-stm32/src/pac/stm32f417ze.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f417zg.rs b/embassy-stm32/src/pac/stm32f417zg.rs index 04a3e952..4cdc36b6 100644 --- a/embassy-stm32/src/pac/stm32f417zg.rs +++ b/embassy-stm32/src/pac/stm32f417zg.rs @@ -181,31 +181,31 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f423ch.rs b/embassy-stm32/src/pac/stm32f423ch.rs index 239676a6..5ba7b6eb 100644 --- a/embassy-stm32/src/pac/stm32f423ch.rs +++ b/embassy-stm32/src/pac/stm32f423ch.rs @@ -164,58 +164,58 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Mosi, PA10, 5); -impl_spi_pin!(SPI2, Miso, PA12, 5); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f423mh.rs b/embassy-stm32/src/pac/stm32f423mh.rs index 0708def5..5f6f0fee 100644 --- a/embassy-stm32/src/pac/stm32f423mh.rs +++ b/embassy-stm32/src/pac/stm32f423mh.rs @@ -164,58 +164,58 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Mosi, PA10, 5); -impl_spi_pin!(SPI2, Miso, PA12, 5); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f423rh.rs b/embassy-stm32/src/pac/stm32f423rh.rs index 0708def5..5f6f0fee 100644 --- a/embassy-stm32/src/pac/stm32f423rh.rs +++ b/embassy-stm32/src/pac/stm32f423rh.rs @@ -164,58 +164,58 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Mosi, PA10, 5); -impl_spi_pin!(SPI2, Miso, PA12, 5); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f423vh.rs b/embassy-stm32/src/pac/stm32f423vh.rs index 0708def5..5f6f0fee 100644 --- a/embassy-stm32/src/pac/stm32f423vh.rs +++ b/embassy-stm32/src/pac/stm32f423vh.rs @@ -164,58 +164,58 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Mosi, PA10, 5); -impl_spi_pin!(SPI2, Miso, PA12, 5); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f423zh.rs b/embassy-stm32/src/pac/stm32f423zh.rs index 0708def5..5f6f0fee 100644 --- a/embassy-stm32/src/pac/stm32f423zh.rs +++ b/embassy-stm32/src/pac/stm32f423zh.rs @@ -164,58 +164,58 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Mosi, PA10, 5); -impl_spi_pin!(SPI2, Miso, PA12, 5); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB12, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Mosi, PA1, 5); -impl_spi_pin!(SPI4, Miso, PA11, 6); -impl_spi_pin!(SPI4, Sck, PB13, 6); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PA10, 6); -impl_spi_pin!(SPI5, Miso, PA12, 6); -impl_spi_pin!(SPI5, Sck, PB0, 6); -impl_spi_pin!(SPI5, Mosi, PB8, 6); -impl_spi_pin!(SPI5, Sck, PE12, 6); -impl_spi_pin!(SPI5, Miso, PE13, 6); -impl_spi_pin!(SPI5, Mosi, PE14, 6); -impl_spi_pin!(SPI5, Sck, PE2, 6); -impl_spi_pin!(SPI5, Miso, PE5, 6); -impl_spi_pin!(SPI5, Mosi, PE6, 6); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f427ag.rs b/embassy-stm32/src/pac/stm32f427ag.rs index bd166eb9..482d0553 100644 --- a/embassy-stm32/src/pac/stm32f427ag.rs +++ b/embassy-stm32/src/pac/stm32f427ag.rs @@ -215,49 +215,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f427ai.rs b/embassy-stm32/src/pac/stm32f427ai.rs index bd166eb9..482d0553 100644 --- a/embassy-stm32/src/pac/stm32f427ai.rs +++ b/embassy-stm32/src/pac/stm32f427ai.rs @@ -215,49 +215,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f427ig.rs b/embassy-stm32/src/pac/stm32f427ig.rs index 6d811e91..264fb175 100644 --- a/embassy-stm32/src/pac/stm32f427ig.rs +++ b/embassy-stm32/src/pac/stm32f427ig.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f427ii.rs b/embassy-stm32/src/pac/stm32f427ii.rs index 6d811e91..264fb175 100644 --- a/embassy-stm32/src/pac/stm32f427ii.rs +++ b/embassy-stm32/src/pac/stm32f427ii.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f427vg.rs b/embassy-stm32/src/pac/stm32f427vg.rs index a3481b09..91b33ba5 100644 --- a/embassy-stm32/src/pac/stm32f427vg.rs +++ b/embassy-stm32/src/pac/stm32f427vg.rs @@ -215,41 +215,41 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f427vi.rs b/embassy-stm32/src/pac/stm32f427vi.rs index a3481b09..91b33ba5 100644 --- a/embassy-stm32/src/pac/stm32f427vi.rs +++ b/embassy-stm32/src/pac/stm32f427vi.rs @@ -215,41 +215,41 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f427zg.rs b/embassy-stm32/src/pac/stm32f427zg.rs index 6d811e91..264fb175 100644 --- a/embassy-stm32/src/pac/stm32f427zg.rs +++ b/embassy-stm32/src/pac/stm32f427zg.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f427zi.rs b/embassy-stm32/src/pac/stm32f427zi.rs index 6d811e91..264fb175 100644 --- a/embassy-stm32/src/pac/stm32f427zi.rs +++ b/embassy-stm32/src/pac/stm32f427zi.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429ag.rs b/embassy-stm32/src/pac/stm32f429ag.rs index 7b973e44..ce1caee6 100644 --- a/embassy-stm32/src/pac/stm32f429ag.rs +++ b/embassy-stm32/src/pac/stm32f429ag.rs @@ -215,49 +215,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429ai.rs b/embassy-stm32/src/pac/stm32f429ai.rs index 7b973e44..ce1caee6 100644 --- a/embassy-stm32/src/pac/stm32f429ai.rs +++ b/embassy-stm32/src/pac/stm32f429ai.rs @@ -215,49 +215,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429be.rs b/embassy-stm32/src/pac/stm32f429be.rs index 9a4d45b1..656c87e0 100644 --- a/embassy-stm32/src/pac/stm32f429be.rs +++ b/embassy-stm32/src/pac/stm32f429be.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429bg.rs b/embassy-stm32/src/pac/stm32f429bg.rs index 9a4d45b1..656c87e0 100644 --- a/embassy-stm32/src/pac/stm32f429bg.rs +++ b/embassy-stm32/src/pac/stm32f429bg.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429bi.rs b/embassy-stm32/src/pac/stm32f429bi.rs index 9a4d45b1..656c87e0 100644 --- a/embassy-stm32/src/pac/stm32f429bi.rs +++ b/embassy-stm32/src/pac/stm32f429bi.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429ie.rs b/embassy-stm32/src/pac/stm32f429ie.rs index 9a4d45b1..656c87e0 100644 --- a/embassy-stm32/src/pac/stm32f429ie.rs +++ b/embassy-stm32/src/pac/stm32f429ie.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429ig.rs b/embassy-stm32/src/pac/stm32f429ig.rs index 9a4d45b1..656c87e0 100644 --- a/embassy-stm32/src/pac/stm32f429ig.rs +++ b/embassy-stm32/src/pac/stm32f429ig.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429ii.rs b/embassy-stm32/src/pac/stm32f429ii.rs index 9a4d45b1..656c87e0 100644 --- a/embassy-stm32/src/pac/stm32f429ii.rs +++ b/embassy-stm32/src/pac/stm32f429ii.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429ne.rs b/embassy-stm32/src/pac/stm32f429ne.rs index 9a4d45b1..656c87e0 100644 --- a/embassy-stm32/src/pac/stm32f429ne.rs +++ b/embassy-stm32/src/pac/stm32f429ne.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429ng.rs b/embassy-stm32/src/pac/stm32f429ng.rs index 9a4d45b1..656c87e0 100644 --- a/embassy-stm32/src/pac/stm32f429ng.rs +++ b/embassy-stm32/src/pac/stm32f429ng.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429ni.rs b/embassy-stm32/src/pac/stm32f429ni.rs index 9a4d45b1..656c87e0 100644 --- a/embassy-stm32/src/pac/stm32f429ni.rs +++ b/embassy-stm32/src/pac/stm32f429ni.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429ve.rs b/embassy-stm32/src/pac/stm32f429ve.rs index bc50d0d0..1d8b1c7c 100644 --- a/embassy-stm32/src/pac/stm32f429ve.rs +++ b/embassy-stm32/src/pac/stm32f429ve.rs @@ -215,41 +215,41 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429vg.rs b/embassy-stm32/src/pac/stm32f429vg.rs index bc50d0d0..1d8b1c7c 100644 --- a/embassy-stm32/src/pac/stm32f429vg.rs +++ b/embassy-stm32/src/pac/stm32f429vg.rs @@ -215,41 +215,41 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429vi.rs b/embassy-stm32/src/pac/stm32f429vi.rs index bc50d0d0..1d8b1c7c 100644 --- a/embassy-stm32/src/pac/stm32f429vi.rs +++ b/embassy-stm32/src/pac/stm32f429vi.rs @@ -215,41 +215,41 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429ze.rs b/embassy-stm32/src/pac/stm32f429ze.rs index 9a4d45b1..656c87e0 100644 --- a/embassy-stm32/src/pac/stm32f429ze.rs +++ b/embassy-stm32/src/pac/stm32f429ze.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429zg.rs b/embassy-stm32/src/pac/stm32f429zg.rs index 9a4d45b1..656c87e0 100644 --- a/embassy-stm32/src/pac/stm32f429zg.rs +++ b/embassy-stm32/src/pac/stm32f429zg.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f429zi.rs b/embassy-stm32/src/pac/stm32f429zi.rs index 9a4d45b1..656c87e0 100644 --- a/embassy-stm32/src/pac/stm32f429zi.rs +++ b/embassy-stm32/src/pac/stm32f429zi.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f437ai.rs b/embassy-stm32/src/pac/stm32f437ai.rs index 83748a01..6d5351b4 100644 --- a/embassy-stm32/src/pac/stm32f437ai.rs +++ b/embassy-stm32/src/pac/stm32f437ai.rs @@ -215,49 +215,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f437ig.rs b/embassy-stm32/src/pac/stm32f437ig.rs index 30c8712e..8bdfb2d0 100644 --- a/embassy-stm32/src/pac/stm32f437ig.rs +++ b/embassy-stm32/src/pac/stm32f437ig.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f437ii.rs b/embassy-stm32/src/pac/stm32f437ii.rs index 30c8712e..8bdfb2d0 100644 --- a/embassy-stm32/src/pac/stm32f437ii.rs +++ b/embassy-stm32/src/pac/stm32f437ii.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f437vg.rs b/embassy-stm32/src/pac/stm32f437vg.rs index f7059b8a..f3d6048d 100644 --- a/embassy-stm32/src/pac/stm32f437vg.rs +++ b/embassy-stm32/src/pac/stm32f437vg.rs @@ -215,41 +215,41 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f437vi.rs b/embassy-stm32/src/pac/stm32f437vi.rs index f7059b8a..f3d6048d 100644 --- a/embassy-stm32/src/pac/stm32f437vi.rs +++ b/embassy-stm32/src/pac/stm32f437vi.rs @@ -215,41 +215,41 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f437zg.rs b/embassy-stm32/src/pac/stm32f437zg.rs index 30c8712e..8bdfb2d0 100644 --- a/embassy-stm32/src/pac/stm32f437zg.rs +++ b/embassy-stm32/src/pac/stm32f437zg.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f437zi.rs b/embassy-stm32/src/pac/stm32f437zi.rs index 30c8712e..8bdfb2d0 100644 --- a/embassy-stm32/src/pac/stm32f437zi.rs +++ b/embassy-stm32/src/pac/stm32f437zi.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f439ai.rs b/embassy-stm32/src/pac/stm32f439ai.rs index 128ffc57..cd06ea3a 100644 --- a/embassy-stm32/src/pac/stm32f439ai.rs +++ b/embassy-stm32/src/pac/stm32f439ai.rs @@ -215,49 +215,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f439bg.rs b/embassy-stm32/src/pac/stm32f439bg.rs index 34ffaac9..5a0019b3 100644 --- a/embassy-stm32/src/pac/stm32f439bg.rs +++ b/embassy-stm32/src/pac/stm32f439bg.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f439bi.rs b/embassy-stm32/src/pac/stm32f439bi.rs index 34ffaac9..5a0019b3 100644 --- a/embassy-stm32/src/pac/stm32f439bi.rs +++ b/embassy-stm32/src/pac/stm32f439bi.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f439ig.rs b/embassy-stm32/src/pac/stm32f439ig.rs index 34ffaac9..5a0019b3 100644 --- a/embassy-stm32/src/pac/stm32f439ig.rs +++ b/embassy-stm32/src/pac/stm32f439ig.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f439ii.rs b/embassy-stm32/src/pac/stm32f439ii.rs index 34ffaac9..5a0019b3 100644 --- a/embassy-stm32/src/pac/stm32f439ii.rs +++ b/embassy-stm32/src/pac/stm32f439ii.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f439ng.rs b/embassy-stm32/src/pac/stm32f439ng.rs index 34ffaac9..5a0019b3 100644 --- a/embassy-stm32/src/pac/stm32f439ng.rs +++ b/embassy-stm32/src/pac/stm32f439ng.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f439ni.rs b/embassy-stm32/src/pac/stm32f439ni.rs index 34ffaac9..5a0019b3 100644 --- a/embassy-stm32/src/pac/stm32f439ni.rs +++ b/embassy-stm32/src/pac/stm32f439ni.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f439vg.rs b/embassy-stm32/src/pac/stm32f439vg.rs index 3228bc47..15642387 100644 --- a/embassy-stm32/src/pac/stm32f439vg.rs +++ b/embassy-stm32/src/pac/stm32f439vg.rs @@ -215,41 +215,41 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f439vi.rs b/embassy-stm32/src/pac/stm32f439vi.rs index 3228bc47..15642387 100644 --- a/embassy-stm32/src/pac/stm32f439vi.rs +++ b/embassy-stm32/src/pac/stm32f439vi.rs @@ -215,41 +215,41 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f439zg.rs b/embassy-stm32/src/pac/stm32f439zg.rs index 34ffaac9..5a0019b3 100644 --- a/embassy-stm32/src/pac/stm32f439zg.rs +++ b/embassy-stm32/src/pac/stm32f439zg.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f439zi.rs b/embassy-stm32/src/pac/stm32f439zi.rs index 34ffaac9..5a0019b3 100644 --- a/embassy-stm32/src/pac/stm32f439zi.rs +++ b/embassy-stm32/src/pac/stm32f439zi.rs @@ -215,54 +215,54 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); impl_spi!(SPI5, APB2); -impl_spi_pin!(SPI5, Mosi, PF11, 5); -impl_spi_pin!(SPI5, Sck, PF7, 5); -impl_spi_pin!(SPI5, Miso, PF8, 5); -impl_spi_pin!(SPI5, Mosi, PF9, 5); -impl_spi_pin!(SPI5, Sck, PH6, 5); -impl_spi_pin!(SPI5, Miso, PH7, 5); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); impl_spi!(SPI6, APB2); -impl_spi_pin!(SPI6, Miso, PG12, 5); -impl_spi_pin!(SPI6, Sck, PG13, 5); -impl_spi_pin!(SPI6, Mosi, PG14, 5); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f446mc.rs b/embassy-stm32/src/pac/stm32f446mc.rs index eda63c60..349fc72e 100644 --- a/embassy-stm32/src/pac/stm32f446mc.rs +++ b/embassy-stm32/src/pac/stm32f446mc.rs @@ -162,49 +162,49 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 7); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 7); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Mosi, PB0, 7); -impl_spi_pin!(SPI3, Mosi, PB2, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Mosi, PC1, 5); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD0, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, MosiPin, PB0, 7); +impl_spi_pin!(SPI3, MosiPin, PB2, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, MosiPin, PC1, 5); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD0, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Miso, PD0, 5); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); -impl_spi_pin!(SPI4, Sck, PG11, 6); -impl_spi_pin!(SPI4, Miso, PG12, 6); -impl_spi_pin!(SPI4, Mosi, PG13, 6); +impl_spi_pin!(SPI4, MisoPin, PD0, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PG11, 6); +impl_spi_pin!(SPI4, MisoPin, PG12, 6); +impl_spi_pin!(SPI4, MosiPin, PG13, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f446me.rs b/embassy-stm32/src/pac/stm32f446me.rs index eda63c60..349fc72e 100644 --- a/embassy-stm32/src/pac/stm32f446me.rs +++ b/embassy-stm32/src/pac/stm32f446me.rs @@ -162,49 +162,49 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 7); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 7); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Mosi, PB0, 7); -impl_spi_pin!(SPI3, Mosi, PB2, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Mosi, PC1, 5); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD0, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, MosiPin, PB0, 7); +impl_spi_pin!(SPI3, MosiPin, PB2, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, MosiPin, PC1, 5); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD0, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Miso, PD0, 5); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); -impl_spi_pin!(SPI4, Sck, PG11, 6); -impl_spi_pin!(SPI4, Miso, PG12, 6); -impl_spi_pin!(SPI4, Mosi, PG13, 6); +impl_spi_pin!(SPI4, MisoPin, PD0, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PG11, 6); +impl_spi_pin!(SPI4, MisoPin, PG12, 6); +impl_spi_pin!(SPI4, MosiPin, PG13, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f446rc.rs b/embassy-stm32/src/pac/stm32f446rc.rs index 78c721ce..84c11482 100644 --- a/embassy-stm32/src/pac/stm32f446rc.rs +++ b/embassy-stm32/src/pac/stm32f446rc.rs @@ -162,37 +162,37 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 7); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 7); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Mosi, PB0, 7); -impl_spi_pin!(SPI3, Mosi, PB2, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Mosi, PC1, 5); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD0, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, MosiPin, PB0, 7); +impl_spi_pin!(SPI3, MosiPin, PB2, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, MosiPin, PC1, 5); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD0, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f446re.rs b/embassy-stm32/src/pac/stm32f446re.rs index 78c721ce..84c11482 100644 --- a/embassy-stm32/src/pac/stm32f446re.rs +++ b/embassy-stm32/src/pac/stm32f446re.rs @@ -162,37 +162,37 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 7); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 7); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Mosi, PB0, 7); -impl_spi_pin!(SPI3, Mosi, PB2, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Mosi, PC1, 5); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD0, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, MosiPin, PB0, 7); +impl_spi_pin!(SPI3, MosiPin, PB2, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, MosiPin, PC1, 5); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD0, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f446vc.rs b/embassy-stm32/src/pac/stm32f446vc.rs index eda63c60..349fc72e 100644 --- a/embassy-stm32/src/pac/stm32f446vc.rs +++ b/embassy-stm32/src/pac/stm32f446vc.rs @@ -162,49 +162,49 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 7); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 7); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Mosi, PB0, 7); -impl_spi_pin!(SPI3, Mosi, PB2, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Mosi, PC1, 5); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD0, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, MosiPin, PB0, 7); +impl_spi_pin!(SPI3, MosiPin, PB2, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, MosiPin, PC1, 5); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD0, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Miso, PD0, 5); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); -impl_spi_pin!(SPI4, Sck, PG11, 6); -impl_spi_pin!(SPI4, Miso, PG12, 6); -impl_spi_pin!(SPI4, Mosi, PG13, 6); +impl_spi_pin!(SPI4, MisoPin, PD0, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PG11, 6); +impl_spi_pin!(SPI4, MisoPin, PG12, 6); +impl_spi_pin!(SPI4, MosiPin, PG13, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f446ve.rs b/embassy-stm32/src/pac/stm32f446ve.rs index eda63c60..349fc72e 100644 --- a/embassy-stm32/src/pac/stm32f446ve.rs +++ b/embassy-stm32/src/pac/stm32f446ve.rs @@ -162,49 +162,49 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 7); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 7); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Mosi, PB0, 7); -impl_spi_pin!(SPI3, Mosi, PB2, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Mosi, PC1, 5); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD0, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, MosiPin, PB0, 7); +impl_spi_pin!(SPI3, MosiPin, PB2, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, MosiPin, PC1, 5); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD0, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Miso, PD0, 5); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); -impl_spi_pin!(SPI4, Sck, PG11, 6); -impl_spi_pin!(SPI4, Miso, PG12, 6); -impl_spi_pin!(SPI4, Mosi, PG13, 6); +impl_spi_pin!(SPI4, MisoPin, PD0, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PG11, 6); +impl_spi_pin!(SPI4, MisoPin, PG12, 6); +impl_spi_pin!(SPI4, MosiPin, PG13, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f446zc.rs b/embassy-stm32/src/pac/stm32f446zc.rs index eda63c60..349fc72e 100644 --- a/embassy-stm32/src/pac/stm32f446zc.rs +++ b/embassy-stm32/src/pac/stm32f446zc.rs @@ -162,49 +162,49 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 7); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 7); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Mosi, PB0, 7); -impl_spi_pin!(SPI3, Mosi, PB2, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Mosi, PC1, 5); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD0, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, MosiPin, PB0, 7); +impl_spi_pin!(SPI3, MosiPin, PB2, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, MosiPin, PC1, 5); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD0, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Miso, PD0, 5); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); -impl_spi_pin!(SPI4, Sck, PG11, 6); -impl_spi_pin!(SPI4, Miso, PG12, 6); -impl_spi_pin!(SPI4, Mosi, PG13, 6); +impl_spi_pin!(SPI4, MisoPin, PD0, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PG11, 6); +impl_spi_pin!(SPI4, MisoPin, PG12, 6); +impl_spi_pin!(SPI4, MosiPin, PG13, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32f446ze.rs b/embassy-stm32/src/pac/stm32f446ze.rs index eda63c60..349fc72e 100644 --- a/embassy-stm32/src/pac/stm32f446ze.rs +++ b/embassy-stm32/src/pac/stm32f446ze.rs @@ -162,49 +162,49 @@ impl_gpio_pin!(PH14, 7, 14, EXTI14); impl_gpio_pin!(PH15, 7, 15, EXTI15); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 5); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 7); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PC7, 5); -impl_spi_pin!(SPI2, Sck, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 7); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Mosi, PB0, 7); -impl_spi_pin!(SPI3, Mosi, PB2, 7); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Mosi, PC1, 5); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD0, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); +impl_spi_pin!(SPI3, MosiPin, PB0, 7); +impl_spi_pin!(SPI3, MosiPin, PB2, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, MosiPin, PC1, 5); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD0, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); impl_spi!(SPI4, APB2); -impl_spi_pin!(SPI4, Miso, PD0, 5); -impl_spi_pin!(SPI4, Sck, PE12, 5); -impl_spi_pin!(SPI4, Miso, PE13, 5); -impl_spi_pin!(SPI4, Mosi, PE14, 5); -impl_spi_pin!(SPI4, Sck, PE2, 5); -impl_spi_pin!(SPI4, Miso, PE5, 5); -impl_spi_pin!(SPI4, Mosi, PE6, 5); -impl_spi_pin!(SPI4, Sck, PG11, 6); -impl_spi_pin!(SPI4, Miso, PG12, 6); -impl_spi_pin!(SPI4, Mosi, PG13, 6); +impl_spi_pin!(SPI4, MisoPin, PD0, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PG11, 6); +impl_spi_pin!(SPI4, MisoPin, PG12, 6); +impl_spi_pin!(SPI4, MosiPin, PG13, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l431cb.rs b/embassy-stm32/src/pac/stm32l431cb.rs index 3526babf..73f31d27 100644 --- a/embassy-stm32/src/pac/stm32l431cb.rs +++ b/embassy-stm32/src/pac/stm32l431cb.rs @@ -130,37 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l431cc.rs b/embassy-stm32/src/pac/stm32l431cc.rs index 3526babf..73f31d27 100644 --- a/embassy-stm32/src/pac/stm32l431cc.rs +++ b/embassy-stm32/src/pac/stm32l431cc.rs @@ -130,37 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l431kb.rs b/embassy-stm32/src/pac/stm32l431kb.rs index 6ee92e99..f4fe0605 100644 --- a/embassy-stm32/src/pac/stm32l431kb.rs +++ b/embassy-stm32/src/pac/stm32l431kb.rs @@ -130,26 +130,26 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l431kc.rs b/embassy-stm32/src/pac/stm32l431kc.rs index 6ee92e99..f4fe0605 100644 --- a/embassy-stm32/src/pac/stm32l431kc.rs +++ b/embassy-stm32/src/pac/stm32l431kc.rs @@ -130,26 +130,26 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l431rb.rs b/embassy-stm32/src/pac/stm32l431rb.rs index 3526babf..73f31d27 100644 --- a/embassy-stm32/src/pac/stm32l431rb.rs +++ b/embassy-stm32/src/pac/stm32l431rb.rs @@ -130,37 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l431rc.rs b/embassy-stm32/src/pac/stm32l431rc.rs index 3526babf..73f31d27 100644 --- a/embassy-stm32/src/pac/stm32l431rc.rs +++ b/embassy-stm32/src/pac/stm32l431rc.rs @@ -130,37 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l431vc.rs b/embassy-stm32/src/pac/stm32l431vc.rs index 3526babf..73f31d27 100644 --- a/embassy-stm32/src/pac/stm32l431vc.rs +++ b/embassy-stm32/src/pac/stm32l431vc.rs @@ -130,37 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l432kb.rs b/embassy-stm32/src/pac/stm32l432kb.rs index 520a130a..6f49490e 100644 --- a/embassy-stm32/src/pac/stm32l432kb.rs +++ b/embassy-stm32/src/pac/stm32l432kb.rs @@ -96,23 +96,23 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l432kc.rs b/embassy-stm32/src/pac/stm32l432kc.rs index 520a130a..6f49490e 100644 --- a/embassy-stm32/src/pac/stm32l432kc.rs +++ b/embassy-stm32/src/pac/stm32l432kc.rs @@ -96,23 +96,23 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l433cb.rs b/embassy-stm32/src/pac/stm32l433cb.rs index d7c46042..523c14eb 100644 --- a/embassy-stm32/src/pac/stm32l433cb.rs +++ b/embassy-stm32/src/pac/stm32l433cb.rs @@ -130,37 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l433cc.rs b/embassy-stm32/src/pac/stm32l433cc.rs index d7c46042..523c14eb 100644 --- a/embassy-stm32/src/pac/stm32l433cc.rs +++ b/embassy-stm32/src/pac/stm32l433cc.rs @@ -130,37 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l433rb.rs b/embassy-stm32/src/pac/stm32l433rb.rs index d7c46042..523c14eb 100644 --- a/embassy-stm32/src/pac/stm32l433rb.rs +++ b/embassy-stm32/src/pac/stm32l433rb.rs @@ -130,37 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l433rc.rs b/embassy-stm32/src/pac/stm32l433rc.rs index d7c46042..523c14eb 100644 --- a/embassy-stm32/src/pac/stm32l433rc.rs +++ b/embassy-stm32/src/pac/stm32l433rc.rs @@ -130,37 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l433vc.rs b/embassy-stm32/src/pac/stm32l433vc.rs index d7c46042..523c14eb 100644 --- a/embassy-stm32/src/pac/stm32l433vc.rs +++ b/embassy-stm32/src/pac/stm32l433vc.rs @@ -130,37 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l442kc.rs b/embassy-stm32/src/pac/stm32l442kc.rs index 7a7e0780..43847827 100644 --- a/embassy-stm32/src/pac/stm32l442kc.rs +++ b/embassy-stm32/src/pac/stm32l442kc.rs @@ -96,23 +96,23 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l443cc.rs b/embassy-stm32/src/pac/stm32l443cc.rs index a3a63382..221a674a 100644 --- a/embassy-stm32/src/pac/stm32l443cc.rs +++ b/embassy-stm32/src/pac/stm32l443cc.rs @@ -130,37 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l443rc.rs b/embassy-stm32/src/pac/stm32l443rc.rs index a3a63382..221a674a 100644 --- a/embassy-stm32/src/pac/stm32l443rc.rs +++ b/embassy-stm32/src/pac/stm32l443rc.rs @@ -130,37 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l443vc.rs b/embassy-stm32/src/pac/stm32l443vc.rs index a3a63382..221a674a 100644 --- a/embassy-stm32/src/pac/stm32l443vc.rs +++ b/embassy-stm32/src/pac/stm32l443vc.rs @@ -130,37 +130,37 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496ae.rs b/embassy-stm32/src/pac/stm32l496ae.rs index 4f15b5bf..1b48e204 100644 --- a/embassy-stm32/src/pac/stm32l496ae.rs +++ b/embassy-stm32/src/pac/stm32l496ae.rs @@ -181,49 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496ag.rs b/embassy-stm32/src/pac/stm32l496ag.rs index 4f15b5bf..1b48e204 100644 --- a/embassy-stm32/src/pac/stm32l496ag.rs +++ b/embassy-stm32/src/pac/stm32l496ag.rs @@ -181,49 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496qe.rs b/embassy-stm32/src/pac/stm32l496qe.rs index 4f15b5bf..1b48e204 100644 --- a/embassy-stm32/src/pac/stm32l496qe.rs +++ b/embassy-stm32/src/pac/stm32l496qe.rs @@ -181,49 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496qg.rs b/embassy-stm32/src/pac/stm32l496qg.rs index 4f15b5bf..1b48e204 100644 --- a/embassy-stm32/src/pac/stm32l496qg.rs +++ b/embassy-stm32/src/pac/stm32l496qg.rs @@ -181,49 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496re.rs b/embassy-stm32/src/pac/stm32l496re.rs index 4f15b5bf..1b48e204 100644 --- a/embassy-stm32/src/pac/stm32l496re.rs +++ b/embassy-stm32/src/pac/stm32l496re.rs @@ -181,49 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496rg.rs b/embassy-stm32/src/pac/stm32l496rg.rs index 4f15b5bf..1b48e204 100644 --- a/embassy-stm32/src/pac/stm32l496rg.rs +++ b/embassy-stm32/src/pac/stm32l496rg.rs @@ -181,49 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496ve.rs b/embassy-stm32/src/pac/stm32l496ve.rs index 4f15b5bf..1b48e204 100644 --- a/embassy-stm32/src/pac/stm32l496ve.rs +++ b/embassy-stm32/src/pac/stm32l496ve.rs @@ -181,49 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496vg.rs b/embassy-stm32/src/pac/stm32l496vg.rs index 4f15b5bf..1b48e204 100644 --- a/embassy-stm32/src/pac/stm32l496vg.rs +++ b/embassy-stm32/src/pac/stm32l496vg.rs @@ -181,49 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496wg.rs b/embassy-stm32/src/pac/stm32l496wg.rs index 4f15b5bf..1b48e204 100644 --- a/embassy-stm32/src/pac/stm32l496wg.rs +++ b/embassy-stm32/src/pac/stm32l496wg.rs @@ -181,49 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496ze.rs b/embassy-stm32/src/pac/stm32l496ze.rs index 4f15b5bf..1b48e204 100644 --- a/embassy-stm32/src/pac/stm32l496ze.rs +++ b/embassy-stm32/src/pac/stm32l496ze.rs @@ -181,49 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l496zg.rs b/embassy-stm32/src/pac/stm32l496zg.rs index 4f15b5bf..1b48e204 100644 --- a/embassy-stm32/src/pac/stm32l496zg.rs +++ b/embassy-stm32/src/pac/stm32l496zg.rs @@ -181,49 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l4a6ag.rs b/embassy-stm32/src/pac/stm32l4a6ag.rs index 7384744e..250bd6d9 100644 --- a/embassy-stm32/src/pac/stm32l4a6ag.rs +++ b/embassy-stm32/src/pac/stm32l4a6ag.rs @@ -181,49 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l4a6qg.rs b/embassy-stm32/src/pac/stm32l4a6qg.rs index 7384744e..250bd6d9 100644 --- a/embassy-stm32/src/pac/stm32l4a6qg.rs +++ b/embassy-stm32/src/pac/stm32l4a6qg.rs @@ -181,49 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l4a6rg.rs b/embassy-stm32/src/pac/stm32l4a6rg.rs index 7384744e..250bd6d9 100644 --- a/embassy-stm32/src/pac/stm32l4a6rg.rs +++ b/embassy-stm32/src/pac/stm32l4a6rg.rs @@ -181,49 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l4a6vg.rs b/embassy-stm32/src/pac/stm32l4a6vg.rs index 7384744e..250bd6d9 100644 --- a/embassy-stm32/src/pac/stm32l4a6vg.rs +++ b/embassy-stm32/src/pac/stm32l4a6vg.rs @@ -181,49 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l4a6zg.rs b/embassy-stm32/src/pac/stm32l4a6zg.rs index 7384744e..250bd6d9 100644 --- a/embassy-stm32/src/pac/stm32l4a6zg.rs +++ b/embassy-stm32/src/pac/stm32l4a6zg.rs @@ -181,49 +181,49 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, HASH_RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); impl_usart!(USART1); diff --git a/embassy-stm32/src/pac/stm32l4p5ae.rs b/embassy-stm32/src/pac/stm32l4p5ae.rs index 98ec9830..44abb83b 100644 --- a/embassy-stm32/src/pac/stm32l4p5ae.rs +++ b/embassy-stm32/src/pac/stm32l4p5ae.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5ag.rs b/embassy-stm32/src/pac/stm32l4p5ag.rs index 98ec9830..44abb83b 100644 --- a/embassy-stm32/src/pac/stm32l4p5ag.rs +++ b/embassy-stm32/src/pac/stm32l4p5ag.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5ce.rs b/embassy-stm32/src/pac/stm32l4p5ce.rs index 98ec9830..44abb83b 100644 --- a/embassy-stm32/src/pac/stm32l4p5ce.rs +++ b/embassy-stm32/src/pac/stm32l4p5ce.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5cg.rs b/embassy-stm32/src/pac/stm32l4p5cg.rs index 98ec9830..44abb83b 100644 --- a/embassy-stm32/src/pac/stm32l4p5cg.rs +++ b/embassy-stm32/src/pac/stm32l4p5cg.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5qe.rs b/embassy-stm32/src/pac/stm32l4p5qe.rs index 98ec9830..44abb83b 100644 --- a/embassy-stm32/src/pac/stm32l4p5qe.rs +++ b/embassy-stm32/src/pac/stm32l4p5qe.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5qg.rs b/embassy-stm32/src/pac/stm32l4p5qg.rs index 98ec9830..44abb83b 100644 --- a/embassy-stm32/src/pac/stm32l4p5qg.rs +++ b/embassy-stm32/src/pac/stm32l4p5qg.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5re.rs b/embassy-stm32/src/pac/stm32l4p5re.rs index 98ec9830..44abb83b 100644 --- a/embassy-stm32/src/pac/stm32l4p5re.rs +++ b/embassy-stm32/src/pac/stm32l4p5re.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5rg.rs b/embassy-stm32/src/pac/stm32l4p5rg.rs index 98ec9830..44abb83b 100644 --- a/embassy-stm32/src/pac/stm32l4p5rg.rs +++ b/embassy-stm32/src/pac/stm32l4p5rg.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5ve.rs b/embassy-stm32/src/pac/stm32l4p5ve.rs index 98ec9830..44abb83b 100644 --- a/embassy-stm32/src/pac/stm32l4p5ve.rs +++ b/embassy-stm32/src/pac/stm32l4p5ve.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5vg.rs b/embassy-stm32/src/pac/stm32l4p5vg.rs index 98ec9830..44abb83b 100644 --- a/embassy-stm32/src/pac/stm32l4p5vg.rs +++ b/embassy-stm32/src/pac/stm32l4p5vg.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5ze.rs b/embassy-stm32/src/pac/stm32l4p5ze.rs index 98ec9830..44abb83b 100644 --- a/embassy-stm32/src/pac/stm32l4p5ze.rs +++ b/embassy-stm32/src/pac/stm32l4p5ze.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4p5zg.rs b/embassy-stm32/src/pac/stm32l4p5zg.rs index 98ec9830..44abb83b 100644 --- a/embassy-stm32/src/pac/stm32l4p5zg.rs +++ b/embassy-stm32/src/pac/stm32l4p5zg.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4q5ag.rs b/embassy-stm32/src/pac/stm32l4q5ag.rs index f7ea12de..e302792a 100644 --- a/embassy-stm32/src/pac/stm32l4q5ag.rs +++ b/embassy-stm32/src/pac/stm32l4q5ag.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4q5cg.rs b/embassy-stm32/src/pac/stm32l4q5cg.rs index f7ea12de..e302792a 100644 --- a/embassy-stm32/src/pac/stm32l4q5cg.rs +++ b/embassy-stm32/src/pac/stm32l4q5cg.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4q5qg.rs b/embassy-stm32/src/pac/stm32l4q5qg.rs index f7ea12de..e302792a 100644 --- a/embassy-stm32/src/pac/stm32l4q5qg.rs +++ b/embassy-stm32/src/pac/stm32l4q5qg.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4q5rg.rs b/embassy-stm32/src/pac/stm32l4q5rg.rs index f7ea12de..e302792a 100644 --- a/embassy-stm32/src/pac/stm32l4q5rg.rs +++ b/embassy-stm32/src/pac/stm32l4q5rg.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4q5vg.rs b/embassy-stm32/src/pac/stm32l4q5vg.rs index f7ea12de..e302792a 100644 --- a/embassy-stm32/src/pac/stm32l4q5vg.rs +++ b/embassy-stm32/src/pac/stm32l4q5vg.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4q5zg.rs b/embassy-stm32/src/pac/stm32l4q5zg.rs index f7ea12de..e302792a 100644 --- a/embassy-stm32/src/pac/stm32l4q5zg.rs +++ b/embassy-stm32/src/pac/stm32l4q5zg.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r5ag.rs b/embassy-stm32/src/pac/stm32l4r5ag.rs index 0fad849d..588b4683 100644 --- a/embassy-stm32/src/pac/stm32l4r5ag.rs +++ b/embassy-stm32/src/pac/stm32l4r5ag.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r5ai.rs b/embassy-stm32/src/pac/stm32l4r5ai.rs index 0fad849d..588b4683 100644 --- a/embassy-stm32/src/pac/stm32l4r5ai.rs +++ b/embassy-stm32/src/pac/stm32l4r5ai.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r5qg.rs b/embassy-stm32/src/pac/stm32l4r5qg.rs index 0fad849d..588b4683 100644 --- a/embassy-stm32/src/pac/stm32l4r5qg.rs +++ b/embassy-stm32/src/pac/stm32l4r5qg.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r5qi.rs b/embassy-stm32/src/pac/stm32l4r5qi.rs index 0fad849d..588b4683 100644 --- a/embassy-stm32/src/pac/stm32l4r5qi.rs +++ b/embassy-stm32/src/pac/stm32l4r5qi.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r5vg.rs b/embassy-stm32/src/pac/stm32l4r5vg.rs index 0fad849d..588b4683 100644 --- a/embassy-stm32/src/pac/stm32l4r5vg.rs +++ b/embassy-stm32/src/pac/stm32l4r5vg.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r5vi.rs b/embassy-stm32/src/pac/stm32l4r5vi.rs index 0fad849d..588b4683 100644 --- a/embassy-stm32/src/pac/stm32l4r5vi.rs +++ b/embassy-stm32/src/pac/stm32l4r5vi.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r5zg.rs b/embassy-stm32/src/pac/stm32l4r5zg.rs index 0fad849d..588b4683 100644 --- a/embassy-stm32/src/pac/stm32l4r5zg.rs +++ b/embassy-stm32/src/pac/stm32l4r5zg.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r5zi.rs b/embassy-stm32/src/pac/stm32l4r5zi.rs index 0fad849d..588b4683 100644 --- a/embassy-stm32/src/pac/stm32l4r5zi.rs +++ b/embassy-stm32/src/pac/stm32l4r5zi.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r7ai.rs b/embassy-stm32/src/pac/stm32l4r7ai.rs index 4bc279c4..39c03935 100644 --- a/embassy-stm32/src/pac/stm32l4r7ai.rs +++ b/embassy-stm32/src/pac/stm32l4r7ai.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r7vi.rs b/embassy-stm32/src/pac/stm32l4r7vi.rs index 4bc279c4..39c03935 100644 --- a/embassy-stm32/src/pac/stm32l4r7vi.rs +++ b/embassy-stm32/src/pac/stm32l4r7vi.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r7zi.rs b/embassy-stm32/src/pac/stm32l4r7zi.rs index 4bc279c4..39c03935 100644 --- a/embassy-stm32/src/pac/stm32l4r7zi.rs +++ b/embassy-stm32/src/pac/stm32l4r7zi.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r9ag.rs b/embassy-stm32/src/pac/stm32l4r9ag.rs index 2a0a52d4..d4bc778f 100644 --- a/embassy-stm32/src/pac/stm32l4r9ag.rs +++ b/embassy-stm32/src/pac/stm32l4r9ag.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r9ai.rs b/embassy-stm32/src/pac/stm32l4r9ai.rs index 2a0a52d4..d4bc778f 100644 --- a/embassy-stm32/src/pac/stm32l4r9ai.rs +++ b/embassy-stm32/src/pac/stm32l4r9ai.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r9vg.rs b/embassy-stm32/src/pac/stm32l4r9vg.rs index 2a0a52d4..d4bc778f 100644 --- a/embassy-stm32/src/pac/stm32l4r9vg.rs +++ b/embassy-stm32/src/pac/stm32l4r9vg.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r9vi.rs b/embassy-stm32/src/pac/stm32l4r9vi.rs index 2a0a52d4..d4bc778f 100644 --- a/embassy-stm32/src/pac/stm32l4r9vi.rs +++ b/embassy-stm32/src/pac/stm32l4r9vi.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r9zg.rs b/embassy-stm32/src/pac/stm32l4r9zg.rs index 2a0a52d4..d4bc778f 100644 --- a/embassy-stm32/src/pac/stm32l4r9zg.rs +++ b/embassy-stm32/src/pac/stm32l4r9zg.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4r9zi.rs b/embassy-stm32/src/pac/stm32l4r9zi.rs index 2a0a52d4..d4bc778f 100644 --- a/embassy-stm32/src/pac/stm32l4r9zi.rs +++ b/embassy-stm32/src/pac/stm32l4r9zi.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s5ai.rs b/embassy-stm32/src/pac/stm32l4s5ai.rs index 81671a5d..86caf9c5 100644 --- a/embassy-stm32/src/pac/stm32l4s5ai.rs +++ b/embassy-stm32/src/pac/stm32l4s5ai.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s5qi.rs b/embassy-stm32/src/pac/stm32l4s5qi.rs index 81671a5d..86caf9c5 100644 --- a/embassy-stm32/src/pac/stm32l4s5qi.rs +++ b/embassy-stm32/src/pac/stm32l4s5qi.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s5vi.rs b/embassy-stm32/src/pac/stm32l4s5vi.rs index 81671a5d..86caf9c5 100644 --- a/embassy-stm32/src/pac/stm32l4s5vi.rs +++ b/embassy-stm32/src/pac/stm32l4s5vi.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s5zi.rs b/embassy-stm32/src/pac/stm32l4s5zi.rs index 81671a5d..86caf9c5 100644 --- a/embassy-stm32/src/pac/stm32l4s5zi.rs +++ b/embassy-stm32/src/pac/stm32l4s5zi.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s7ai.rs b/embassy-stm32/src/pac/stm32l4s7ai.rs index 402b2cad..abee0fd9 100644 --- a/embassy-stm32/src/pac/stm32l4s7ai.rs +++ b/embassy-stm32/src/pac/stm32l4s7ai.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s7vi.rs b/embassy-stm32/src/pac/stm32l4s7vi.rs index 402b2cad..abee0fd9 100644 --- a/embassy-stm32/src/pac/stm32l4s7vi.rs +++ b/embassy-stm32/src/pac/stm32l4s7vi.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s7zi.rs b/embassy-stm32/src/pac/stm32l4s7zi.rs index 402b2cad..abee0fd9 100644 --- a/embassy-stm32/src/pac/stm32l4s7zi.rs +++ b/embassy-stm32/src/pac/stm32l4s7zi.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s9ai.rs b/embassy-stm32/src/pac/stm32l4s9ai.rs index ccabd113..1207d866 100644 --- a/embassy-stm32/src/pac/stm32l4s9ai.rs +++ b/embassy-stm32/src/pac/stm32l4s9ai.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s9vi.rs b/embassy-stm32/src/pac/stm32l4s9vi.rs index ccabd113..1207d866 100644 --- a/embassy-stm32/src/pac/stm32l4s9vi.rs +++ b/embassy-stm32/src/pac/stm32l4s9vi.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/pac/stm32l4s9zi.rs b/embassy-stm32/src/pac/stm32l4s9zi.rs index ccabd113..1207d866 100644 --- a/embassy-stm32/src/pac/stm32l4s9zi.rs +++ b/embassy-stm32/src/pac/stm32l4s9zi.rs @@ -181,50 +181,50 @@ pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); impl_rng!(RNG, RNG); pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); impl_spi!(SPI1, APB2); -impl_spi_pin!(SPI1, Sck, PA1, 5); -impl_spi_pin!(SPI1, Miso, PA11, 5); -impl_spi_pin!(SPI1, Mosi, PA12, 5); -impl_spi_pin!(SPI1, Sck, PA5, 5); -impl_spi_pin!(SPI1, Miso, PA6, 5); -impl_spi_pin!(SPI1, Mosi, PA7, 5); -impl_spi_pin!(SPI1, Sck, PB3, 5); -impl_spi_pin!(SPI1, Miso, PB4, 5); -impl_spi_pin!(SPI1, Mosi, PB5, 5); -impl_spi_pin!(SPI1, Sck, PE13, 5); -impl_spi_pin!(SPI1, Miso, PE14, 5); -impl_spi_pin!(SPI1, Mosi, PE15, 5); -impl_spi_pin!(SPI1, Sck, PG2, 5); -impl_spi_pin!(SPI1, Miso, PG3, 5); -impl_spi_pin!(SPI1, Mosi, PG4, 5); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); impl_spi!(SPI2, APB1); -impl_spi_pin!(SPI2, Sck, PA9, 3); -impl_spi_pin!(SPI2, Sck, PB10, 5); -impl_spi_pin!(SPI2, Sck, PB13, 5); -impl_spi_pin!(SPI2, Miso, PB14, 5); -impl_spi_pin!(SPI2, Mosi, PB15, 5); -impl_spi_pin!(SPI2, Mosi, PC1, 3); -impl_spi_pin!(SPI2, Miso, PC2, 5); -impl_spi_pin!(SPI2, Mosi, PC3, 5); -impl_spi_pin!(SPI2, Sck, PD1, 5); -impl_spi_pin!(SPI2, Sck, PD3, 3); -impl_spi_pin!(SPI2, Miso, PD3, 5); -impl_spi_pin!(SPI2, Mosi, PD4, 5); -impl_spi_pin!(SPI2, Sck, PI1, 5); -impl_spi_pin!(SPI2, Miso, PI2, 5); -impl_spi_pin!(SPI2, Mosi, PI3, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); impl_spi!(SPI3, APB1); -impl_spi_pin!(SPI3, Sck, PB3, 6); -impl_spi_pin!(SPI3, Miso, PB4, 6); -impl_spi_pin!(SPI3, Mosi, PB5, 6); -impl_spi_pin!(SPI3, Sck, PC10, 6); -impl_spi_pin!(SPI3, Miso, PC11, 6); -impl_spi_pin!(SPI3, Mosi, PC12, 6); -impl_spi_pin!(SPI3, Mosi, PD6, 5); -impl_spi_pin!(SPI3, Miso, PG10, 6); -impl_spi_pin!(SPI3, Mosi, PG11, 6); -impl_spi_pin!(SPI3, Sck, PG9, 6); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); pub use regs::dma_v1 as dma; pub use regs::exti_v1 as exti; diff --git a/embassy-stm32/src/rng.rs b/embassy-stm32/src/rng.rs index 672a8f62..bc613e0a 100644 --- a/embassy-stm32/src/rng.rs +++ b/embassy-stm32/src/rng.rs @@ -2,18 +2,22 @@ use core::future::Future; use core::task::Poll; -use defmt::*; use embassy::traits; use embassy::util::{AtomicWaker, Unborrow}; use embassy_extras::unborrow; use futures::future::poll_fn; use rand_core::{CryptoRng, RngCore}; -//Guse crate::interrupt; +use crate::interrupt; use crate::pac; pub(crate) static RNG_WAKER: AtomicWaker = AtomicWaker::new(); +pub enum Error { + SeedError, + ClockError, +} + pub struct Random { inner: T, } @@ -75,11 +79,6 @@ impl RngCore for Random { impl CryptoRng for Random {} -pub enum Error { - SeedError, - ClockError, -} - impl traits::rng::Rng for Random { type Error = Error; #[rustfmt::skip] @@ -146,12 +145,16 @@ macro_rules! impl_rng { impl crate::rng::Instance for peripherals::RNG {} - #[$crate::interrupt] - unsafe fn $irq() { - let bits = $crate::pac::RNG.sr().read(); - if bits.drdy() || bits.seis() || bits.ceis() { - $crate::pac::RNG.cr().write(|reg| reg.set_ie(false)); - $crate::rng::RNG_WAKER.wake(); + mod rng_irq { + use crate::interrupt; + + #[interrupt] + unsafe fn $irq() { + let bits = $crate::pac::RNG.sr().read(); + if bits.drdy() || bits.seis() || bits.ceis() { + $crate::pac::RNG.cr().write(|reg| reg.set_ie(false)); + $crate::rng::RNG_WAKER.wake(); + } } } }; diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs index 27f1be93..3e00fdd4 100644 --- a/embassy-stm32/src/spi/mod.rs +++ b/embassy-stm32/src/spi/mod.rs @@ -6,6 +6,12 @@ mod spi; pub use spi::*; +pub enum Error { + Framing, + Crc, + Overrun, +} + // TODO move upwards in the tree pub enum ByteOrder { LsbFirst, @@ -32,3 +38,64 @@ impl Default for Config { } } } + +pub(crate) mod sealed { + use super::*; + use crate::gpio::Pin; + use embassy::util::AtomicWaker; + + pub trait Instance { + fn regs() -> &'static crate::pac::spi::Spi; + } + + pub trait SckPin: Pin { + const AF: u8; + fn af(&self) -> u8 { + Self::AF + } + } + + pub trait MosiPin: Pin { + const AF: u8; + fn af(&self) -> u8 { + Self::AF + } + } + + pub trait MisoPin: Pin { + const AF: u8; + fn af(&self) -> u8 { + Self::AF + } + } +} + +pub trait Instance: sealed::Instance + 'static {} + +pub trait SckPin: sealed::SckPin + 'static {} + +pub trait MosiPin: sealed::MosiPin + 'static {} + +pub trait MisoPin: sealed::MisoPin + 'static {} + +macro_rules! impl_spi { + ($inst:ident, $clk:ident) => { + impl crate::spi::sealed::Instance for peripherals::$inst { + fn regs() -> &'static crate::pac::spi::Spi { + &crate::pac::$inst + } + } + + impl crate::spi::Instance for peripherals::$inst {} + }; +} + +macro_rules! impl_spi_pin { + ($inst:ident, $pin_func:ident, $pin:ident, $af:expr) => { + impl crate::spi::$pin_func for peripherals::$pin {} + + impl crate::spi::sealed::$pin_func for peripherals::$pin { + const AF: u8 = $af; + } + }; +} diff --git a/embassy-stm32/src/spi/spi_v1.rs b/embassy-stm32/src/spi/spi_v1.rs index 3ef096e4..002fe207 100644 --- a/embassy-stm32/src/spi/spi_v1.rs +++ b/embassy-stm32/src/spi/spi_v1.rs @@ -1,17 +1,15 @@ #![macro_use] -pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; -use core::marker::PhantomData; -use embassy::interrupt::Interrupt; -use embedded_hal::blocking::spi::{Write, Transfer}; -use embassy::util::Unborrow; -use embassy_extras::{impl_unborrow, unborrow}; -use crate::gpio::{Pin, AnyPin}; +use crate::gpio::{AnyPin, Pin}; use crate::pac::gpio::vals::{Afr, Moder}; -use crate::pac::spi; use crate::pac::gpio::Gpio; +use crate::pac::spi; +use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; use crate::time::Hertz; -use crate::spi::{WordSize, Config, ByteOrder}; +use core::marker::PhantomData; +use embassy::util::Unborrow; +use embassy_extras::unborrow; +pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; impl WordSize { fn dff(&self) -> spi::vals::Dff { @@ -23,7 +21,7 @@ impl WordSize { } pub struct Spi<'d, T: Instance> { - peri: T, + //peri: T, sck: AnyPin, mosi: AnyPin, miso: AnyPin, @@ -32,16 +30,17 @@ pub struct Spi<'d, T: Instance> { } impl<'d, T: Instance> Spi<'d, T> { - pub fn new(pclk: Hertz, - peri: impl Unborrow + 'd, - sck: impl Unborrow>, - mosi: impl Unborrow>, - miso: impl Unborrow>, - freq: F, - config: Config, + pub fn new( + pclk: Hertz, + peri: impl Unborrow + 'd, + sck: impl Unborrow>, + mosi: impl Unborrow>, + miso: impl Unborrow>, + freq: F, + config: Config, ) -> Self - where - F: Into + where + F: Into, { unborrow!(peri); unborrow!(sck, mosi, miso); @@ -57,10 +56,9 @@ impl<'d, T: Instance> Spi<'d, T> { let miso = miso.degrade(); unsafe { - T::regs().cr2() - .write(|w| { - w.set_ssoe(false); - }); + T::regs().cr2().write(|w| { + w.set_ssoe(false); + }); } let br = Self::compute_baud_rate(pclk, freq.into()); @@ -71,7 +69,7 @@ impl<'d, T: Instance> Spi<'d, T> { match config.mode.phase == Phase::CaptureOnSecondTransition { true => spi::vals::Cpha::SECONDEDGE, false => spi::vals::Cpha::FIRSTEDGE, - } + }, ); w.set_cpol(match config.mode.polarity == Polarity::IdleHigh { true => spi::vals::Cpol::IDLEHIGH, @@ -81,22 +79,20 @@ impl<'d, T: Instance> Spi<'d, T> { w.set_mstr(spi::vals::Mstr::MASTER); w.set_br(spi::vals::Br(br)); w.set_spe(true); - w.set_lsbfirst( - match config.byte_order { - ByteOrder::LsbFirst => spi::vals::Lsbfirst::LSBFIRST, - ByteOrder::MsbFirst => spi::vals::Lsbfirst::MSBFIRST, - } - ); + w.set_lsbfirst(match config.byte_order { + ByteOrder::LsbFirst => spi::vals::Lsbfirst::LSBFIRST, + ByteOrder::MsbFirst => spi::vals::Lsbfirst::MSBFIRST, + }); w.set_ssi(true); w.set_ssm(true); w.set_crcen(false); w.set_bidimode(spi::vals::Bidimode::UNIDIRECTIONAL); - w.set_dff( WordSize::EightBit.dff() ) + w.set_dff(WordSize::EightBit.dff()) }); } Self { - peri, + //peri, sck, mosi, miso, @@ -112,7 +108,6 @@ impl<'d, T: Instance> Spi<'d, T> { } unsafe fn unconfigure_pin(block: Gpio, pin: usize) { - let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) }; block.moder().modify(|w| w.set_moder(pin, Moder::ANALOG)); } @@ -132,14 +127,14 @@ impl<'d, T: Instance> Spi<'d, T> { fn set_word_size(&mut self, word_size: WordSize) { if self.current_word_size == word_size { - return + return; } unsafe { - T::regs().cr1().modify( |reg| { + T::regs().cr1().modify(|reg| { reg.set_spe(false); - reg.set_dff( word_size.dff() ) + reg.set_dff(word_size.dff()) }); - T::regs().cr1().modify( |reg| { + T::regs().cr1().modify(|reg| { reg.set_spe(true); }); self.current_word_size = word_size; @@ -157,12 +152,6 @@ impl<'d, T: Instance> Drop for Spi<'d, T> { } } -pub enum Error { - Framing, - Crc, - Overrun, -} - impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { type Error = Error; @@ -300,65 +289,3 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> Ok(words) } } - - -pub(crate) mod sealed { - use super::*; - use embassy::util::AtomicWaker; - - pub trait Instance { - fn regs() -> &'static spi::Spi; - } - - pub trait Sck: Pin { - const AF: u8; - fn af(&self) -> u8 { - Self::AF - } - } - - pub trait Mosi: Pin { - const AF: u8; - fn af(&self) -> u8 { - Self::AF - } - } - - pub trait Miso: Pin { - const AF: u8; - fn af(&self) -> u8 { - Self::AF - } - } -} - -pub trait Instance: sealed::Instance + 'static {} - -pub trait Sck: sealed::Sck + 'static {} - -pub trait Mosi: sealed::Mosi + 'static {} - -pub trait Miso: sealed::Miso + 'static {} - -macro_rules! impl_spi { - ($inst:ident, $clk:ident) => { - impl crate::spi::sealed::Instance for peripherals::$inst { - fn regs() -> &'static crate::pac::spi::Spi { - &crate::pac::$inst - } - } - - impl crate::spi::Instance for peripherals::$inst {} - }; -} - -macro_rules! impl_spi_pin { - ($inst:ident, $pin_func:ident, $pin:ident, $af:expr) => { - impl crate::spi::$pin_func for peripherals::$pin { - } - - impl crate::spi::sealed::$pin_func for peripherals::$pin { - const AF: u8 = $af; - } - } -} \ No newline at end of file diff --git a/embassy-stm32/src/spi/spi_v2.rs b/embassy-stm32/src/spi/spi_v2.rs index 48370c84..b6ae8b27 100644 --- a/embassy-stm32/src/spi/spi_v2.rs +++ b/embassy-stm32/src/spi/spi_v2.rs @@ -1,17 +1,15 @@ #![macro_use] -pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; -use core::marker::PhantomData; -use embassy::interrupt::Interrupt; -use embedded_hal::blocking::spi::{Write, Transfer}; -use embassy::util::Unborrow; -use embassy_extras::{impl_unborrow, unborrow}; -use crate::gpio::{Pin, AnyPin}; +use crate::gpio::{AnyPin, Pin}; use crate::pac::gpio::vals::{Afr, Moder}; -use crate::pac::spi; use crate::pac::gpio::Gpio; +use crate::pac::spi; +use crate::spi::{ByteOrder, Config, Instance, MisoPin, MosiPin, SckPin, WordSize}; use crate::time::Hertz; -use crate::spi::{WordSize, Config, ByteOrder}; +use core::marker::PhantomData; +use embassy::util::Unborrow; +use embassy_extras::unborrow; +pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; impl WordSize { fn ds(&self) -> spi::vals::Ds { @@ -30,25 +28,25 @@ impl WordSize { } pub struct Spi<'d, T: Instance> { - peri: T, + //peri: T, sck: AnyPin, mosi: AnyPin, miso: AnyPin, - //irq: T::Interrupt, phantom: PhantomData<&'d mut T>, } impl<'d, T: Instance> Spi<'d, T> { - pub fn new(pclk: Hertz, - peri: impl Unborrow + 'd, - sck: impl Unborrow>, - mosi: impl Unborrow>, - miso: impl Unborrow>, - freq: F, - config: Config, + pub fn new( + pclk: Hertz, + peri: impl Unborrow + 'd, + sck: impl Unborrow>, + mosi: impl Unborrow>, + miso: impl Unborrow>, + freq: F, + config: Config, ) -> Self - where - F: Into + where + F: Into, { unborrow!(peri); unborrow!(sck, mosi, miso); @@ -64,10 +62,9 @@ impl<'d, T: Instance> Spi<'d, T> { let miso = miso.degrade(); unsafe { - T::regs().cr2() - .write(|w| { - w.set_ssoe(false); - }); + T::regs().cr2().write(|w| { + w.set_ssoe(false); + }); } let br = Self::compute_baud_rate(pclk, freq.into()); @@ -78,7 +75,7 @@ impl<'d, T: Instance> Spi<'d, T> { match config.mode.phase == Phase::CaptureOnSecondTransition { true => spi::vals::Cpha::SECONDEDGE, false => spi::vals::Cpha::FIRSTEDGE, - } + }, ); w.set_cpol(match config.mode.polarity == Polarity::IdleHigh { true => spi::vals::Cpol::IDLEHIGH, @@ -88,12 +85,10 @@ impl<'d, T: Instance> Spi<'d, T> { w.set_mstr(spi::vals::Mstr::MASTER); w.set_br(spi::vals::Br(br)); w.set_spe(true); - w.set_lsbfirst( - match config.byte_order { - ByteOrder::LsbFirst => spi::vals::Lsbfirst::LSBFIRST, - ByteOrder::MsbFirst => spi::vals::Lsbfirst::MSBFIRST, - } - ); + w.set_lsbfirst(match config.byte_order { + ByteOrder::LsbFirst => spi::vals::Lsbfirst::LSBFIRST, + ByteOrder::MsbFirst => spi::vals::Lsbfirst::MSBFIRST, + }); w.set_ssi(true); w.set_ssm(true); w.set_crcen(false); @@ -102,7 +97,7 @@ impl<'d, T: Instance> Spi<'d, T> { } Self { - peri, + //peri, sck, mosi, miso, @@ -117,7 +112,6 @@ impl<'d, T: Instance> Spi<'d, T> { } unsafe fn unconfigure_pin(block: Gpio, pin: usize) { - let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) }; block.moder().modify(|w| w.set_moder(pin, Moder::ANALOG)); } @@ -137,11 +131,10 @@ impl<'d, T: Instance> Spi<'d, T> { fn set_word_size(word_size: WordSize) { unsafe { - T::regs().cr2() - .write(|w| { - w.set_ds(word_size.ds()); - w.set_frxth(word_size.frxth()); - }); + T::regs().cr2().write(|w| { + w.set_ds(word_size.ds()); + w.set_frxth(word_size.frxth()); + }); } } } @@ -299,65 +292,3 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> Ok(words) } } - - -pub(crate) mod sealed { - use super::*; - use embassy::util::AtomicWaker; - - pub trait Instance { - fn regs() -> &'static spi::Spi; - } - - pub trait Sck: Pin { - const AF: u8; - fn af(&self) -> u8 { - Self::AF - } - } - - pub trait Mosi: Pin { - const AF: u8; - fn af(&self) -> u8 { - Self::AF - } - } - - pub trait Miso: Pin { - const AF: u8; - fn af(&self) -> u8 { - Self::AF - } - } -} - -pub trait Instance: sealed::Instance + 'static {} - -pub trait Sck: sealed::Sck + 'static {} - -pub trait Mosi: sealed::Mosi + 'static {} - -pub trait Miso: sealed::Miso + 'static {} - -macro_rules! impl_spi { - ($inst:ident, $clk:ident) => { - impl crate::spi::sealed::Instance for peripherals::$inst { - fn regs() -> &'static crate::pac::spi::Spi { - &crate::pac::$inst - } - } - - impl crate::spi::Instance for peripherals::$inst {} - }; -} - -macro_rules! impl_spi_pin { - ($inst:ident, $pin_func:ident, $pin:ident, $af:expr) => { - impl crate::spi::$pin_func for peripherals::$pin { - } - - impl crate::spi::sealed::$pin_func for peripherals::$pin { - const AF: u8 = $af; - } - } -} \ No newline at end of file diff --git a/embassy-stm32/src/time.rs b/embassy-stm32/src/time.rs index 4df799e3..c131415c 100644 --- a/embassy-stm32/src/time.rs +++ b/embassy-stm32/src/time.rs @@ -1,4 +1,3 @@ - //! Time units /// Bits per second @@ -124,4 +123,4 @@ impl Into for MilliSeconds { fn into(self) -> MicroSeconds { MicroSeconds(self.0 * 1_000) } -} \ No newline at end of file +} diff --git a/embassy-stm32/stm32-data b/embassy-stm32/stm32-data index e06947f2..500cb4b3 160000 --- a/embassy-stm32/stm32-data +++ b/embassy-stm32/stm32-data @@ -1 +1 @@ -Subproject commit e06947f20f01c938d95410d4310c09d116dbca47 +Subproject commit 500cb4b31aa767347f6360c6002c8a89adabd3b6 From 28533cfc77e47148122df868ac13132dbfc0740f Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Sat, 15 May 2021 00:47:22 +0200 Subject: [PATCH 8/8] Simplify SPI example --- embassy-stm32-examples/src/bin/spi.rs | 36 ++++++--------------------- 1 file changed, 7 insertions(+), 29 deletions(-) diff --git a/embassy-stm32-examples/src/bin/spi.rs b/embassy-stm32-examples/src/bin/spi.rs index 308c1c68..59ba0958 100644 --- a/embassy-stm32-examples/src/bin/spi.rs +++ b/embassy-stm32-examples/src/bin/spi.rs @@ -8,14 +8,14 @@ #[path = "../example_common.rs"] mod example_common; -use embassy_stm32::gpio::{Level, Output, Input, Pull}; -use embedded_hal::digital::v2::{OutputPin, InputPin}; +use embassy_stm32::gpio::{Input, Level, Output, Pull}; +use embedded_hal::digital::v2::{InputPin, OutputPin}; use example_common::*; use cortex_m_rt::entry; use stm32f4::stm32f429 as pac; //use stm32l4::stm32l4x5 as pac; -use embassy_stm32::spi::{Spi, MODE_0, ByteOrder, Config}; +use embassy_stm32::spi::{ByteOrder, Config, Spi, MODE_0}; use embassy_stm32::time::Hertz; use embedded_hal::blocking::spi::Transfer; @@ -48,10 +48,8 @@ fn main() -> ! { }); let rc = pp.RCC.cfgr.read().sws().bits(); - info!("rcc -> {}", rc); let p = embassy_stm32::init(Default::default()); - let mut led = Output::new(p.PA5, Level::High); let mut spi = Spi::new( Hertz(16_000_000), p.SPI3, @@ -62,33 +60,13 @@ fn main() -> ! { Config::default(), ); - let mut cs = Output::new( p.PE0, Level::High); - cs.set_low(); - - let mut rdy = Input::new(p.PE1, Pull::Down); - let mut wake = Output::new( p.PB13, Level::Low); - let mut reset = Output::new( p.PE8, Level::Low); - - wake.set_high().unwrap(); - reset.set_high().unwrap(); + let mut cs = Output::new(p.PE0, Level::High); loop { - info!("loop"); - while rdy.is_low().unwrap() { - info!("await ready") - } - info!("ready"); - let mut buf = [0x0A;4]; + let mut buf = [0x0A; 4]; + cs.set_low(); spi.transfer(&mut buf); + cs.set_high(); info!("xfer {=[u8]:x}", buf); } - - loop { - info!("high"); - led.set_high().unwrap(); - cortex_m::asm::delay(10_000_000); - info!("low"); - led.set_low().unwrap(); - cortex_m::asm::delay(10_000_000); - } }