From 39d06b59cd8eb6f64e5986bfaaf4e5f7d504f5c1 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Mon, 14 Feb 2022 02:12:06 +0100 Subject: [PATCH] Update stm32-data --- embassy-stm32/src/i2c/v1.rs | 52 +++++++++++++----------------------- embassy-stm32/src/i2c/v2.rs | 18 ++++++------- embassy-stm32/src/rcc/f0.rs | 21 ++++++--------- embassy-stm32/src/rcc/f1.rs | 2 +- embassy-stm32/src/rcc/f3.rs | 10 +++---- embassy-stm32/src/rcc/f4.rs | 4 +-- embassy-stm32/src/rcc/f7.rs | 4 +-- embassy-stm32/src/rcc/g0.rs | 6 ++--- embassy-stm32/src/rcc/h7.rs | 8 ++---- embassy-stm32/src/rcc/l0.rs | 2 +- embassy-stm32/src/rcc/l1.rs | 2 +- embassy-stm32/src/rcc/mod.rs | 27 ++++--------------- stm32-data | 2 +- 13 files changed, 56 insertions(+), 102 deletions(-) diff --git a/embassy-stm32/src/i2c/v1.rs b/embassy-stm32/src/i2c/v1.rs index 922c1c7e..5a9e8282 100644 --- a/embassy-stm32/src/i2c/v1.rs +++ b/embassy-stm32/src/i2c/v1.rs @@ -108,11 +108,11 @@ impl<'d, T: Instance> I2c<'d, T> { // Send a START condition T::regs().cr1().modify(|reg| { - reg.set_start(i2c::vals::Start::START); + reg.set_start(true); }); // Wait until START condition was generated - while self.check_and_clear_error_flags()?.sb() == i2c::vals::Sb::NOSTART {} + while !self.check_and_clear_error_flags()?.start() {} // Also wait until signalled we're master and everything is waiting for us while { @@ -126,13 +126,9 @@ impl<'d, T: Instance> I2c<'d, T> { T::regs().dr().write(|reg| reg.set_dr(addr << 1)); // Wait until address was sent - while { - // Check for any I2C errors. If a NACK occurs, the ADDR bit will never be set. - let sr1 = self.check_and_clear_error_flags()?; - - // Wait for the address to be acknowledged - !sr1.addr() - } {} + // Wait for the address to be acknowledged + // Check for any I2C errors. If a NACK occurs, the ADDR bit will never be set. + while !self.check_and_clear_error_flags()?.addr() {} // Clear condition by reading SR2 let _ = T::regs().sr2().read(); @@ -150,7 +146,7 @@ impl<'d, T: Instance> I2c<'d, T> { // Wait until we're ready for sending while { // Check for any I2C errors. If a NACK occurs, the ADDR bit will never be set. - !self.check_and_clear_error_flags()?.tx_e() + !self.check_and_clear_error_flags()?.txe() } {} // Push out a byte of data @@ -170,7 +166,7 @@ impl<'d, T: Instance> I2c<'d, T> { // Check for any potential error conditions. self.check_and_clear_error_flags()?; - !T::regs().sr1().read().rx_ne() + !T::regs().sr1().read().rxne() } {} let value = T::regs().dr().read().dr(); @@ -182,13 +178,13 @@ impl<'d, T: Instance> I2c<'d, T> { // Send a START condition and set ACK bit unsafe { T::regs().cr1().modify(|reg| { - reg.set_start(i2c::vals::Start::START); + reg.set_start(true); reg.set_ack(true); }); } // Wait until START condition was generated - while unsafe { T::regs().sr1().read().sb() } == i2c::vals::Sb::NOSTART {} + while unsafe { !T::regs().sr1().read().start() } {} // Also wait until signalled we're master and everything is waiting for us while { @@ -197,24 +193,14 @@ impl<'d, T: Instance> I2c<'d, T> { } {} // Set up current address, we're trying to talk to - unsafe { - T::regs().dr().write(|reg| reg.set_dr((addr << 1) + 1)); - } + unsafe { T::regs().dr().write(|reg| reg.set_dr((addr << 1) + 1)) } // Wait until address was sent - while { - unsafe { - let sr1 = self.check_and_clear_error_flags()?; - - // Wait for the address to be acknowledged - !sr1.addr() - } - } {} + // Wait for the address to be acknowledged + while unsafe { !self.check_and_clear_error_flags()?.addr() } {} // Clear condition by reading SR2 - unsafe { - let _ = T::regs().sr2().read(); - } + let _ = unsafe { T::regs().sr2().read() }; // Receive bytes into buffer for c in buffer { @@ -225,15 +211,15 @@ impl<'d, T: Instance> I2c<'d, T> { unsafe { T::regs().cr1().modify(|reg| { reg.set_ack(false); - reg.set_stop(i2c::vals::Stop::STOP); - }); + reg.set_stop(true); + }) } // Receive last byte *last = unsafe { self.recv_byte()? }; // Wait for the STOP to be sent. - while unsafe { T::regs().cr1().read().stop() == i2c::vals::Stop::STOP } {} + while unsafe { T::regs().cr1().read().stop() } {} // Fallthrough is success Ok(()) @@ -246,11 +232,9 @@ impl<'d, T: Instance> I2c<'d, T> { unsafe { self.write_bytes(addr, bytes)?; // Send a STOP condition - T::regs() - .cr1() - .modify(|reg| reg.set_stop(i2c::vals::Stop::STOP)); + T::regs().cr1().modify(|reg| reg.set_stop(true)); // Wait for STOP condition to transmit. - while T::regs().cr1().read().stop() == i2c::vals::Stop::STOP {} + while T::regs().cr1().read().stop() {} }; // Fallthrough is success diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs index 58ab771b..493aacb6 100644 --- a/embassy-stm32/src/i2c/v2.rs +++ b/embassy-stm32/src/i2c/v2.rs @@ -132,7 +132,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> { fn master_stop(&mut self) { unsafe { - T::regs().cr2().write(|w| w.set_stop(i2c::vals::Stop::STOP)); + T::regs().cr2().write(|w| w.set_stop(true)); } } @@ -143,7 +143,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> { // Wait for any previous address sequence to end // automatically. This could be up to 50% of a bus // cycle (ie. up to 0.5/freq) - while T::regs().cr2().read().start() == i2c::vals::Start::START {} + while T::regs().cr2().read().start() {} } // Set START and prepare to receive bytes into @@ -158,10 +158,10 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> { T::regs().cr2().modify(|w| { w.set_sadd((address << 1 | 0) as u16); - w.set_add10(i2c::vals::Add::BIT7); - w.set_rd_wrn(i2c::vals::RdWrn::READ); + w.set_add10(i2c::vals::Addmode::BIT7); + w.set_dir(i2c::vals::Dir::READ); w.set_nbytes(length as u8); - w.set_start(i2c::vals::Start::START); + w.set_start(true); w.set_autoend(stop.autoend()); w.set_reload(reload); }); @@ -173,7 +173,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> { // Wait for any previous address sequence to end // automatically. This could be up to 50% of a bus // cycle (ie. up to 0.5/freq) - while T::regs().cr2().read().start() == i2c::vals::Start::START {} + while T::regs().cr2().read().start() {} let reload = if reload { i2c::vals::Reload::NOTCOMPLETED @@ -186,10 +186,10 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> { // I2C is in slave mode. T::regs().cr2().modify(|w| { w.set_sadd((address << 1 | 0) as u16); - w.set_add10(i2c::vals::Add::BIT7); - w.set_rd_wrn(i2c::vals::RdWrn::WRITE); + w.set_add10(i2c::vals::Addmode::BIT7); + w.set_dir(i2c::vals::Dir::WRITE); w.set_nbytes(length as u8); - w.set_start(i2c::vals::Start::START); + w.set_start(true); w.set_autoend(stop.autoend()); w.set_reload(reload); }); diff --git a/embassy-stm32/src/rcc/f0.rs b/embassy-stm32/src/rcc/f0.rs index 1527afa0..427c958f 100644 --- a/embassy-stm32/src/rcc/f0.rs +++ b/embassy-stm32/src/rcc/f0.rs @@ -1,4 +1,4 @@ -use crate::pac::rcc::vals::{Hpre, Hsebyp, Pllmul, Pllsrc, Ppre, Sw, Usbsw}; +use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Sw, Usbsw}; use crate::pac::{FLASH, RCC}; use crate::time::Hertz; @@ -16,7 +16,7 @@ pub struct Config { pub bypass_hse: bool, pub usb_pll: bool, - #[cfg(rcc_f0)] + #[cfg(not(stm32f0x0))] pub hsi48: bool, pub sys_ck: Option, @@ -28,7 +28,7 @@ pub(crate) unsafe fn init(config: Config) { let sysclk = config.sys_ck.map(|v| v.0).unwrap_or(HSI); let (src_clk, use_hsi48) = config.hse.map(|v| (v.0, false)).unwrap_or_else(|| { - #[cfg(rcc_f0)] + #[cfg(not(stm32f0x0))] if config.hsi48 { return (48_000_000, true); } @@ -97,10 +97,7 @@ pub(crate) unsafe fn init(config: Config) { RCC.cr().modify(|w| { w.set_csson(true); w.set_hseon(true); - - if config.bypass_hse { - w.set_hsebyp(Hsebyp::BYPASSED); - } + w.set_hsebyp(config.bypass_hse); }); while !RCC.cr().read().hserdy() {} @@ -108,14 +105,12 @@ pub(crate) unsafe fn init(config: Config) { RCC.cfgr().modify(|w| w.set_pllsrc(Pllsrc::HSE_DIV_PREDIV)) } } + // use_hsi48 will always be false for stm32f0x0 + #[cfg(not(stm32f0x0))] (false, true) => { - // use_hsi48 will always be false for rcc_f0x0 - #[cfg(rcc_f0)] RCC.cr2().modify(|w| w.set_hsi48on(true)); - #[cfg(rcc_f0)] while !RCC.cr2().read().hsi48rdy() {} - #[cfg(rcc_f0)] if pllmul_bits.is_some() { RCC.cfgr() .modify(|w| w.set_pllsrc(Pllsrc::HSI48_DIV_PREDIV)) @@ -155,7 +150,7 @@ pub(crate) unsafe fn init(config: Config) { if config.hse.is_some() { w.set_sw(Sw::HSE); } else if use_hsi48 { - #[cfg(rcc_f0)] + #[cfg(not(stm32f0x0))] w.set_sw(Sw::HSI48); } else { w.set_sw(Sw::HSI) @@ -169,6 +164,6 @@ pub(crate) unsafe fn init(config: Config) { apb2: Hertz(pclk), apb1_tim: Hertz(pclk * timer_mul), apb2_tim: Hertz(pclk * timer_mul), - ahb: Hertz(hclk), + ahb1: Hertz(hclk), }); } diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs index d44544d2..ca0883b4 100644 --- a/embassy-stm32/src/rcc/f1.rs +++ b/embassy-stm32/src/rcc/f1.rs @@ -173,7 +173,7 @@ pub(crate) unsafe fn init(config: Config) { apb2: Hertz(pclk2), apb1_tim: Hertz(pclk1 * timer_mul1), apb2_tim: Hertz(pclk2 * timer_mul2), - ahb: Hertz(hclk), + ahb1: Hertz(hclk), adc: Hertz(adcclk), }); } diff --git a/embassy-stm32/src/rcc/f3.rs b/embassy-stm32/src/rcc/f3.rs index 2727a5b1..82091531 100644 --- a/embassy-stm32/src/rcc/f3.rs +++ b/embassy-stm32/src/rcc/f3.rs @@ -1,5 +1,5 @@ use crate::pac::flash::vals::Latency; -use crate::pac::rcc::vals::{Hpre, Hsebyp, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre}; +use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre}; use crate::pac::{FLASH, RCC}; use crate::rcc::{set_freqs, Clocks}; use crate::time::Hertz; @@ -106,11 +106,7 @@ pub(crate) unsafe fn init(config: Config) { // Enable HSE if config.hse.is_some() { RCC.cr().write(|w| { - w.set_hsebyp(if config.bypass_hse { - Hsebyp::BYPASSED - } else { - Hsebyp::NOTBYPASSED - }); + w.set_hsebyp(config.bypass_hse); // We turn on clock security to switch to HSI when HSE fails w.set_csson(true); w.set_hseon(true); @@ -164,7 +160,7 @@ pub(crate) unsafe fn init(config: Config) { apb2: Hertz(pclk2), apb1_tim: Hertz(pclk1 * timer_mul1), apb2_tim: Hertz(pclk2 * timer_mul2), - ahb: Hertz(hclk), + ahb1: Hertz(hclk), }); } diff --git a/embassy-stm32/src/rcc/f4.rs b/embassy-stm32/src/rcc/f4.rs index aba8fc0e..22a2e9ad 100644 --- a/embassy-stm32/src/rcc/f4.rs +++ b/embassy-stm32/src/rcc/f4.rs @@ -1,5 +1,5 @@ use super::sealed::RccPeripheral; -use crate::pac::rcc::vals::{Hpre, Hsebyp, Ppre, Sw}; +use crate::pac::rcc::vals::{Hpre, Ppre, Sw}; use crate::pac::{FLASH, PWR, RCC}; use crate::rcc::{set_freqs, Clocks}; use crate::time::Hertz; @@ -200,7 +200,7 @@ pub(crate) unsafe fn init(config: Config) { if config.hse.is_some() { RCC.cr().modify(|w| { - w.set_hsebyp(Hsebyp(config.bypass_hse as u8)); + w.set_hsebyp(config.bypass_hse); w.set_hseon(true); }); while !RCC.cr().read().hserdy() {} diff --git a/embassy-stm32/src/rcc/f7.rs b/embassy-stm32/src/rcc/f7.rs index 1a053029..9f2c63c1 100644 --- a/embassy-stm32/src/rcc/f7.rs +++ b/embassy-stm32/src/rcc/f7.rs @@ -1,6 +1,6 @@ use super::sealed::RccPeripheral; use crate::pac::pwr::vals::Vos; -use crate::pac::rcc::vals::{Hpre, Hsebyp, Ppre, Sw}; +use crate::pac::rcc::vals::{Hpre, Ppre, Sw}; use crate::pac::{FLASH, PWR, RCC}; use crate::rcc::{set_freqs, Clocks}; use crate::time::Hertz; @@ -213,7 +213,7 @@ pub(crate) unsafe fn init(config: Config) { if config.hse.is_some() { RCC.cr().modify(|w| { - w.set_hsebyp(Hsebyp(config.bypass_hse as u8)); + w.set_hsebyp(config.bypass_hse); w.set_hseon(true); }); while !RCC.cr().read().hserdy() {} diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs index a3a4c197..71d44fd3 100644 --- a/embassy-stm32/src/rcc/g0.rs +++ b/embassy-stm32/src/rcc/g0.rs @@ -176,8 +176,8 @@ pub(crate) unsafe fn init(config: Config) { set_freqs(Clocks { sys: sys_clk.hz(), - ahb: ahb_freq.hz(), - apb: apb_freq.hz(), - apb_tim: apb_tim_freq.hz(), + ahb1: ahb_freq.hz(), + apb1: apb_freq.hz(), + apb1_tim: apb_tim_freq.hz(), }); } diff --git a/embassy-stm32/src/rcc/h7.rs b/embassy-stm32/src/rcc/h7.rs index 23c91636..1b2c595b 100644 --- a/embassy-stm32/src/rcc/h7.rs +++ b/embassy-stm32/src/rcc/h7.rs @@ -7,7 +7,7 @@ use stm32_metapac::rcc::vals::{Mco1, Mco2}; use crate::gpio::sealed::AFType; use crate::gpio::Speed; use crate::pac::rcc::vals::Timpre; -use crate::pac::rcc::vals::{Ckpersel, Dppre, Hpre, Hsebyp, Hsidiv, Pllsrc, Sw}; +use crate::pac::rcc::vals::{Ckpersel, Dppre, Hpre, Hsidiv, Pllsrc, Sw}; use crate::pac::{PWR, RCC, SYSCFG}; use crate::peripherals; use crate::rcc::{set_freqs, Clocks}; @@ -569,11 +569,7 @@ pub(crate) unsafe fn init(mut config: Config) { // Ensure HSE is on and stable RCC.cr().modify(|w| { w.set_hseon(true); - w.set_hsebyp(if config.bypass_hse { - Hsebyp::BYPASSED - } else { - Hsebyp::NOTBYPASSED - }); + w.set_hsebyp(config.bypass_hse); }); while !RCC.cr().read().hserdy() {} Some(hse) diff --git a/embassy-stm32/src/rcc/l0.rs b/embassy-stm32/src/rcc/l0.rs index 25daeedf..e482dcc2 100644 --- a/embassy-stm32/src/rcc/l0.rs +++ b/embassy-stm32/src/rcc/l0.rs @@ -353,7 +353,7 @@ pub(crate) unsafe fn init(config: Config) { set_freqs(Clocks { sys: sys_clk.hz(), - ahb: ahb_freq.hz(), + ahb1: ahb_freq.hz(), apb1: apb1_freq.hz(), apb2: apb2_freq.hz(), apb1_tim: apb1_tim_freq.hz(), diff --git a/embassy-stm32/src/rcc/l1.rs b/embassy-stm32/src/rcc/l1.rs index 904e6ab5..dfcbd4f2 100644 --- a/embassy-stm32/src/rcc/l1.rs +++ b/embassy-stm32/src/rcc/l1.rs @@ -319,7 +319,7 @@ pub(crate) unsafe fn init(config: Config) { set_freqs(Clocks { sys: sys_clk.hz(), - ahb: ahb_freq.hz(), + ahb1: ahb_freq.hz(), apb1: apb1_freq.hz(), apb2: apb2_freq.hz(), apb1_tim: apb1_tim_freq.hz(), diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs index 3aab01af..5c223bc4 100644 --- a/embassy-stm32/src/rcc/mod.rs +++ b/embassy-stm32/src/rcc/mod.rs @@ -3,7 +3,7 @@ use crate::time::Hertz; use core::mem::MaybeUninit; -#[cfg_attr(any(rcc_f0, rcc_f0x0), path = "f0.rs")] +#[cfg_attr(rcc_f0, path = "f0.rs")] #[cfg_attr(rcc_f1, path = "f1.rs")] #[cfg_attr(rcc_f3, path = "f3.rs")] #[cfg_attr(any(rcc_f4, rcc_f410), path = "f4.rs")] @@ -24,46 +24,29 @@ pub use _version::*; pub struct Clocks { pub sys: Hertz, - #[cfg(rcc_g0)] - pub apb: Hertz, - #[cfg(rcc_g0)] - pub apb_tim: Hertz, - - #[cfg(not(rcc_g0))] + // APB pub apb1: Hertz, - #[cfg(not(rcc_g0))] pub apb1_tim: Hertz, - #[cfg(not(rcc_g0))] pub apb2: Hertz, #[cfg(not(rcc_g0))] pub apb2_tim: Hertz, - #[cfg(any(rcc_wl5, rcc_u5))] pub apb3: Hertz, + #[cfg(any(rcc_h7))] + pub apb4: Hertz, - #[cfg(any(rcc_l0, rcc_l1, rcc_f0, rcc_f1, rcc_f3, rcc_f0x0, rcc_g0))] - pub ahb: Hertz, - - #[cfg(any( - rcc_l4, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_g4, rcc_u5, rcc_wb, rcc_wl5 - ))] + // AHB pub ahb1: Hertz, - #[cfg(any( rcc_l4, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_g4, rcc_u5, rcc_wb, rcc_wl5 ))] pub ahb2: Hertz, - #[cfg(any(rcc_l4, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_u5, rcc_wb, rcc_wl5))] pub ahb3: Hertz, - #[cfg(any(rcc_h7))] pub ahb4: Hertz, - #[cfg(any(rcc_h7))] - pub apb4: Hertz, - #[cfg(any(rcc_f4, rcc_f410, rcc_f7))] pub pll48: Option, diff --git a/stm32-data b/stm32-data index b665a729..dbb0ad74 160000 --- a/stm32-data +++ b/stm32-data @@ -1 +1 @@ -Subproject commit b665a729227a4cdabad58e728f7d4c6a94454b7a +Subproject commit dbb0ad74f2a4612f0ca168da38e1c443a838a607