Fix dma
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parent
9ff5c50774
commit
efe456ab14
@ -40,14 +40,14 @@ pub(crate) unsafe fn init() {
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pub unsafe fn read<'a, C: Channel, W: Word>(
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ch: impl Peripheral<P = C> + 'a,
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from: *const W,
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to: *mut W,
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len: usize,
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to: *mut [W],
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dreq: u8,
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) -> Transfer<'a, C> {
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let (to_ptr, len) = crate::dma::slice_ptr_parts(to);
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copy_inner(
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ch,
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from as *const u32,
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to as *mut u32,
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to_ptr as *mut u32,
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len,
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W::size(),
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false,
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@ -58,14 +58,14 @@ pub unsafe fn read<'a, C: Channel, W: Word>(
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pub unsafe fn write<'a, C: Channel, W: Word>(
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ch: impl Peripheral<P = C> + 'a,
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from: *const W,
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from: *const [W],
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to: *mut W,
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len: usize,
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dreq: u8,
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) -> Transfer<'a, C> {
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let (from_ptr, len) = crate::dma::slice_ptr_parts(from);
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copy_inner(
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ch,
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from as *const u32,
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from_ptr as *const u32,
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to as *mut u32,
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len,
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W::size(),
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@ -325,7 +325,6 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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}
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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let (from_ptr, len) = crate::dma::slice_ptr_parts(buffer);
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let ch = self.tx_dma.as_mut().unwrap();
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let transfer = unsafe {
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self.inner.regs().dmacr().modify(|reg| {
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@ -333,20 +332,13 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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});
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::write(
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ch,
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from_ptr as *const u32,
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self.inner.regs().dr().ptr() as *mut _,
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len,
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T::TX_DREQ,
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)
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crate::dma::write(ch, buffer, self.inner.regs().dr().ptr() as *mut _, T::TX_DREQ)
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};
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transfer.await;
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Ok(())
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}
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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let (to_ptr, len) = crate::dma::slice_ptr_parts_mut(buffer);
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let ch = self.rx_dma.as_mut().unwrap();
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let transfer = unsafe {
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self.inner.regs().dmacr().modify(|reg| {
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@ -354,13 +346,7 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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});
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(
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ch,
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self.inner.regs().dr().ptr() as *const _,
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to_ptr as *mut u32,
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len,
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T::RX_DREQ,
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)
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crate::dma::read(ch, self.inner.regs().dr().ptr() as *const _, buffer, T::RX_DREQ)
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};
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transfer.await;
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Ok(())
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@ -375,8 +361,8 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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}
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async fn transfer_inner(&mut self, rx_ptr: *mut [u8], tx_ptr: *const [u8]) -> Result<(), Error> {
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let (from_ptr, from_len) = crate::dma::slice_ptr_parts(tx_ptr);
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let (to_ptr, to_len) = crate::dma::slice_ptr_parts_mut(rx_ptr);
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let (_, from_len) = crate::dma::slice_ptr_parts(tx_ptr);
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let (_, to_len) = crate::dma::slice_ptr_parts_mut(rx_ptr);
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assert_eq!(from_len, to_len);
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let tx_ch = self.tx_dma.as_mut().unwrap();
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let tx_transfer = unsafe {
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@ -385,13 +371,7 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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});
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::write(
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tx_ch,
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from_ptr as *const u32,
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self.inner.regs().dr().ptr() as *mut _,
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from_len,
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T::TX_DREQ,
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)
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crate::dma::write(tx_ch, tx_ptr, self.inner.regs().dr().ptr() as *mut _, T::TX_DREQ)
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};
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let rx_ch = self.rx_dma.as_mut().unwrap();
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let rx_transfer = unsafe {
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@ -400,13 +380,7 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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});
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(
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rx_ch,
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self.inner.regs().dr().ptr() as *const _,
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to_ptr as *mut u32,
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to_len,
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T::RX_DREQ,
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)
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crate::dma::read(rx_ch, self.inner.regs().dr().ptr() as *const _, rx_ptr, T::RX_DREQ)
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};
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join(tx_transfer, rx_transfer).await;
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Ok(())
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@ -120,7 +120,6 @@ impl<'d, T: Instance, M: Mode> UartTx<'d, T, M> {
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impl<'d, T: Instance> UartTx<'d, T, Async> {
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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let (from_ptr, len) = crate::dma::slice_ptr_parts(buffer);
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let ch = self.tx_dma.as_mut().unwrap();
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let transfer = unsafe {
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T::regs().uartdmacr().modify(|reg| {
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@ -128,13 +127,7 @@ impl<'d, T: Instance> UartTx<'d, T, Async> {
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});
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::write(
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ch,
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from_ptr as *const u32,
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T::regs().uartdr().ptr() as *mut _,
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len,
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T::TX_DREQ,
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)
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crate::dma::write(ch, buffer, T::regs().uartdr().ptr() as *mut _, T::TX_DREQ)
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};
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transfer.await;
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Ok(())
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@ -180,7 +173,6 @@ impl<'d, T: Instance, M: Mode> UartRx<'d, T, M> {
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impl<'d, T: Instance> UartRx<'d, T, Async> {
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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let (to_ptr, len) = crate::dma::slice_ptr_parts_mut(buffer);
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let ch = self.rx_dma.as_mut().unwrap();
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let transfer = unsafe {
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T::regs().uartdmacr().modify(|reg| {
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@ -188,13 +180,7 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
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});
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(
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ch,
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T::regs().uartdr().ptr() as *const _,
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to_ptr as *mut u32,
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len,
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T::RX_DREQ,
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)
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crate::dma::read(ch, T::regs().uartdr().ptr() as *const _, buffer, T::RX_DREQ)
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};
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transfer.await;
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Ok(())
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