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Mix dmamux into bdma_v1.

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This commit is contained in:
Bob McWhirter
2021-07-08 14:55:27 -04:00
parent 6ec7253095
commit f01ddd5f5c
11 changed files with 245 additions and 256 deletions
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216
embassy-stm32/src/dmamux/mod.rs
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@ -20,41 +20,11 @@ use crate::peripherals;
use core::future::Future;
use crate::dma::{ReadDma, WriteDma};
use crate::dma_traits::{ReadDma, WriteDma};
const CH_COUNT: usize = peripheral_count!(DMA) * 8;
const CH_STATUS_NONE: u8 = 0;
const CH_STATUS_COMPLETED: u8 = 1;
const CH_STATUS_ERROR: u8 = 2;
struct State {
ch_wakers: [AtomicWaker; CH_COUNT],
ch_status: [AtomicU8; CH_COUNT],
}
impl State {
const fn new() -> Self {
const AW: AtomicWaker = AtomicWaker::new();
const AU: AtomicU8 = AtomicU8::new(CH_STATUS_NONE);
Self {
ch_wakers: [AW; CH_COUNT],
ch_status: [AU; CH_COUNT],
}
}
}
static STATE: State = State::new();
#[allow(unused)]
pub(crate) async unsafe fn transfer_p2m(
ch: &mut impl Channel,
ch_func: u8,
src: *const u8,
dst: &mut [u8],
) {
unimplemented!()
}
pub(crate) fn configure_channel(ch_num: u8, request_num: u8) {}
/*
#[allow(unused)]
pub(crate) async unsafe fn transfer_m2p(
ch: &mut impl Channel,
@ -128,22 +98,36 @@ pub(crate) async unsafe fn transfer_m2p(
// TODO handle error
assert!(res == CH_STATUS_COMPLETED);
}
*/
pub(crate) unsafe fn configure_dmamux(
dmamux_regs: &pac::dmamux::Dmamux,
dmamux_ch_num: u8,
request: u8,
) {
let ch_mux_regs = dmamux_regs.ccr(dmamux_ch_num as _);
ch_mux_regs.write(|reg| {
// one request?
reg.set_nbreq(0);
reg.set_dmareq_id(request);
});
ch_mux_regs.modify(|reg| {
reg.set_ege(true);
//reg.set_se(true);
//reg.set_soie(true);
});
}
pub(crate) mod sealed {
use super::*;
pub trait Bdma {
fn regs() -> &'static pac::bdma::Dma;
fn num() -> u8;
}
pub trait DmaMux {
fn regs() -> &'static pac::dmamux::Dmamux;
}
pub trait Channel {
fn num(&self) -> usize;
fn regs(&self) -> pac::bdma::Ch;
fn dma_regs() -> &'static pac::bdma::Dma;
fn dma_ch_num(&self) -> u8;
@ -156,7 +140,6 @@ pub(crate) mod sealed {
}
}
pub trait Bdma: sealed::Bdma {}
pub trait DmaMux: sealed::DmaMux {}
pub trait Channel: sealed::Channel {}
pub trait PeripheralChannel<PERI, OP>: sealed::Channel {}
@ -172,10 +155,6 @@ macro_rules! impl_dma_channel {
($dma_num * 8) + $channel_num
}
fn regs(&self) -> pac::bdma::Ch {
Self::dma_regs().ch(self.dma_ch_num() as _)
}
fn dma_regs() -> &'static pac::bdma::Dma {
&crate::pac::$dma_peri
}
@ -192,42 +171,6 @@ macro_rules! impl_dma_channel {
($dma_num * 8) + $channel_num
}
}
impl<T> WriteDma<T> for peripherals::$channel_peri
where
Self: sealed::PeripheralChannel<T, M2P>,
T: 'static,
{
type WriteDmaFuture<'a> = impl Future<Output = ()>;
fn transfer<'a>(&'a mut self, buf: &'a [u8], dst: *mut u8) -> Self::WriteDmaFuture<'a>
where
T: 'a,
{
let request = sealed::PeripheralChannel::<T, M2P>::request(self);
unsafe { transfer_m2p(self, request, buf, dst) }
}
}
impl<T> ReadDma<T> for peripherals::$channel_peri
where
Self: sealed::PeripheralChannel<T, P2M>,
T: 'static,
{
type ReadDmaFuture<'a> = impl Future<Output = ()>;
fn transfer<'a>(
&'a mut self,
src: *const u8,
buf: &'a mut [u8],
) -> Self::ReadDmaFuture<'a>
where
T: 'a,
{
let request = sealed::PeripheralChannel::<T, P2M>::request(self);
unsafe { transfer_p2m(self, request, src, buf) }
}
}
};
}
@ -242,25 +185,8 @@ macro_rules! impl_dmamux {
};
}
macro_rules! impl_bdma {
($peri:ident, $dma_num:expr) => {
impl sealed::Bdma for peripherals::$peri {
fn num() -> u8 {
$dma_num
}
fn regs() -> &'static pac::bdma::Dma {
&pac::$peri
}
}
impl Bdma for peripherals::$peri {}
};
}
peripherals! {
(bdma, DMA1) => {
impl_bdma!(DMA1, 0);
dma_channels! {
($channel_peri:ident, DMA1, $channel_num:expr) => {
impl_dma_channel!($channel_peri, DMAMUX1, $channel_num, DMA1, 0);
@ -268,7 +194,6 @@ peripherals! {
}
};
(bdma, DMA2) => {
impl_bdma!(DMA2, 1);
dma_channels! {
($channel_peri:ident, DMA2, $channel_num:expr) => {
impl_dma_channel!($channel_peri, DMAMUX1, $channel_num, DMA2, 1);
@ -285,9 +210,6 @@ macro_rules! impl_usart_dma_requests {
dma_requests! {
// TODO: DRY this up.
(usart, $peri:ident, RX, $request:expr) => {
impl usart::RxDma<peripherals::$peri> for peripherals::$channel_peri { }
impl usart::sealed::RxDma<peripherals::$peri> for peripherals::$channel_peri { }
impl sealed::PeripheralChannel<peripherals::$peri, P2M> for peripherals::$channel_peri {
fn request(&self) -> u8 {
$request
@ -299,9 +221,6 @@ macro_rules! impl_usart_dma_requests {
};
(usart, $peri:ident, TX, $request:expr) => {
impl usart::TxDma<peripherals::$peri> for peripherals::$channel_peri { }
impl usart::sealed::TxDma<peripherals::$peri> for peripherals::$channel_peri { }
impl sealed::PeripheralChannel<peripherals::$peri, M2P> for peripherals::$channel_peri {
fn request(&self) -> u8 {
$request
@ -313,9 +232,6 @@ macro_rules! impl_usart_dma_requests {
};
(uart, $peri:ident, TX, $request:expr) => {
impl usart::RxDma<peripherals::$peri> for peripherals::$channel_peri { }
impl usart::sealed::RxDma<peripherals::$peri> for peripherals::$channel_peri { }
impl sealed::PeripheralChannel<peripherals::$peri, P2M> for peripherals::$channel_peri {
fn request(&self) -> u8 {
$request
@ -326,9 +242,6 @@ macro_rules! impl_usart_dma_requests {
};
(uart, $peri:ident, RX, $request:expr) => {
impl usart::TxDma<peripherals::$peri> for peripherals::$channel_peri { }
impl usart::sealed::TxDma<peripherals::$peri> for peripherals::$channel_peri { }
impl sealed::PeripheralChannel<peripherals::$peri, M2P> for peripherals::$channel_peri {
fn request(&self) -> u8 {
$request
@ -351,86 +264,5 @@ dma_channels! {
};
}
unsafe fn on_irq() {
defmt::info!("irq fire");
peripherals! {
//(bdma, $dma:ident) => {
(bdma, DMA1) => {
defmt::info!("---> dma DMA1");
//for isrn in 0..2 {
//let isr = pac::$dma.isr(isrn).read();
let isr = pac::DMA1.isr().read();
pac::DMA1.ifcr().write_value(isr);
let dman = <peripherals::DMA1 as sealed::Bdma>::num() as usize;
for chn in 0..8 {
let n = dman * 8 + chn;
defmt::info!("n={}", n);
if isr.teif(chn) {
defmt::info!("transfer error");
STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Release);
STATE.ch_wakers[n].wake();
} else if isr.tcif(chn) {
defmt::info!("transfer complete");
STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Release);
STATE.ch_wakers[n].wake();
} else if isr.htif(chn) {
defmt::info!("half transfer");
} else if isr.gif(chn) {
defmt::info!("half transfer");
}
}
//}
};
(bdma, DMA2) => {
defmt::info!("---> dma DMA2");
//for isrn in 0..2 {
//let isr = pac::$dma.isr(isrn).read();
let isr = pac::DMA2.isr().read();
pac::DMA2.ifcr().write_value(isr);
let dman = <peripherals::DMA2 as sealed::Bdma>::num() as usize;
for chn in 0..8 {
let n = dman * 8 + chn;
defmt::info!("n={}", n);
if isr.teif(chn) {
defmt::info!("transfer error");
STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Release);
STATE.ch_wakers[n].wake();
} else if isr.tcif(chn) {
defmt::info!("transfer complete");
STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Release);
STATE.ch_wakers[n].wake();
} else if isr.htif(chn) {
defmt::info!("half transfer");
} else if isr.gif(chn) {
defmt::info!("half transfer");
}
}
//}
};
}
defmt::info!("irq fire complete");
}
/// safety: must be called only once
pub(crate) unsafe fn init() {
interrupts! {
(DMA, $irq:ident) => {
defmt::info!("enable irq {}", stringify!($irq));
interrupt::$irq::steal().enable();
};
}
}
interrupts! {
(DMA, $irq:ident) => {
#[crate::interrupt]
unsafe fn $irq () {
defmt::info!("irq firing {}", stringify!($irq));
on_irq()
}
};
}
pub(crate) unsafe fn init() {}