From d052631118d8cc998696cf353a5ae7f5b28bbd69 Mon Sep 17 00:00:00 2001
From: chemicstry <chemicstry@gmail.com>
Date: Wed, 30 Mar 2022 00:27:33 +0300
Subject: [PATCH] Fix STM32 timer interrupt bug

---
 embassy-stm32/src/time_driver.rs | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/embassy-stm32/src/time_driver.rs b/embassy-stm32/src/time_driver.rs
index 5b3efca7..d936a11a 100644
--- a/embassy-stm32/src/time_driver.rs
+++ b/embassy-stm32/src/time_driver.rs
@@ -172,8 +172,11 @@ impl RtcDriver {
             // Mid-way point
             r.ccr(0).write(|w| w.set_ccr(0x8000));
 
-            // Enable CC0, disable others
-            r.dier().write(|w| w.set_ccie(0, true));
+            // Enable overflow and half-overflow interrupts
+            r.dier().write(|w| {
+                w.set_uie(true);
+                w.set_ccie(0, true);
+            });
 
             let irq: <T as BasicInstance>::Interrupt = core::mem::transmute(());
             irq.unpend();
@@ -197,6 +200,7 @@ impl RtcDriver {
             // miss interrupts.
             r.sr().write_value(regs::SrGp(!sr.0));
 
+            // Overflow
             if sr.uif() {
                 self.next_period();
             }