From f0ab9900580b18ae8e76fc6a7b7b053aa80d1f89 Mon Sep 17 00:00:00 2001
From: Brandon Ros <brandonros1@gmail.com>
Date: Tue, 22 Aug 2023 18:30:21 -0400
Subject: [PATCH] debug! over defmt::debug!

---
 cyw43/src/bus.rs | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/cyw43/src/bus.rs b/cyw43/src/bus.rs
index abe0f2cb..fdc1db58 100644
--- a/cyw43/src/bus.rs
+++ b/cyw43/src/bus.rs
@@ -50,13 +50,13 @@ where
 
     pub async fn init(&mut self) {
         // Reset
-        defmt::debug!("WL_REG off/on");
+        debug!("WL_REG off/on");
         self.pwr.set_low().unwrap();
         Timer::after(Duration::from_millis(20)).await;
         self.pwr.set_high().unwrap();
         Timer::after(Duration::from_millis(250)).await;
 
-        defmt::debug!("read REG_BUS_TEST_RO");
+        debug!("read REG_BUS_TEST_RO");
         while self
             .read32_swapped(FUNC_BUS, REG_BUS_TEST_RO)
             .inspect(|v| trace!("{:#x}", v))
@@ -64,19 +64,19 @@ where
             != FEEDBEAD
         {}
 
-        defmt::debug!("write REG_BUS_TEST_RW");
+        debug!("write REG_BUS_TEST_RW");
         self.write32_swapped(FUNC_BUS, REG_BUS_TEST_RW, TEST_PATTERN).await;
         let val = self.read32_swapped(FUNC_BUS, REG_BUS_TEST_RW).await;
         trace!("{:#x}", val);
         assert_eq!(val, TEST_PATTERN);
 
-        defmt::debug!("read REG_BUS_CTRL");
+        debug!("read REG_BUS_CTRL");
         let val = self.read32_swapped(FUNC_BUS, REG_BUS_CTRL).await;
         trace!("{:#010b}", (val & 0xff));
 
         // 32-bit word length, little endian (which is the default endianess).
         // TODO: C library is uint32_t val = WORD_LENGTH_32 | HIGH_SPEED_MODE| ENDIAN_BIG | INTERRUPT_POLARITY_HIGH | WAKE_UP | 0x4 << (8 * SPI_RESPONSE_DELAY) | INTR_WITH_STATUS << (8 * SPI_STATUS_ENABLE);
-        defmt::debug!("write REG_BUS_CTRL");
+        debug!("write REG_BUS_CTRL");
         self.write32_swapped(
             FUNC_BUS,
             REG_BUS_CTRL,
@@ -89,29 +89,29 @@ where
         )
         .await;
 
-        defmt::debug!("read REG_BUS_CTRL");
+        debug!("read REG_BUS_CTRL");
         let val = self.read8(FUNC_BUS, REG_BUS_CTRL).await;
         trace!("{:#b}", val);
 
         // TODO: C doesn't do this? i doubt it messes anything up
-        defmt::debug!("read REG_BUS_TEST_RO");
+        debug!("read REG_BUS_TEST_RO");
         let val = self.read32(FUNC_BUS, REG_BUS_TEST_RO).await;
         trace!("{:#x}", val);
         assert_eq!(val, FEEDBEAD);
 
         // TODO: C doesn't do this? i doubt it messes anything up
-        defmt::debug!("read REG_BUS_TEST_RW");
+        debug!("read REG_BUS_TEST_RW");
         let val = self.read32(FUNC_BUS, REG_BUS_TEST_RW).await;
         trace!("{:#x}", val);
         assert_eq!(val, TEST_PATTERN);
 
-        defmt::debug!("write SPI_RESP_DELAY_F1 CYW43_BACKPLANE_READ_PAD_LEN_BYTES");
+        debug!("write SPI_RESP_DELAY_F1 CYW43_BACKPLANE_READ_PAD_LEN_BYTES");
         self.write8(FUNC_BUS, SPI_RESP_DELAY_F1, WHD_BUS_SPI_BACKPLANE_READ_PADD_SIZE)
             .await;
 
         // TODO: Make sure error interrupt bits are clear?
         // cyw43_write_reg_u8(self, BUS_FUNCTION, SPI_INTERRUPT_REGISTER, DATA_UNAVAILABLE | COMMAND_ERROR | DATA_ERROR | F1_OVERFLOW) != 0)
-        defmt::debug!("Make sure error interrupt bits are clear");
+        debug!("Make sure error interrupt bits are clear");
         self.write8(
             FUNC_BUS,
             REG_BUS_INTERRUPT,
@@ -121,7 +121,7 @@ where
 
         // Enable a selection of interrupts
         // TODO: why not all of these F2_F3_FIFO_RD_UNDERFLOW | F2_F3_FIFO_WR_OVERFLOW | COMMAND_ERROR | DATA_ERROR | F2_PACKET_AVAILABLE | F1_OVERFLOW | F1_INTR
-        defmt::debug!("enable a selection of interrupts");
+        debug!("enable a selection of interrupts");
         self.write16(
             FUNC_BUS,
             REG_BUS_INTERRUPT_ENABLE,
@@ -244,7 +244,7 @@ where
     }
 
     async fn backplane_readn(&mut self, addr: u32, len: u32) -> u32 {
-        defmt::debug!("backplane_readn addr = {:08x} len = {}", addr, len);
+        debug!("backplane_readn addr = {:08x} len = {}", addr, len);
 
         self.backplane_set_window(addr).await;
 
@@ -255,7 +255,7 @@ where
         
         let val = self.readn(FUNC_BACKPLANE, bus_addr, len).await;
 
-        defmt::debug!("backplane_readn addr = {:08x} len = {} val = {:08x}", addr, len, val);
+        debug!("backplane_readn addr = {:08x} len = {} val = {:08x}", addr, len, val);
 
         self.backplane_set_window(0x18000000).await; // CHIPCOMMON_BASE_ADDRESS
 
@@ -263,7 +263,7 @@ where
     }
 
     async fn backplane_writen(&mut self, addr: u32, val: u32, len: u32) {
-        defmt::debug!("backplane_writen addr = {:08x} len = {} val = {:08x}", addr, len, val);
+        debug!("backplane_writen addr = {:08x} len = {} val = {:08x}", addr, len, val);
 
         self.backplane_set_window(addr).await;
 
@@ -345,7 +345,7 @@ where
 
         self.status = self.spi.cmd_read(cmd, &mut buf[..len]).await;
 
-        defmt::debug!("readn cmd = {:08x} addr = {:08x} len = {} buf = {:08x}", cmd, addr, len, buf);
+        debug!("readn cmd = {:08x} addr = {:08x} len = {} buf = {:08x}", cmd, addr, len, buf);
 
         // if we read from the backplane, the result is in the second word, after the response delay
         if func == FUNC_BACKPLANE {