Use const REGS
This commit is contained in:
Grant Miller
parent
482ffea4dd
commit
f0b62bc8e0
@ -10,6 +10,7 @@ use self::sealed::WordSize;
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use crate::dma::{slice_ptr_parts, slice_ptr_parts_mut, NoDma, Transfer};
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use crate::gpio::sealed::{AFType, Pin as _};
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use crate::gpio::AnyPin;
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use crate::pac::spi::Spi as Regs;
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use crate::pac::spi::{regs, vals};
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use crate::peripherals;
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use crate::rcc::RccPeripheral;
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@ -17,8 +18,6 @@ use crate::time::Hertz;
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pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
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type Regs = &'static crate::pac::spi::Spi;
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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@ -219,10 +218,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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#[cfg(any(spi_v1, spi_f1))]
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unsafe {
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T::regs().cr2().modify(|w| {
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T::REGS.cr2().modify(|w| {
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w.set_ssoe(false);
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});
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T::regs().cr1().modify(|w| {
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T::REGS.cr1().modify(|w| {
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w.set_cpha(cpha);
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w.set_cpol(cpol);
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@ -242,12 +241,12 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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}
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#[cfg(spi_v2)]
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unsafe {
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T::regs().cr2().modify(|w| {
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T::REGS.cr2().modify(|w| {
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w.set_frxth(WordSize::EightBit.frxth());
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w.set_ds(WordSize::EightBit.ds());
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w.set_ssoe(false);
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});
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T::regs().cr1().modify(|w| {
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T::REGS.cr1().modify(|w| {
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w.set_cpha(cpha);
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w.set_cpol(cpol);
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@ -263,8 +262,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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}
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#[cfg(spi_v3)]
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unsafe {
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T::regs().ifcr().write(|w| w.0 = 0xffff_ffff);
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T::regs().cfg2().modify(|w| {
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T::REGS.ifcr().write(|w| w.0 = 0xffff_ffff);
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T::REGS.cfg2().modify(|w| {
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//w.set_ssoe(true);
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w.set_ssoe(false);
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w.set_cpha(cpha);
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@ -279,16 +278,16 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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w.set_afcntr(vals::Afcntr::CONTROLLED);
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w.set_ssiop(vals::Ssiop::ACTIVEHIGH);
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});
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T::regs().cfg1().modify(|w| {
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T::REGS.cfg1().modify(|w| {
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w.set_crcen(false);
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w.set_mbr(br);
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w.set_dsize(WordSize::EightBit.dsize());
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});
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T::regs().cr2().modify(|w| {
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T::REGS.cr2().modify(|w| {
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w.set_tsize(0);
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w.set_tser(0);
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});
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T::regs().cr1().modify(|w| {
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T::REGS.cr1().modify(|w| {
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w.set_ssi(false);
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w.set_spe(true);
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});
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@ -314,7 +313,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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#[cfg(any(spi_v1, spi_f1, spi_v2))]
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unsafe {
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T::regs().cr1().modify(|w| {
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T::REGS.cr1().modify(|w| {
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w.set_cpha(cpha);
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w.set_cpol(cpol);
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w.set_lsbfirst(lsbfirst);
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@ -323,7 +322,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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#[cfg(spi_v3)]
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unsafe {
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T::regs().cfg2().modify(|w| {
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T::REGS.cfg2().modify(|w| {
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w.set_cpha(cpha);
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w.set_cpol(cpol);
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w.set_lsbfirst(lsbfirst);
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@ -333,9 +332,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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pub fn get_current_config(&self) -> Config {
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#[cfg(any(spi_v1, spi_f1, spi_v2))]
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let cfg = unsafe { T::regs().cr1().read() };
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let cfg = unsafe { T::REGS.cr1().read() };
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#[cfg(spi_v3)]
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let cfg = unsafe { T::regs().cfg2().read() };
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let cfg = unsafe { T::REGS.cfg2().read() };
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let polarity = if cfg.cpol() == vals::Cpol::IDLELOW {
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Polarity::IdleLow
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} else {
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@ -366,40 +365,40 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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#[cfg(any(spi_v1, spi_f1))]
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unsafe {
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T::regs().cr1().modify(|reg| {
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T::REGS.cr1().modify(|reg| {
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reg.set_spe(false);
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reg.set_dff(word_size.dff())
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});
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T::regs().cr1().modify(|reg| {
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T::REGS.cr1().modify(|reg| {
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reg.set_spe(true);
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});
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}
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#[cfg(spi_v2)]
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unsafe {
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T::regs().cr1().modify(|w| {
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T::REGS.cr1().modify(|w| {
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w.set_spe(false);
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});
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T::regs().cr2().modify(|w| {
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T::REGS.cr2().modify(|w| {
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w.set_frxth(word_size.frxth());
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w.set_ds(word_size.ds());
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});
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T::regs().cr1().modify(|w| {
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T::REGS.cr1().modify(|w| {
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w.set_spe(true);
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});
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}
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#[cfg(spi_v3)]
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unsafe {
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T::regs().cr1().modify(|w| {
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T::REGS.cr1().modify(|w| {
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w.set_csusp(true);
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});
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while T::regs().sr().read().eot() {}
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T::regs().cr1().modify(|w| {
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while T::REGS.sr().read().eot() {}
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T::REGS.cr1().modify(|w| {
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w.set_spe(false);
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});
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T::regs().cfg1().modify(|w| {
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T::REGS.cfg1().modify(|w| {
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w.set_dsize(word_size.dsize());
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});
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T::regs().cr1().modify(|w| {
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T::REGS.cr1().modify(|w| {
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w.set_csusp(false);
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w.set_spe(true);
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});
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@ -414,34 +413,34 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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{
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self.set_word_size(WordSize::EightBit);
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unsafe {
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T::regs().cr1().modify(|w| {
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T::REGS.cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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// TODO: This is unnecessary in some versions because
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// clearing SPE automatically clears the fifos
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flush_rx_fifo(T::regs());
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flush_rx_fifo(T::REGS);
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let tx_request = self.txdma.request();
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let tx_dst = T::regs().tx_ptr();
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let tx_dst = T::REGS.tx_ptr();
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unsafe { self.txdma.start_write(tx_request, data, tx_dst) }
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let tx_f = Transfer::new(&mut self.txdma);
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unsafe {
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set_txdmaen(T::regs(), true);
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T::regs().cr1().modify(|w| {
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set_txdmaen(T::REGS, true);
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T::REGS.cr1().modify(|w| {
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w.set_spe(true);
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});
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#[cfg(spi_v3)]
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T::regs().cr1().modify(|w| {
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T::REGS.cr1().modify(|w| {
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w.set_cstart(true);
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});
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}
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tx_f.await;
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finish_dma(T::regs());
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finish_dma(T::REGS);
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Ok(())
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}
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@ -453,21 +452,21 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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{
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self.set_word_size(WordSize::EightBit);
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unsafe {
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T::regs().cr1().modify(|w| {
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T::REGS.cr1().modify(|w| {
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w.set_spe(false);
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});
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set_rxdmaen(T::regs(), true);
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set_rxdmaen(T::REGS, true);
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}
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let (_, clock_byte_count) = slice_ptr_parts_mut(data);
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let rx_request = self.rxdma.request();
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let rx_src = T::regs().rx_ptr();
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let rx_src = T::REGS.rx_ptr();
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unsafe { self.rxdma.start_read(rx_request, rx_src, data) };
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let rx_f = Transfer::new(&mut self.rxdma);
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let tx_request = self.txdma.request();
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let tx_dst = T::regs().tx_ptr();
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let tx_dst = T::REGS.tx_ptr();
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let clock_byte = 0x00u8;
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let tx_f = crate::dma::write_repeated(
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&mut self.txdma,
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@ -478,19 +477,19 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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);
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unsafe {
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set_txdmaen(T::regs(), true);
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T::regs().cr1().modify(|w| {
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set_txdmaen(T::REGS, true);
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T::REGS.cr1().modify(|w| {
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w.set_spe(true);
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});
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#[cfg(spi_v3)]
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T::regs().cr1().modify(|w| {
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T::REGS.cr1().modify(|w| {
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w.set_cstart(true);
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});
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}
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join(tx_f, rx_f).await;
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finish_dma(T::regs());
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finish_dma(T::REGS);
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Ok(())
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}
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@ -506,79 +505,74 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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self.set_word_size(WordSize::EightBit);
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unsafe {
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T::regs().cr1().modify(|w| {
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T::REGS.cr1().modify(|w| {
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w.set_spe(false);
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});
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set_rxdmaen(T::regs(), true);
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set_rxdmaen(T::REGS, true);
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}
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// TODO: This is unnecessary in some versions because
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// clearing SPE automatically clears the fifos
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flush_rx_fifo(T::regs());
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flush_rx_fifo(T::REGS);
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let rx_request = self.rxdma.request();
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let rx_src = T::regs().rx_ptr();
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let rx_src = T::REGS.rx_ptr();
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unsafe { self.rxdma.start_read(rx_request, rx_src, read) };
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let rx_f = Transfer::new(&mut self.rxdma);
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let tx_request = self.txdma.request();
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let tx_dst = T::regs().tx_ptr();
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let tx_dst = T::REGS.tx_ptr();
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unsafe { self.txdma.start_write(tx_request, write, tx_dst) }
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let tx_f = Transfer::new(&mut self.txdma);
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unsafe {
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set_txdmaen(T::regs(), true);
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T::regs().cr1().modify(|w| {
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set_txdmaen(T::REGS, true);
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T::REGS.cr1().modify(|w| {
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w.set_spe(true);
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});
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#[cfg(spi_v3)]
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T::regs().cr1().modify(|w| {
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T::REGS.cr1().modify(|w| {
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w.set_cstart(true);
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});
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}
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join(tx_f, rx_f).await;
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finish_dma(T::regs());
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finish_dma(T::REGS);
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Ok(())
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}
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pub fn blocking_write<W: Word>(&mut self, words: &[W]) -> Result<(), Error> {
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self.set_word_size(W::WORDSIZE);
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let regs = T::regs();
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for word in words.iter() {
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let _ = transfer_word(regs, *word)?;
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let _ = transfer_word(T::REGS, *word)?;
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}
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Ok(())
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}
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pub fn blocking_read<W: Word>(&mut self, words: &mut [W]) -> Result<(), Error> {
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self.set_word_size(W::WORDSIZE);
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let regs = T::regs();
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for word in words.iter_mut() {
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*word = transfer_word(regs, W::default())?;
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*word = transfer_word(T::REGS, W::default())?;
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}
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Ok(())
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}
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pub fn blocking_transfer_in_place<W: Word>(&mut self, words: &mut [W]) -> Result<(), Error> {
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self.set_word_size(W::WORDSIZE);
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let regs = T::regs();
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for word in words.iter_mut() {
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*word = transfer_word(regs, *word)?;
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*word = transfer_word(T::REGS, *word)?;
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}
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Ok(())
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}
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pub fn blocking_transfer<W: Word>(&mut self, read: &mut [W], write: &[W]) -> Result<(), Error> {
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self.set_word_size(W::WORDSIZE);
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let regs = T::regs();
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let len = read.len().max(write.len());
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for i in 0..len {
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let wb = write.get(i).copied().unwrap_or_default();
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let rb = transfer_word(regs, wb)?;
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let rb = transfer_word(T::REGS, wb)?;
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if let Some(r) = read.get_mut(i) {
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*r = rb;
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}
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@ -623,7 +617,7 @@ trait RegsExt {
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fn rx_ptr<W>(&self) -> *mut W;
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}
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impl RegsExt for crate::pac::spi::Spi {
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impl RegsExt for Regs {
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fn tx_ptr<W>(&self) -> *mut W {
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#[cfg(not(spi_v3))]
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let dr = self.dr();
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@ -938,7 +932,7 @@ pub(crate) mod sealed {
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use super::*;
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pub trait Instance {
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fn regs() -> &'static crate::pac::spi::Spi;
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const REGS: Regs;
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}
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pub trait Word: Copy + 'static {
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@ -1016,9 +1010,7 @@ dma_trait!(TxDma, Instance);
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foreach_peripheral!(
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(spi, $inst:ident) => {
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impl sealed::Instance for peripherals::$inst {
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fn regs() -> &'static crate::pac::spi::Spi {
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&crate::pac::$inst
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}
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const REGS: Regs = crate::pac::$inst;
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}
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impl Instance for peripherals::$inst {}
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