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Merge #1227

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1227: stm32/dma: fix spurious transfer complete interrupts r=Dirbaio a=pattop

DMA interrupts must be acknowledged by writing to the DMA_{L,H}IFCR
register.

Writing to the CR register is unnecessary as the channel (EN bit) is
disabled by hardware on completion of the transfer.


Co-authored-by: Patrick Oppenlander <patrick.oppenlander@gmail.com>
This commit is contained in:
bors[bot] 2023-02-23 15:44:43 +00:00 committed by GitHub
commit f0f92909c1
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1 changed files with 2 additions and 6 deletions
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embassy-stm32/src/dma/dma.rs
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@ -432,12 +432,8 @@ mod low_level_api {
} }
if isr.tcif(channel_num % 4) && cr.read().tcie() { if isr.tcif(channel_num % 4) && cr.read().tcie() {
if cr.read().dbm() == vals::Dbm::DISABLED { /* acknowledge transfer complete interrupt */
cr.write(|_| ()); // Disable channel with the default value.
} else {
// for double buffered mode, clear TCIF flag but do not stop the transfer
dma.ifcr(channel_num / 4).write(|w| w.set_tcif(channel_num % 4, true)); dma.ifcr(channel_num / 4).write(|w| w.set_tcif(channel_num % 4, true));
}
STATE.channels[state_index].waker.wake(); STATE.channels[state_index].waker.wake();
} }
} }