Adjust for STM32U5.

embassy-stm32/Cargo.toml

@@ -1037,6 +1037,29 @@ stm32l4s7zi = [ "stm32-metapac/stm32l4s7zi" ]
 stm32l4s9ai = [ "stm32-metapac/stm32l4s9ai" ]
 stm32l4s9vi = [ "stm32-metapac/stm32l4s9vi" ]
 stm32l4s9zi = [ "stm32-metapac/stm32l4s9zi" ]
+stm32u575ag = [ "stm32-metapac/stm32u575ag" ]
+stm32u575ai = [ "stm32-metapac/stm32u575ai" ]
+stm32u575cg = [ "stm32-metapac/stm32u575cg" ]
+stm32u575ci = [ "stm32-metapac/stm32u575ci" ]
+stm32u575og = [ "stm32-metapac/stm32u575og" ]
+stm32u575oi = [ "stm32-metapac/stm32u575oi" ]
+stm32u575qg = [ "stm32-metapac/stm32u575qg" ]
+stm32u575qi = [ "stm32-metapac/stm32u575qi" ]
+stm32u575rg = [ "stm32-metapac/stm32u575rg" ]
+stm32u575ri = [ "stm32-metapac/stm32u575ri" ]
+stm32u575vg = [ "stm32-metapac/stm32u575vg" ]
+stm32u575vi = [ "stm32-metapac/stm32u575vi" ]
+stm32u575zg = [ "stm32-metapac/stm32u575zg" ]
+stm32u575zi = [ "stm32-metapac/stm32u575zi" ]
+stm32u585ai = [ "stm32-metapac/stm32u585ai" ]
+stm32u585ci = [ "stm32-metapac/stm32u585ci" ]
+stm32u585oi = [ "stm32-metapac/stm32u585oi" ]
+stm32u585qe = [ "stm32-metapac/stm32u585qe" ]
+stm32u585qi = [ "stm32-metapac/stm32u585qi" ]
+stm32u585ri = [ "stm32-metapac/stm32u585ri" ]
+stm32u585vi = [ "stm32-metapac/stm32u585vi" ]
+stm32u585ze = [ "stm32-metapac/stm32u585ze" ]
+stm32u585zi = [ "stm32-metapac/stm32u585zi" ]
 stm32wb55cc = [ "stm32-metapac/stm32wb55cc" ]
 stm32wb55ce = [ "stm32-metapac/stm32wb55ce" ]
 stm32wb55cg = [ "stm32-metapac/stm32wb55cg" ]

embassy-stm32/src/exti.rs

@@ -30,11 +30,11 @@ fn cpu_regs() -> pac::exti::Exti {
     EXTI
 }
 
-#[cfg(not(any(exti_g0, exti_l5, gpio_v1)))]
+#[cfg(not(any(exti_g0, exti_l5, gpio_v1, exti_u5)))]
 fn exticr_regs() -> pac::syscfg::Syscfg {
     pac::SYSCFG
 }
-#[cfg(any(exti_g0, exti_l5))]
+#[cfg(any(exti_g0, exti_l5, exti_u5))]
 fn exticr_regs() -> pac::exti::Exti {
     EXTI
 }
@@ -44,9 +44,9 @@ fn exticr_regs() -> pac::afio::Afio {
 }
 
 pub unsafe fn on_irq() {
-    #[cfg(not(any(exti_g0, exti_l5)))]
+    #[cfg(not(any(exti_g0, exti_l5, exti_u5)))]
     let bits = EXTI.pr(0).read().0;
-    #[cfg(any(exti_g0, exti_l5))]
+    #[cfg(any(exti_g0, exti_l5, exti_u5))]
     let bits = EXTI.rpr(0).read().0 | EXTI.fpr(0).read().0;
 
     // Mask all the channels that fired.
@@ -58,9 +58,9 @@ pub unsafe fn on_irq() {
     }
 
     // Clear pending
-    #[cfg(not(any(exti_g0, exti_l5)))]
+    #[cfg(not(any(exti_g0, exti_l5, exti_u5)))]
     EXTI.pr(0).write_value(Lines(bits));
-    #[cfg(any(exti_g0, exti_l5))]
+    #[cfg(any(exti_g0, exti_l5, exti_u5))]
     {
         EXTI.rpr(0).write_value(Lines(bits));
         EXTI.fpr(0).write_value(Lines(bits));
@@ -148,9 +148,9 @@ impl<'a> ExtiInputFuture<'a> {
             EXTI.ftsr(0).modify(|w| w.set_line(pin, falling));
 
             // clear pending bit
-            #[cfg(not(any(exti_g0, exti_l5)))]
+            #[cfg(not(any(exti_g0, exti_l5, exti_u5)))]
             EXTI.pr(0).write(|w| w.set_line(pin, true));
-            #[cfg(any(exti_g0, exti_l5))]
+            #[cfg(any(exti_g0, exti_l5, exti_u5))]
             {
                 EXTI.rpr(0).write(|w| w.set_line(pin, true));
                 EXTI.fpr(0).write(|w| w.set_line(pin, true));

embassy-stm32/src/pwr/mod.rs

@@ -4,6 +4,7 @@
 #[cfg_attr(pwr_wl5, path = "wl5.rs")]
 #[cfg_attr(pwr_g0, path = "g0.rs")]
 #[cfg_attr(pwr_l1, path = "l1.rs")]
+#[cfg_attr(pwr_u5, path = "u5.rs")]
 mod _version;
 
 pub use _version::*;

embassy-stm32/src/rcc/mod.rs

@@ -24,19 +24,19 @@ pub struct Clocks {
     #[cfg(not(rcc_g0))]
     pub apb2_tim: Hertz,
 
-    #[cfg(rcc_wl5)]
+    #[cfg(any(rcc_wl5, rcc_u5))]
     pub apb3: Hertz,
 
     #[cfg(any(rcc_l0, rcc_l1, rcc_f0, rcc_f1, rcc_f0x0, rcc_g0))]
     pub ahb: Hertz,
 
-    #[cfg(any(rcc_l4, rcc_f4, rcc_f7, rcc_h7, rcc_wb, rcc_wl5))]
+    #[cfg(any(rcc_l4, rcc_f4, rcc_f7, rcc_h7, rcc_u5, rcc_wb, rcc_wl5))]
     pub ahb1: Hertz,
 
-    #[cfg(any(rcc_l4, rcc_f4, rcc_f7, rcc_h7, rcc_wb, rcc_wl5))]
+    #[cfg(any(rcc_l4, rcc_f4, rcc_f7, rcc_h7, rcc_u5, rcc_wb, rcc_wl5))]
     pub ahb2: Hertz,
 
-    #[cfg(any(rcc_l4, rcc_f4, rcc_f7, rcc_h7, rcc_wb, rcc_wl5))]
+    #[cfg(any(rcc_l4, rcc_f4, rcc_f7, rcc_h7, rcc_u5, rcc_wb, rcc_wl5))]
     pub ahb3: Hertz,
 
     #[cfg(any(rcc_h7))]
@@ -100,6 +100,9 @@ cfg_if::cfg_if! {
     } else if #[cfg(any(rcc_g0))] {
         mod g0;
         pub use g0::*;
+    } else if #[cfg(any(rcc_u5))] {
+        mod u5;
+        pub use u5::*;
     }
 }
 

embassy-stm32/src/rcc/u5/mod.rs

@@ -0,0 +1,15 @@
+pub struct Config {}
+
+impl Config {
+    pub fn new() -> Self {
+        Config {}
+    }
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Config::new()
+    }
+}
+
+pub unsafe fn init(config: Config) {}

examples/stm32l4/.cargo/config.toml

@@ -1,7 +1,8 @@
 [target.'cfg(all(target_arch = "arm", target_os = "none"))']
 # replace STM32F429ZITx with your chip as listed in `probe-run --list-chips`
 #runner = "probe-run --chip STM32L475VGT6"
-runner = "probe-run --chip STM32L475VG"
+#runner = "probe-run --chip STM32L475VG"
+runner = "probe-run --chip STM32L4S5VI"
 
 rustflags = [
   # LLD (shipped with the Rust toolchain) is used as the default linker

stm32-data

@@ -1 +1 @@
-Subproject commit 8d3ca7adc6eac3d648bf0c33509e678beaba105a
+Subproject commit bd731709fb98935a632ff63ff0ae8e607397f0ff

stm32-gen-features/src/lib.rs

@@ -2,7 +2,7 @@
 
 use std::{iter::FilterMap, path::Path, slice::Iter};
 
-const SUPPORTED_FAMILIES: [&str; 11] = [
+const SUPPORTED_FAMILIES: [&str; 12] = [
     "stm32f0",
     "stm32f1",
     "stm32f4",
@@ -12,6 +12,7 @@ const SUPPORTED_FAMILIES: [&str; 11] = [
     "stm32l1",
     "stm32l4",
     "stm32h7",
+    "stm32u5",
     "stm32wb55",
     "stm32wl55",
 ];

stm32-metapac-gen/src/lib.rs

@@ -150,6 +150,9 @@ macro_rules! peripheral_count {{
 }
 
 fn make_dma_channel_counts(out: &mut String, data: &BTreeMap<String, u8>) {
+    if data.len() == 0 {
+        return;
+    }
     write!(
         out,
         "#[macro_export]

stm32-metapac/Cargo.toml

@@ -1215,6 +1215,29 @@ stm32l562qe = []
 stm32l562re = []
 stm32l562ve = []
 stm32l562ze = []
+stm32u575ag = []
+stm32u575ai = []
+stm32u575cg = []
+stm32u575ci = []
+stm32u575og = []
+stm32u575oi = []
+stm32u575qg = []
+stm32u575qi = []
+stm32u575rg = []
+stm32u575ri = []
+stm32u575vg = []
+stm32u575vi = []
+stm32u575zg = []
+stm32u575zi = []
+stm32u585ai = []
+stm32u585ci = []
+stm32u585oi = []
+stm32u585qe = []
+stm32u585qi = []
+stm32u585ri = []
+stm32u585vi = []
+stm32u585ze = []
+stm32u585zi = []
 stm32wb10cc = []
 stm32wb15cc = []
 stm32wb30ce = []