From f28ab18d7bc05ade2130979d67b0af6ad4085d76 Mon Sep 17 00:00:00 2001
From: xoviat <xoviat@users.noreply.github.com>
Date: Sun, 27 Aug 2023 09:50:02 -0500
Subject: [PATCH] stm32: fix l4 re-export

---
 embassy-stm32/src/rcc/l4.rs                   | 20 ++++++++-----------
 examples/stm32l4/src/bin/rtc.rs               |  2 +-
 .../src/bin/spe_adin1110_http_server.rs       |  2 +-
 3 files changed, 10 insertions(+), 14 deletions(-)

diff --git a/embassy-stm32/src/rcc/l4.rs b/embassy-stm32/src/rcc/l4.rs
index 1f02254b..c6bccfd2 100644
--- a/embassy-stm32/src/rcc/l4.rs
+++ b/embassy-stm32/src/rcc/l4.rs
@@ -9,7 +9,7 @@ use crate::gpio::sealed::AFType;
 use crate::gpio::Speed;
 use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw};
 use crate::pac::{FLASH, PWR, RCC};
-use crate::rcc::bd::{BackupDomain, RtcClockSource as RCS};
+use crate::rcc::bd::{BackupDomain, RtcClockSource};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
 use crate::{peripherals, Peripheral};
@@ -254,16 +254,11 @@ impl Default for Config {
             pllsai1: None,
             #[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
             hsi48: false,
-            rtc_mux: RtcClockSource::LSI32,
+            rtc_mux: RtcClockSource::LSI,
         }
     }
 }
 
-pub enum RtcClockSource {
-    LSE32,
-    LSI32,
-}
-
 pub enum McoClock {
     DIV1,
     DIV2,
@@ -413,7 +408,7 @@ pub(crate) unsafe fn init(config: Config) {
     RCC.apb1enr1().modify(|w| w.set_pwren(true));
 
     match config.rtc_mux {
-        RtcClockSource::LSE32 => {
+        RtcClockSource::LSE => {
             // 1. Unlock the backup domain
             PWR.cr1().modify(|w| w.set_dbp(true));
 
@@ -429,17 +424,18 @@ pub(crate) unsafe fn init(config: Config) {
             // Wait until LSE is running
             while !RCC.bdcr().read().lserdy() {}
 
-            BackupDomain::set_rtc_clock_source(RCS::LSE);
+            BackupDomain::set_rtc_clock_source(RtcClockSource::LSE);
         }
-        RtcClockSource::LSI32 => {
+        RtcClockSource::LSI => {
             // Turn on the internal 32 kHz LSI oscillator
             RCC.csr().modify(|w| w.set_lsion(true));
 
             // Wait until LSI is running
             while !RCC.csr().read().lsirdy() {}
 
-            BackupDomain::set_rtc_clock_source(RCS::LSI);
+            BackupDomain::set_rtc_clock_source(RtcClockSource::LSI);
         }
+        _ => unreachable!(),
     }
 
     let (sys_clk, sw) = match config.mux {
@@ -451,7 +447,7 @@ pub(crate) unsafe fn init(config: Config) {
                 w.set_msirgsel(true);
                 w.set_msion(true);
 
-                if let RtcClockSource::LSE32 = config.rtc_mux {
+                if let RtcClockSource::LSE = config.rtc_mux {
                     // If LSE is enabled, enable calibration of MSI
                     w.set_msipllen(true);
                 } else {
diff --git a/examples/stm32l4/src/bin/rtc.rs b/examples/stm32l4/src/bin/rtc.rs
index 294ea456..f3f8aa46 100644
--- a/examples/stm32l4/src/bin/rtc.rs
+++ b/examples/stm32l4/src/bin/rtc.rs
@@ -23,7 +23,7 @@ async fn main(_spawner: Spawner) {
             PLLMul::Mul20,
             None,
         );
-        config.rcc.rtc_mux = rcc::RtcClockSource::LSE32;
+        config.rcc.rtc_mux = rcc::RtcClockSource::LSE;
         embassy_stm32::init(config)
     };
     info!("Hello World!");
diff --git a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
index 148c5877..0a677be7 100644
--- a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
+++ b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
@@ -84,7 +84,7 @@ async fn main(spawner: Spawner) {
         None,
     );
     config.rcc.hsi48 = true; // needed for rng
-    config.rcc.rtc_mux = rcc::RtcClockSource::LSI32;
+    config.rcc.rtc_mux = rcc::RtcClockSource::LSI;
 
     let dp = embassy_stm32::init(config);