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Shared buses with SetConfig

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This commit is contained in:
Henrik Alsér
2022-07-08 15:47:47 +02:00
parent 6baddaf539
commit f30ff9cadc
9 changed files with 352 additions and 0 deletions
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4
embassy-embedded-hal/src/lib.rs
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@ -4,3 +4,7 @@
pub mod adapter;
pub mod shared_bus;
pub trait SetConfig<C> {
fn set_config(&mut self, config: &C);
}

84
embassy-embedded-hal/src/shared_bus/blocking/i2c.rs
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@ -7,6 +7,7 @@ use embedded_hal_1::i2c::blocking::{I2c, Operation};
use embedded_hal_1::i2c::ErrorType;
use crate::shared_bus::i2c::I2cBusDeviceError;
use crate::SetConfig;
pub struct I2cBusDevice<'a, M: RawMutex, BUS> {
bus: &'a Mutex<M, RefCell<BUS>>,
@ -82,3 +83,86 @@ where
todo!()
}
}
pub struct I2cBusDeviceWithConfig<'a, M: RawMutex, BUS, C> {
bus: &'a Mutex<M, RefCell<BUS>>,
config: C,
}
impl<'a, M: RawMutex, BUS, C> I2cBusDeviceWithConfig<'a, M, BUS, C> {
pub fn new(bus: &'a Mutex<M, RefCell<BUS>>, config: C) -> Self {
Self { bus, config }
}
}
impl<'a, M: RawMutex, BUS, C> ErrorType for I2cBusDeviceWithConfig<'a, M, BUS, C>
where
BUS: ErrorType,
{
type Error = I2cBusDeviceError<BUS::Error>;
}
impl<M, BUS, C> I2c for I2cBusDeviceWithConfig<'_, M, BUS, C>
where
M: RawMutex,
BUS: I2c + SetConfig<C>,
{
fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
self.bus.lock(|bus| {
let mut bus = bus.borrow_mut();
bus.set_config(&self.config);
bus.read(address, buffer).map_err(I2cBusDeviceError::I2c)
})
}
fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Self::Error> {
self.bus.lock(|bus| {
let mut bus = bus.borrow_mut();
bus.set_config(&self.config);
bus.write(address, bytes).map_err(I2cBusDeviceError::I2c)
})
}
fn write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Self::Error> {
self.bus.lock(|bus| {
let mut bus = bus.borrow_mut();
bus.set_config(&self.config);
bus.write_read(address, wr_buffer, rd_buffer)
.map_err(I2cBusDeviceError::I2c)
})
}
fn transaction<'a>(&mut self, address: u8, operations: &mut [Operation<'a>]) -> Result<(), Self::Error> {
let _ = address;
let _ = operations;
todo!()
}
fn write_iter<B: IntoIterator<Item = u8>>(&mut self, addr: u8, bytes: B) -> Result<(), Self::Error> {
let _ = addr;
let _ = bytes;
todo!()
}
fn write_iter_read<B: IntoIterator<Item = u8>>(
&mut self,
addr: u8,
bytes: B,
buffer: &mut [u8],
) -> Result<(), Self::Error> {
let _ = addr;
let _ = bytes;
let _ = buffer;
todo!()
}
fn transaction_iter<'a, O: IntoIterator<Item = Operation<'a>>>(
&mut self,
address: u8,
operations: O,
) -> Result<(), Self::Error> {
let _ = address;
let _ = operations;
todo!()
}
}

50
embassy-embedded-hal/src/shared_bus/blocking/spi.rs
View File

@ -8,6 +8,7 @@ use embedded_hal_1::spi;
use embedded_hal_1::spi::blocking::{SpiBusFlush, SpiDevice};
use crate::shared_bus::spi::SpiBusDeviceError;
use crate::SetConfig;
pub struct SpiBusDevice<'a, M: RawMutex, BUS, CS> {
bus: &'a Mutex<M, RefCell<BUS>>,
@ -55,3 +56,52 @@ where
})
}
}
pub struct SpiBusDeviceWithConfig<'a, M: RawMutex, BUS, CS, C> {
bus: &'a Mutex<M, RefCell<BUS>>,
cs: CS,
config: C,
}
impl<'a, M: RawMutex, BUS, CS, C> SpiBusDeviceWithConfig<'a, M, BUS, CS, C> {
pub fn new(bus: &'a Mutex<M, RefCell<BUS>>, cs: CS, config: C) -> Self {
Self { bus, cs, config }
}
}
impl<'a, M: RawMutex, BUS, CS, C> spi::ErrorType for SpiBusDeviceWithConfig<'a, M, BUS, CS, C>
where
BUS: spi::ErrorType,
CS: OutputPin,
{
type Error = SpiBusDeviceError<BUS::Error, CS::Error>;
}
impl<BUS, M, CS, C> SpiDevice for SpiBusDeviceWithConfig<'_, M, BUS, CS, C>
where
M: RawMutex,
BUS: SpiBusFlush + SetConfig<C>,
CS: OutputPin,
{
type Bus = BUS;
fn transaction<R>(&mut self, f: impl FnOnce(&mut Self::Bus) -> Result<R, BUS::Error>) -> Result<R, Self::Error> {
self.bus.lock(|bus| {
let mut bus = bus.borrow_mut();
bus.set_config(&self.config);
self.cs.set_low().map_err(SpiBusDeviceError::Cs)?;
let f_res = f(&mut bus);
// On failure, it's important to still flush and deassert CS.
let flush_res = bus.flush();
let cs_res = self.cs.set_high();
let f_res = f_res.map_err(SpiBusDeviceError::Spi)?;
flush_res.map_err(SpiBusDeviceError::Spi)?;
cs_res.map_err(SpiBusDeviceError::Cs)?;
Ok(f_res)
})
}
}

78
embassy-embedded-hal/src/shared_bus/i2c.rs
View File

@ -29,6 +29,8 @@ use embassy::blocking_mutex::raw::RawMutex;
use embassy::mutex::Mutex;
use embedded_hal_async::i2c;
use crate::SetConfig;
#[derive(Copy, Clone, Eq, PartialEq, Debug)]
pub enum I2cBusDeviceError<BUS> {
I2c(BUS),
@ -116,3 +118,79 @@ where
async move { todo!() }
}
}
pub struct I2cBusDeviceWithConfig<'a, M: RawMutex, BUS, C> {
bus: &'a Mutex<M, BUS>,
config: C,
}
impl<'a, M: RawMutex, BUS, C> I2cBusDeviceWithConfig<'a, M, BUS, C> {
pub fn new(bus: &'a Mutex<M, BUS>, config: C) -> Self {
Self { bus, config }
}
}
impl<'a, M: RawMutex, BUS, C> i2c::ErrorType for I2cBusDeviceWithConfig<'a, M, BUS, C>
where
BUS: i2c::ErrorType,
{
type Error = I2cBusDeviceError<BUS::Error>;
}
impl<M, BUS, C> i2c::I2c for I2cBusDeviceWithConfig<'_, M, BUS, C>
where
M: RawMutex + 'static,
BUS: i2c::I2c + SetConfig<C> + 'static,
{
type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Self::ReadFuture<'a> {
async move {
let mut bus = self.bus.lock().await;
bus.set_config(&self.config);
bus.read(address, buffer).await.map_err(I2cBusDeviceError::I2c)?;
Ok(())
}
}
type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Self::WriteFuture<'a> {
async move {
let mut bus = self.bus.lock().await;
bus.set_config(&self.config);
bus.write(address, bytes).await.map_err(I2cBusDeviceError::I2c)?;
Ok(())
}
}
type WriteReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
fn write_read<'a>(
&'a mut self,
address: u8,
wr_buffer: &'a [u8],
rd_buffer: &'a mut [u8],
) -> Self::WriteReadFuture<'a> {
async move {
let mut bus = self.bus.lock().await;
bus.set_config(&self.config);
bus.write_read(address, wr_buffer, rd_buffer)
.await
.map_err(I2cBusDeviceError::I2c)?;
Ok(())
}
}
type TransactionFuture<'a, 'b> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a, 'b: 'a;
fn transaction<'a, 'b>(
&'a mut self,
address: u8,
operations: &'a mut [embedded_hal_async::i2c::Operation<'b>],
) -> Self::TransactionFuture<'a, 'b> {
let _ = address;
let _ = operations;
async move { todo!() }
}
}

61
embassy-embedded-hal/src/shared_bus/spi.rs
View File

@ -34,6 +34,8 @@ use embedded_hal_1::digital::blocking::OutputPin;
use embedded_hal_1::spi::ErrorType;
use embedded_hal_async::spi;
use crate::SetConfig;
#[derive(Copy, Clone, Eq, PartialEq, Debug)]
pub enum SpiBusDeviceError<BUS, CS> {
Spi(BUS),
@ -109,3 +111,62 @@ where
}
}
}
pub struct SpiBusDeviceWithConfig<'a, M: RawMutex, BUS, CS, C> {
bus: &'a Mutex<M, BUS>,
cs: CS,
config: C,
}
impl<'a, M: RawMutex, BUS, CS, C> SpiBusDeviceWithConfig<'a, M, BUS, CS, C> {
pub fn new(bus: &'a Mutex<M, BUS>, cs: CS, config: C) -> Self {
Self { bus, cs, config }
}
}
impl<'a, M: RawMutex, BUS, CS, C> spi::ErrorType for SpiBusDeviceWithConfig<'a, M, BUS, CS, C>
where
BUS: spi::ErrorType,
CS: OutputPin,
{
type Error = SpiBusDeviceError<BUS::Error, CS::Error>;
}
impl<M, BUS, CS, C> spi::SpiDevice for SpiBusDeviceWithConfig<'_, M, BUS, CS, C>
where
M: RawMutex + 'static,
BUS: spi::SpiBusFlush + SetConfig<C> + 'static,
CS: OutputPin,
{
type Bus = BUS;
type TransactionFuture<'a, R, F, Fut> = impl Future<Output = Result<R, Self::Error>> + 'a
where
Self: 'a, R: 'a, F: FnOnce(*mut Self::Bus) -> Fut + 'a,
Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>> + 'a;
fn transaction<'a, R, F, Fut>(&'a mut self, f: F) -> Self::TransactionFuture<'a, R, F, Fut>
where
R: 'a,
F: FnOnce(*mut Self::Bus) -> Fut + 'a,
Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>> + 'a,
{
async move {
let mut bus = self.bus.lock().await;
bus.set_config(&self.config);
self.cs.set_low().map_err(SpiBusDeviceError::Cs)?;
let f_res = f(&mut *bus).await;
// On failure, it's important to still flush and deassert CS.
let flush_res = bus.flush().await;
let cs_res = self.cs.set_high();
let f_res = f_res.map_err(SpiBusDeviceError::Spi)?;
flush_res.map_err(SpiBusDeviceError::Spi)?;
cs_res.map_err(SpiBusDeviceError::Cs)?;
Ok(f_res)
}
}
}