From f48391a6856fdf713002cf9068087136b83da915 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Mon, 22 Aug 2022 16:22:37 +0200 Subject: [PATCH] rp: fix nvic prio bits (it's 2, not 3) --- embassy-rp/Cargo.toml | 2 +- embassy-rp/src/gpio.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/embassy-rp/Cargo.toml b/embassy-rp/Cargo.toml index af7c8ee6..0e53d3a3 100644 --- a/embassy-rp/Cargo.toml +++ b/embassy-rp/Cargo.toml @@ -30,7 +30,7 @@ unstable-traits = ["embedded-hal-1"] embassy-util = { version = "0.1.0", path = "../embassy-util" } embassy-executor = { version = "0.1.0", path = "../embassy-executor" } embassy-time = { version = "0.1.0", path = "../embassy-time", features = [ "tick-1mhz" ] } -embassy-cortex-m = { version = "0.1.0", path = "../embassy-cortex-m", features = ["prio-bits-3"]} +embassy-cortex-m = { version = "0.1.0", path = "../embassy-cortex-m", features = ["prio-bits-2"]} embassy-hal-common = {version = "0.1.0", path = "../embassy-hal-common" } embassy-embedded-hal = {version = "0.1.0", path = "../embassy-embedded-hal" } atomic-polyfill = "1.0.1" diff --git a/embassy-rp/src/gpio.rs b/embassy-rp/src/gpio.rs index f9fa8378..90862fa3 100644 --- a/embassy-rp/src/gpio.rs +++ b/embassy-rp/src/gpio.rs @@ -189,7 +189,7 @@ impl<'d, T: Pin> InputFuture<'d, T> { unsafe { let irq = interrupt::IO_IRQ_BANK0::steal(); irq.disable(); - irq.set_priority(interrupt::Priority::P6); + irq.set_priority(interrupt::Priority::P3); // Each INTR register is divided into 8 groups, one group for each // pin, and each group consists of LEVEL_LOW, LEVEL_HIGH, EDGE_LOW,