Address code review comments
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295af2a057
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f6c2e26372
@ -15,27 +15,47 @@ use crate::{interrupt, pac, peripherals};
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unsafe fn DMA_IRQ_0() {
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unsafe fn DMA_IRQ_0() {
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let ints0 = pac::DMA.ints0().read().ints0();
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let ints0 = pac::DMA.ints0().read().ints0();
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critical_section::with(|_| {
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for channel in 0..CHANNEL_COUNT {
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for channel in 0..CHANNEL_COUNT {
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if ints0 & (1 << channel) == (1 << channel) {
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if ints0 & (1 << channel) == (1 << channel) {
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CHANNEL_WAKERS[channel].wake();
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CHANNEL_WAKERS[channel].wake();
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}
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}
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}
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}
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pac::DMA.ints0().write(|w| w.set_ints0(ints0));
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pac::DMA.ints0().write(|w| w.set_ints0(ints0));
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});
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}
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}
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pub fn read<'a, C: Channel, W: Word>(ch: impl Peripheral<P = C> + 'a, from: *const W, to: &mut [W]) -> Transfer<'a, C> {
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pub(crate) unsafe fn init() {
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let irq = interrupt::DMA_IRQ_0::steal();
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irq.disable();
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irq.set_priority(interrupt::Priority::P6);
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pac::DMA.inte0().write(|w| w.set_inte0(0xFFFF));
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irq.enable();
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}
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pub unsafe fn read<'a, C: Channel, W: Word>(
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ch: impl Peripheral<P = C> + 'a,
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from: *const W,
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to: &mut [W],
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) -> Transfer<'a, C> {
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let (ptr, len) = crate::dma::slice_ptr_parts_mut(to);
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let (ptr, len) = crate::dma::slice_ptr_parts_mut(to);
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copy_inner(ch, from as *const u32, ptr as *mut u32, len, W::size(), false, true)
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copy_inner(ch, from as *const u32, ptr as *mut u32, len, W::size(), false, true)
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}
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}
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pub fn write<'a, C: Channel, W: Word>(ch: impl Peripheral<P = C> + 'a, from: &[W], to: *mut W) -> Transfer<'a, C> {
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pub unsafe fn write<'a, C: Channel, W: Word>(
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ch: impl Peripheral<P = C> + 'a,
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from: &[W],
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to: *mut W,
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) -> Transfer<'a, C> {
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let (from_ptr, len) = crate::dma::slice_ptr_parts(from);
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let (from_ptr, len) = crate::dma::slice_ptr_parts(from);
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copy_inner(ch, from_ptr as *const u32, to as *mut u32, len, W::size(), true, false)
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copy_inner(ch, from_ptr as *const u32, to as *mut u32, len, W::size(), true, false)
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}
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}
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pub fn copy<'a, C: Channel, W: Word>(ch: impl Peripheral<P = C> + 'a, from: &[W], to: &mut [W]) -> Transfer<'a, C> {
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pub unsafe fn copy<'a, C: Channel, W: Word>(
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ch: impl Peripheral<P = C> + 'a,
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from: &[W],
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to: &mut [W],
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) -> Transfer<'a, C> {
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let (from_ptr, from_len) = crate::dma::slice_ptr_parts(from);
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let (from_ptr, from_len) = crate::dma::slice_ptr_parts(from);
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let (to_ptr, to_len) = crate::dma::slice_ptr_parts_mut(to);
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let (to_ptr, to_len) = crate::dma::slice_ptr_parts_mut(to);
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assert_eq!(from_len, to_len);
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assert_eq!(from_len, to_len);
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@ -91,16 +111,6 @@ impl<'a, C: Channel> Transfer<'a, C> {
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pub(crate) fn new(channel: impl Peripheral<P = C> + 'a) -> Self {
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pub(crate) fn new(channel: impl Peripheral<P = C> + 'a) -> Self {
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into_ref!(channel);
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into_ref!(channel);
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unsafe {
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let irq = interrupt::DMA_IRQ_0::steal();
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irq.disable();
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irq.set_priority(interrupt::Priority::P6);
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pac::DMA.inte0().write(|w| w.set_inte0(1 << channel.number()));
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irq.enable();
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}
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Self { channel }
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Self { channel }
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}
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}
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}
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}
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@ -105,6 +105,7 @@ pub fn init(_config: config::Config) -> Peripherals {
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unsafe {
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unsafe {
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clocks::init();
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clocks::init();
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timer::init();
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timer::init();
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dma::init();
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}
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}
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peripherals
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peripherals
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@ -120,17 +120,16 @@ impl<'d, T: Instance, M: Mode> UartTx<'d, T, M> {
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impl<'d, T: Instance> UartTx<'d, T, Async> {
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impl<'d, T: Instance> UartTx<'d, T, Async> {
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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if let Some(ch) = &mut self.tx_dma {
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let ch = self.tx_dma.as_mut().unwrap();
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unsafe {
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let transfer = unsafe {
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T::regs().uartdmacr().modify(|reg| {
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T::regs().uartdmacr().modify(|reg| {
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reg.set_txdmae(true);
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reg.set_txdmae(true);
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});
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});
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}
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// If we don't assign future to a variable, the data register pointer
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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// is held across an await and makes the future non-Send.
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let transfer = crate::dma::write(ch, buffer, T::regs().uartdr().ptr() as *mut _);
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crate::dma::write(ch, buffer, T::regs().uartdr().ptr() as *mut _)
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};
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transfer.await;
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transfer.await;
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}
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Ok(())
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Ok(())
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}
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}
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}
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}
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@ -170,17 +169,16 @@ impl<'d, T: Instance, M: Mode> UartRx<'d, T, M> {
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impl<'d, T: Instance> UartRx<'d, T, Async> {
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impl<'d, T: Instance> UartRx<'d, T, Async> {
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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if let Some(ch) = &mut self.rx_dma {
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let ch = self.rx_dma.as_mut().unwrap();
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unsafe {
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let transfer = unsafe {
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T::regs().uartdmacr().modify(|reg| {
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T::regs().uartdmacr().modify(|reg| {
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reg.set_rxdmae(true);
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reg.set_rxdmae(true);
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});
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});
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}
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// If we don't assign future to a variable, the data register pointer
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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// is held across an await and makes the future non-Send.
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let transfer = crate::dma::read(ch, T::regs().uartdr().ptr() as *const _, buffer);
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crate::dma::read(ch, T::regs().uartdr().ptr() as *const _, buffer)
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};
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transfer.await;
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transfer.await;
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}
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Ok(())
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Ok(())
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}
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}
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}
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}
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