usb: fix slow enumeration with EP0 max_packet_size of 8 or 16.

This commit is contained in:
Dario Nieuwenhuis 2022-04-06 03:02:13 +02:00
parent b2e517bb28
commit f6d11dfba5
2 changed files with 15 additions and 2 deletions

View File

@ -198,7 +198,7 @@ pub trait ControlHandler {
#[derive(Debug)] #[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub(crate) struct DataInStage { pub(crate) struct DataInStage {
length: usize, pub(crate) length: usize,
} }
/// Typestate representing a ControlPipe in the DATA OUT stage /// Typestate representing a ControlPipe in the DATA OUT stage

View File

@ -222,7 +222,20 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
} }
} }
async fn handle_control_in(&mut self, req: Request, stage: DataInStage) { async fn handle_control_in(&mut self, req: Request, mut stage: DataInStage) {
// If we don't have an address yet, respond with max 1 packet.
// The host doesn't know our EP0 max packet size yet, and might assume
// a full-length packet is a short packet, thinking we're done sending data.
// See https://github.com/hathach/tinyusb/issues/184
const DEVICE_DESCRIPTOR_LEN: u8 = 18;
if self.pending_address == 0
&& self.config.max_packet_size_0 < DEVICE_DESCRIPTOR_LEN
&& (self.config.max_packet_size_0 as usize) < stage.length
{
trace!("received control req while not addressed: capping response to 1 packet.");
stage.length = self.config.max_packet_size_0 as _;
}
match (req.request_type, req.recipient) { match (req.request_type, req.recipient) {
(RequestType::Standard, Recipient::Device) => match req.request { (RequestType::Standard, Recipient::Device) => match req.request {
Request::GET_STATUS => { Request::GET_STATUS => {