Merge #441
441: Add implementation of async trait for STM32 I2C v2 r=Dirbaio a=lulf * Add DMA read implementation for I2C v2 * Add example using DMA for I2C Co-authored-by: Ulf Lilleengen <ulf.lilleengen@gmail.com>
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@ -1,9 +1,11 @@
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use core::cmp;
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use core::future::Future;
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use core::marker::PhantomData;
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use core::task::Poll;
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use atomic_polyfill::{AtomicUsize, Ordering};
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use embassy::interrupt::InterruptExt;
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use embassy::traits::i2c::I2c as I2cTrait;
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use embassy::util::Unborrow;
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use embassy::waitqueue::AtomicWaker;
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use embassy_hal_common::drop::OnDrop;
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@ -139,14 +141,14 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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}
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}
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fn master_read(&mut self, address: u8, length: usize, stop: Stop, reload: bool, restart: bool) {
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unsafe fn master_read(address: u8, length: usize, stop: Stop, reload: bool, restart: bool) {
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assert!(length < 256 && length > 0);
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if !restart {
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// Wait for any previous address sequence to end
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// automatically. This could be up to 50% of a bus
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// cycle (ie. up to 0.5/freq)
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while unsafe { T::regs().cr2().read().start() == i2c::vals::Start::START } {}
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while T::regs().cr2().read().start() == i2c::vals::Start::START {}
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}
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// Set START and prepare to receive bytes into
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@ -159,7 +161,6 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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i2c::vals::Reload::COMPLETED
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};
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unsafe {
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T::regs().cr2().modify(|w| {
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w.set_sadd((address << 1 | 0) as u16);
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w.set_add10(i2c::vals::Add::BIT7);
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@ -170,7 +171,6 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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w.set_reload(reload);
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});
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}
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}
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unsafe fn master_write(address: u8, length: usize, stop: Stop, reload: bool) {
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assert!(length < 256 && length > 0);
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@ -309,13 +309,15 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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};
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let last_chunk_idx = total_chunks.saturating_sub(1);
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self.master_read(
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unsafe {
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Self::master_read(
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address,
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buffer.len().min(255),
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Stop::Automatic,
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last_chunk_idx != 0,
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restart,
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);
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}
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for (number, chunk) in buffer.chunks_mut(255).enumerate() {
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if number != 0 {
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@ -482,6 +484,88 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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Ok(())
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}
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async fn read_dma_internal(
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&mut self,
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address: u8,
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buffer: &mut [u8],
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restart: bool,
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) -> Result<(), Error>
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where
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RXDMA: crate::i2c::RxDma<T>,
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{
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let total_len = buffer.len();
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let completed_chunks = total_len / 255;
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let total_chunks = if completed_chunks * 255 == total_len {
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completed_chunks
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} else {
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completed_chunks + 1
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};
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let dma_transfer = unsafe {
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let regs = T::regs();
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regs.cr1().modify(|w| {
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w.set_rxdmaen(true);
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w.set_tcie(true);
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});
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let src = regs.rxdr().ptr() as *mut u8;
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let ch = &mut self.rx_dma;
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ch.read(ch.request(), src, buffer)
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};
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let state_number = T::state_number();
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STATE.chunks_transferred[state_number].store(0, Ordering::Relaxed);
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let mut remaining_len = total_len;
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let _on_drop = OnDrop::new(|| {
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let regs = T::regs();
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unsafe {
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regs.cr1().modify(|w| {
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w.set_rxdmaen(false);
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w.set_tcie(false);
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})
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}
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});
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// NOTE(unsafe) self.rx_dma does not fiddle with the i2c registers
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unsafe {
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Self::master_read(
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address,
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total_len.min(255),
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Stop::Software,
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total_chunks != 1,
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restart,
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);
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}
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poll_fn(|cx| {
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STATE.waker[state_number].register(cx.waker());
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let chunks_transferred = STATE.chunks_transferred[state_number].load(Ordering::Relaxed);
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if chunks_transferred == total_chunks {
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return Poll::Ready(());
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} else if chunks_transferred != 0 {
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remaining_len = remaining_len.saturating_sub(255);
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let last_piece = chunks_transferred + 1 == total_chunks;
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// NOTE(unsafe) self.rx_dma does not fiddle with the i2c registers
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unsafe {
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Self::master_continue(remaining_len.min(255), !last_piece);
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T::regs().cr1().modify(|w| w.set_tcie(true));
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}
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}
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Poll::Pending
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})
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.await;
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dma_transfer.await;
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// This should be done already
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self.wait_tc()?;
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self.master_stop();
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Ok(())
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}
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pub async fn write_dma(&mut self, address: u8, bytes: &[u8]) -> Result<(), Error>
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where
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TXDMA: crate::i2c::TxDma<T>,
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@ -511,6 +595,18 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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Ok(())
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}
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pub async fn read_dma(
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&mut self,
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address: u8,
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buffer: &mut [u8],
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restart: bool,
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) -> Result<(), Error>
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where
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RXDMA: crate::i2c::RxDma<T>,
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{
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self.read_dma_internal(address, buffer, restart).await
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}
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pub fn write_vectored(&mut self, address: u8, bytes: &[&[u8]]) -> Result<(), Error> {
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if bytes.is_empty() {
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return Err(Error::ZeroLengthTransfer);
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@ -754,3 +850,36 @@ impl Timings {
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}
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}
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}
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impl<'d, T: Instance, TXDMA: super::TxDma<T>, RXDMA: super::RxDma<T>> I2cTrait<u8>
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for I2c<'d, T, TXDMA, RXDMA>
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{
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type Error = super::Error;
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#[rustfmt::skip]
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type WriteFuture<'a> where 'd: 'a, T: 'a, TXDMA: 'a, RXDMA: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
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#[rustfmt::skip]
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type ReadFuture<'a> where 'd: 'a, T: 'a, TXDMA: 'a, RXDMA: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
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#[rustfmt::skip]
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type WriteReadFuture<'a> where 'd: 'a, T: 'a, TXDMA: 'a, RXDMA: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
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fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Self::ReadFuture<'a> {
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self.read_dma(address, buffer, false)
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}
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fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Self::WriteFuture<'a> {
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self.write_dma(address, bytes)
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}
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fn write_read<'a>(
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&'a mut self,
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address: u8,
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bytes: &'a [u8],
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buffer: &'a mut [u8],
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) -> Self::WriteReadFuture<'a> {
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async move {
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self.write_dma(address, bytes).await?;
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self.read_dma(address, buffer, true).await
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}
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}
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}
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35
examples/stm32l4/src/bin/i2c_dma.rs
Normal file
35
examples/stm32l4/src/bin/i2c_dma.rs
Normal file
@ -0,0 +1,35 @@
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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#[path = "../example_common.rs"]
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mod example_common;
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use embassy::executor::Spawner;
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use embassy::traits::i2c::I2c as I2cTrait;
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use embassy_stm32::i2c::I2c;
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use embassy_stm32::interrupt;
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use embassy_stm32::time::Hertz;
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use embassy_stm32::Peripherals;
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use example_common::{info, unwrap};
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const ADDRESS: u8 = 0x5F;
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const WHOAMI: u8 = 0x0F;
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#[embassy::main]
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async fn main(_spawner: Spawner, p: Peripherals) -> ! {
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let irq = interrupt::take!(I2C2_EV);
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let mut i2c = I2c::new(
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p.I2C2,
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p.PB10,
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p.PB11,
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irq,
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p.DMA1_CH4,
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p.DMA1_CH5,
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Hertz(100_000),
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);
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let mut data = [0u8; 1];
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unwrap!(i2c.write_read(ADDRESS, &[WHOAMI], &mut data).await);
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info!("Whoami: {}", data[0]);
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}
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