stm32/can: move to irq binding use embassy channel
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xoviat
parent
403cbb1dc9
commit
f8d35806dc
@ -69,7 +69,6 @@ cfg-if = "1.0.0"
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embedded-io = { version = "0.4.0", features = ["async"], optional = true }
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chrono = { version = "^0.4", default-features = false, optional = true}
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bit_field = "0.10.2"
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heapless = { version = "0.7.5", default-features = false }
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[dev-dependencies]
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critical-section = { version = "1.1", features = ["std"] }
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@ -1,17 +1,73 @@
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use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::ops::{Deref, DerefMut};
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use core::task::Poll;
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pub use bxcan;
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use bxcan::{Data, ExtendedId, Frame, Id, StandardId};
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use embassy_cortex_m::interrupt::Interrupt;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use futures::FutureExt;
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use crate::gpio::sealed::AFType;
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use crate::interrupt::InterruptExt;
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use crate::pac::can::vals::{Lec, RirIde};
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use crate::rcc::RccPeripheral;
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use crate::time::Hertz;
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use crate::{peripherals, Peripheral};
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use crate::{interrupt, peripherals, Peripheral};
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/// Interrupt handler.
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pub struct TxInterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::Handler<T::TXInterrupt> for TxInterruptHandler<T> {
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unsafe fn on_interrupt() {
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T::regs().tsr().write(|v| {
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v.set_rqcp(0, true);
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v.set_rqcp(1, true);
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v.set_rqcp(2, true);
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});
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T::state().tx_waker.wake();
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}
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}
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pub struct Rx0InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::Handler<T::RX0Interrupt> for Rx0InterruptHandler<T> {
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unsafe fn on_interrupt() {
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Can::<T>::receive_fifo(RxFifo::Fifo0);
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}
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}
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pub struct Rx1InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::Handler<T::RX1Interrupt> for Rx1InterruptHandler<T> {
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unsafe fn on_interrupt() {
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Can::<T>::receive_fifo(RxFifo::Fifo1);
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}
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}
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pub struct SceInterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::Handler<T::SCEInterrupt> for SceInterruptHandler<T> {
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unsafe fn on_interrupt() {
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let msr = T::regs().msr();
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let msr_val = msr.read();
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if msr_val.erri() {
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msr.modify(|v| v.set_erri(true));
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T::state().err_waker.wake();
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}
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}
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}
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pub struct Can<'d, T: Instance> {
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can: bxcan::Can<BxcanInstance<'d, T>>,
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@ -64,12 +120,13 @@ impl<'d, T: Instance> Can<'d, T> {
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peri: impl Peripheral<P = T> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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tx_irq: impl Peripheral<P = T::TXInterrupt> + 'd,
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rx0_irq: impl Peripheral<P = T::RX0Interrupt> + 'd,
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rx1_irq: impl Peripheral<P = T::RX1Interrupt> + 'd,
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sce_irq: impl Peripheral<P = T::SCEInterrupt> + 'd,
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_irqs: impl interrupt::Binding<T::TXInterrupt, TxInterruptHandler<T>>
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+ interrupt::Binding<T::RX0Interrupt, Rx0InterruptHandler<T>>
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+ interrupt::Binding<T::RX1Interrupt, Rx1InterruptHandler<T>>
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+ interrupt::Binding<T::SCEInterrupt, SceInterruptHandler<T>>
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+ 'd,
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) -> Self {
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into_ref!(peri, rx, tx, tx_irq, rx0_irq, rx1_irq, sce_irq);
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into_ref!(peri, rx, tx);
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unsafe {
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rx.set_as_af(rx.af_num(), AFType::Input);
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@ -79,21 +136,19 @@ impl<'d, T: Instance> Can<'d, T> {
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T::enable();
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T::reset();
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tx_irq.unpend();
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tx_irq.set_handler(Self::tx_interrupt);
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tx_irq.enable();
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unsafe {
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T::TXInterrupt::steal().unpend();
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T::TXInterrupt::steal().enable();
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rx0_irq.unpend();
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rx0_irq.set_handler(Self::rx0_interrupt);
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rx0_irq.enable();
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T::RX0Interrupt::steal().unpend();
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T::RX0Interrupt::steal().enable();
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rx1_irq.unpend();
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rx1_irq.set_handler(Self::rx1_interrupt);
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rx1_irq.enable();
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T::RX1Interrupt::steal().unpend();
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T::RX1Interrupt::steal().enable();
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sce_irq.unpend();
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sce_irq.set_handler(Self::sce_interrupt);
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sce_irq.enable();
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T::SCEInterrupt::steal().unpend();
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T::SCEInterrupt::steal().enable();
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}
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let can = bxcan::Can::builder(BxcanInstance(peri)).leave_disabled();
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Self { can }
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@ -133,12 +188,11 @@ impl<'d, T: Instance> Can<'d, T> {
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pub async fn receive_frame_or_error(&mut self) -> FrameOrError {
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poll_fn(|cx| {
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if let Some(frame) = T::state().rx_queue.dequeue() {
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if let Poll::Ready(frame) = T::state().rx_queue.recv().poll_unpin(cx) {
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return Poll::Ready(FrameOrError::Frame(frame));
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} else if let Some(err) = self.curr_error() {
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return Poll::Ready(FrameOrError::Error(err));
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}
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T::state().rx_waker.register(cx.waker());
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T::state().err_waker.register(cx.waker());
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Poll::Pending
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})
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@ -159,69 +213,42 @@ impl<'d, T: Instance> Can<'d, T> {
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None
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}
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unsafe fn sce_interrupt(_: *mut ()) {
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let msr = T::regs().msr();
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let msr_val = msr.read();
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if msr_val.erri() {
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msr.modify(|v| v.set_erri(true));
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T::state().err_waker.wake();
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return;
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}
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}
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unsafe fn tx_interrupt(_: *mut ()) {
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T::regs().tsr().write(|v| {
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v.set_rqcp(0, true);
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v.set_rqcp(1, true);
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v.set_rqcp(2, true);
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});
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T::state().tx_waker.wake();
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}
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unsafe fn rx0_interrupt(_: *mut ()) {
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Self::receive_fifo(RxFifo::Fifo0);
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}
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unsafe fn rx1_interrupt(_: *mut ()) {
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Self::receive_fifo(RxFifo::Fifi1);
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}
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unsafe fn receive_fifo(fifo: RxFifo) {
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let state = T::state();
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let regs = T::regs();
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let fifo_idx = match fifo {
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RxFifo::Fifo0 => 0usize,
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RxFifo::Fifi1 => 1usize,
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RxFifo::Fifo1 => 1usize,
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};
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let rfr = regs.rfr(fifo_idx);
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let fifo = regs.rx(fifo_idx);
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// If there are no pending messages, there is nothing to do
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if rfr.read().fmp() == 0 {
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return;
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loop {
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// If there are no pending messages, there is nothing to do
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if rfr.read().fmp() == 0 {
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return;
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}
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let rir = fifo.rir().read();
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let id = if rir.ide() == RirIde::STANDARD {
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Id::from(StandardId::new_unchecked(rir.stid()))
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} else {
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Id::from(ExtendedId::new_unchecked(rir.exid()))
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};
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let data_len = fifo.rdtr().read().dlc() as usize;
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let mut data: [u8; 8] = [0; 8];
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data[0..4].copy_from_slice(&fifo.rdlr().read().0.to_ne_bytes());
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data[4..8].copy_from_slice(&fifo.rdhr().read().0.to_ne_bytes());
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let frame = Frame::new_data(id, Data::new(&data[0..data_len]).unwrap());
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rfr.modify(|v| v.set_rfom(true));
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/*
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NOTE: consensus was reached that if rx_queue is full, packets should be dropped
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*/
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let _ = state.rx_queue.try_send(frame);
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}
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let rir = fifo.rir().read();
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let id = if rir.ide() == RirIde::STANDARD {
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Id::from(StandardId::new_unchecked(rir.stid()))
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} else {
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Id::from(ExtendedId::new_unchecked(rir.exid()))
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};
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let data_len = fifo.rdtr().read().dlc() as usize;
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let mut data: [u8; 8] = [0; 8];
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data[0..4].copy_from_slice(&fifo.rdlr().read().0.to_ne_bytes());
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data[4..8].copy_from_slice(&fifo.rdhr().read().0.to_ne_bytes());
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let frame = Frame::new_data(id, Data::new(&data[0..data_len]).unwrap());
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rfr.modify(|v| v.set_rfom(true));
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match state.rx_queue.enqueue(frame) {
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Ok(_) => {}
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Err(_) => defmt::error!("RX queue overflow"),
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}
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state.rx_waker.wake();
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}
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pub fn calc_bxcan_timings(periph_clock: Hertz, can_bitrate: u32) -> Option<u32> {
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@ -318,7 +345,7 @@ impl<'d, T: Instance> Can<'d, T> {
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enum RxFifo {
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Fifo0,
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Fifi1,
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Fifo1,
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}
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impl<'d, T: Instance> Drop for Can<'d, T> {
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@ -345,23 +372,22 @@ impl<'d, T: Instance> DerefMut for Can<'d, T> {
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}
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pub(crate) mod sealed {
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use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
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use embassy_sync::channel::Channel;
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use embassy_sync::waitqueue::AtomicWaker;
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use heapless::mpmc::Q8;
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pub struct State {
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pub tx_waker: AtomicWaker,
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pub rx_waker: AtomicWaker,
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pub err_waker: AtomicWaker,
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pub rx_queue: Q8<bxcan::Frame>,
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pub rx_queue: Channel<CriticalSectionRawMutex, bxcan::Frame, 32>,
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}
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impl State {
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pub const fn new() -> Self {
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Self {
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tx_waker: AtomicWaker::new(),
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rx_waker: AtomicWaker::new(),
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err_waker: AtomicWaker::new(),
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rx_queue: Q8::new(),
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rx_queue: Channel::new(),
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}
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}
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}
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