rp/clocks: comment out all gpin handling for now
gpin clock sources aren't going to be very useful during cold boot and thus require runtime clock reconfig. once we get there we can use this for reference. or maybe we can't, only time will tell.
This commit is contained in:
pennae
parent
1e029a9e66
commit
fc746a88b5
@ -8,6 +8,10 @@ use crate::gpio::sealed::Pin;
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use crate::gpio::AnyPin;
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use crate::{pac, reset, Peripheral};
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// NOTE: all gpin handling is commented out for future reference.
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// gpin is not usually safe to use during the boot init() call, so it won't
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// be very useful until we have runtime clock reconfiguration. once this
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// happens we can resurrect the commented-out gpin bits.
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struct Clocks {
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xosc: AtomicU32,
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sys: AtomicU32,
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@ -16,8 +20,8 @@ struct Clocks {
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pll_usb: AtomicU32,
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usb: AtomicU32,
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adc: AtomicU32,
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gpin0: AtomicU32,
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gpin1: AtomicU32,
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// gpin0: AtomicU32,
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// gpin1: AtomicU32,
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rosc: AtomicU32,
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peri: AtomicU32,
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rtc: AtomicU16,
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@ -31,8 +35,8 @@ static CLOCKS: Clocks = Clocks {
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pll_usb: AtomicU32::new(0),
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usb: AtomicU32::new(0),
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adc: AtomicU32::new(0),
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gpin0: AtomicU32::new(0),
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gpin1: AtomicU32::new(0),
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// gpin0: AtomicU32::new(0),
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// gpin1: AtomicU32::new(0),
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rosc: AtomicU32::new(0),
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peri: AtomicU32::new(0),
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rtc: AtomicU16::new(0),
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@ -47,8 +51,8 @@ pub enum PeriClkSrc {
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PllUsb = ClkPeriCtrlAuxsrc::CLKSRC_PLL_USB.0,
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Rosc = ClkPeriCtrlAuxsrc::ROSC_CLKSRC_PH.0,
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Xosc = ClkPeriCtrlAuxsrc::XOSC_CLKSRC.0,
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Gpin0 = ClkPeriCtrlAuxsrc::CLKSRC_GPIN0.0,
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Gpin1 = ClkPeriCtrlAuxsrc::CLKSRC_GPIN1.0,
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// Gpin0 = ClkPeriCtrlAuxsrc::CLKSRC_GPIN0.0,
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// Gpin1 = ClkPeriCtrlAuxsrc::CLKSRC_GPIN1.0,
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}
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#[non_exhaustive]
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@ -61,8 +65,8 @@ pub struct ClockConfig {
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pub usb_clk: Option<UsbClkConfig>,
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pub adc_clk: Option<AdcClkConfig>,
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pub rtc_clk: Option<RtcClkConfig>,
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gpin0: Option<(u32, Gpin<'static, AnyPin>)>,
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gpin1: Option<(u32, Gpin<'static, AnyPin>)>,
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// gpin0: Option<(u32, Gpin<'static, AnyPin>)>,
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// gpin1: Option<(u32, Gpin<'static, AnyPin>)>,
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}
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impl ClockConfig {
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@ -118,8 +122,8 @@ impl ClockConfig {
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div_frac: 0,
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phase: 0,
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}),
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gpin0: None,
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gpin1: None,
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// gpin0: None,
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// gpin1: None,
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}
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}
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@ -156,20 +160,20 @@ impl ClockConfig {
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div_frac: 171,
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phase: 0,
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}),
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gpin0: None,
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gpin1: None,
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// gpin0: None,
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// gpin1: None,
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}
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}
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pub fn bind_gpin<P: GpinPin>(&mut self, gpin: Gpin<'static, P>, hz: u32) {
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match P::NR {
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0 => self.gpin0 = Some((hz, gpin.map_into())),
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1 => self.gpin1 = Some((hz, gpin.map_into())),
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_ => unreachable!(),
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}
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// pin is now provisionally bound. if the config is applied it must be forgotten,
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// or Gpin::drop will deconfigure the clock input.
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}
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// pub fn bind_gpin<P: GpinPin>(&mut self, gpin: Gpin<'static, P>, hz: u32) {
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// match P::NR {
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// 0 => self.gpin0 = Some((hz, gpin.map_into())),
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// 1 => self.gpin1 = Some((hz, gpin.map_into())),
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// _ => unreachable!(),
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// }
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// // pin is now provisionally bound. if the config is applied it must be forgotten,
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// // or Gpin::drop will deconfigure the clock input.
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// }
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}
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#[repr(u16)]
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@ -219,8 +223,8 @@ pub enum RefClkSrc {
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Rosc,
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// aux sources
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PllUsb,
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Gpin0,
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Gpin1,
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// Gpin0,
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// Gpin1,
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}
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#[non_exhaustive]
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@ -233,8 +237,8 @@ pub enum SysClkSrc {
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PllUsb,
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Rosc,
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Xosc,
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Gpin0,
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Gpin1,
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// Gpin0,
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// Gpin1,
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}
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pub struct SysClkConfig {
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@ -251,8 +255,8 @@ pub enum UsbClkSrc {
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PllSys = ClkUsbCtrlAuxsrc::CLKSRC_PLL_SYS.0,
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Rosc = ClkUsbCtrlAuxsrc::ROSC_CLKSRC_PH.0,
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Xosc = ClkUsbCtrlAuxsrc::XOSC_CLKSRC.0,
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Gpin0 = ClkUsbCtrlAuxsrc::CLKSRC_GPIN0.0,
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Gpin1 = ClkUsbCtrlAuxsrc::CLKSRC_GPIN1.0,
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// Gpin0 = ClkUsbCtrlAuxsrc::CLKSRC_GPIN0.0,
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// Gpin1 = ClkUsbCtrlAuxsrc::CLKSRC_GPIN1.0,
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}
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pub struct UsbClkConfig {
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@ -269,8 +273,8 @@ pub enum AdcClkSrc {
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PllSys = ClkAdcCtrlAuxsrc::CLKSRC_PLL_SYS.0,
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Rosc = ClkAdcCtrlAuxsrc::ROSC_CLKSRC_PH.0,
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Xosc = ClkAdcCtrlAuxsrc::XOSC_CLKSRC.0,
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Gpin0 = ClkAdcCtrlAuxsrc::CLKSRC_GPIN0.0,
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Gpin1 = ClkAdcCtrlAuxsrc::CLKSRC_GPIN1.0,
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// Gpin0 = ClkAdcCtrlAuxsrc::CLKSRC_GPIN0.0,
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// Gpin1 = ClkAdcCtrlAuxsrc::CLKSRC_GPIN1.0,
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}
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pub struct AdcClkConfig {
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@ -287,8 +291,8 @@ pub enum RtcClkSrc {
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PllSys = ClkRtcCtrlAuxsrc::CLKSRC_PLL_SYS.0,
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Rosc = ClkRtcCtrlAuxsrc::ROSC_CLKSRC_PH.0,
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Xosc = ClkRtcCtrlAuxsrc::XOSC_CLKSRC.0,
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Gpin0 = ClkRtcCtrlAuxsrc::CLKSRC_GPIN0.0,
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Gpin1 = ClkRtcCtrlAuxsrc::CLKSRC_GPIN1.0,
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// Gpin0 = ClkRtcCtrlAuxsrc::CLKSRC_GPIN0.0,
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// Gpin1 = ClkRtcCtrlAuxsrc::CLKSRC_GPIN1.0,
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}
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pub struct RtcClkConfig {
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@ -306,6 +310,7 @@ pub(crate) unsafe fn init(config: ClockConfig) {
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// - USB, SYSCFG (breaks usb-to-swd on core1)
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let mut peris = reset::ALL_PERIPHERALS;
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peris.set_io_qspi(false);
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// peris.set_io_bank0(false); // might be suicide if we're clocked from gpin
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peris.set_pads_qspi(false);
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peris.set_pll_sys(false);
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peris.set_pll_usb(false);
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@ -332,16 +337,16 @@ pub(crate) unsafe fn init(config: ClockConfig) {
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reset::reset(peris);
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reset::unreset_wait(peris);
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let gpin0_freq = config.gpin0.map_or(0, |p| {
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core::mem::forget(p.1);
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p.0
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});
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CLOCKS.gpin0.store(gpin0_freq, Ordering::Relaxed);
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let gpin1_freq = config.gpin1.map_or(0, |p| {
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core::mem::forget(p.1);
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p.0
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});
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CLOCKS.gpin1.store(gpin1_freq, Ordering::Relaxed);
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// let gpin0_freq = config.gpin0.map_or(0, |p| {
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// core::mem::forget(p.1);
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// p.0
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// });
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// CLOCKS.gpin0.store(gpin0_freq, Ordering::Relaxed);
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// let gpin1_freq = config.gpin1.map_or(0, |p| {
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// core::mem::forget(p.1);
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// p.0
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// });
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// CLOCKS.gpin1.store(gpin1_freq, Ordering::Relaxed);
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let rosc_freq = match config.rosc {
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Some(config) => configure_rosc(config),
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@ -381,8 +386,8 @@ pub(crate) unsafe fn init(config: ClockConfig) {
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RefClkSrc::Xosc => (Src::XOSC_CLKSRC, Aux::CLKSRC_PLL_USB, xosc_freq / div),
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RefClkSrc::Rosc => (Src::ROSC_CLKSRC_PH, Aux::CLKSRC_PLL_USB, rosc_freq / div),
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RefClkSrc::PllUsb => (Src::CLKSRC_CLK_REF_AUX, Aux::CLKSRC_PLL_USB, pll_usb_freq / div),
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RefClkSrc::Gpin0 => (Src::CLKSRC_CLK_REF_AUX, Aux::CLKSRC_GPIN0, gpin0_freq / div),
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RefClkSrc::Gpin1 => (Src::CLKSRC_CLK_REF_AUX, Aux::CLKSRC_GPIN1, gpin1_freq / div),
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// RefClkSrc::Gpin0 => (Src::CLKSRC_CLK_REF_AUX, Aux::CLKSRC_GPIN0, gpin0_freq / div),
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// RefClkSrc::Gpin1 => (Src::CLKSRC_CLK_REF_AUX, Aux::CLKSRC_GPIN1, gpin1_freq / div),
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}
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};
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assert!(clk_ref_freq != 0);
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@ -409,8 +414,8 @@ pub(crate) unsafe fn init(config: ClockConfig) {
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SysClkSrc::PllUsb => (Src::CLKSRC_CLK_SYS_AUX, Aux::CLKSRC_PLL_USB, pll_usb_freq),
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SysClkSrc::Rosc => (Src::CLKSRC_CLK_SYS_AUX, Aux::ROSC_CLKSRC, rosc_freq),
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SysClkSrc::Xosc => (Src::CLKSRC_CLK_SYS_AUX, Aux::XOSC_CLKSRC, xosc_freq),
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SysClkSrc::Gpin0 => (Src::CLKSRC_CLK_SYS_AUX, Aux::CLKSRC_GPIN0, gpin0_freq),
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SysClkSrc::Gpin1 => (Src::CLKSRC_CLK_SYS_AUX, Aux::CLKSRC_GPIN1, gpin1_freq),
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// SysClkSrc::Gpin0 => (Src::CLKSRC_CLK_SYS_AUX, Aux::CLKSRC_GPIN0, gpin0_freq),
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// SysClkSrc::Gpin1 => (Src::CLKSRC_CLK_SYS_AUX, Aux::CLKSRC_GPIN1, gpin1_freq),
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};
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assert!(config.sys_clk.div_int <= 0x1000000);
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let div = config.sys_clk.div_int as u64 * 256 + config.sys_clk.div_frac as u64;
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@ -445,8 +450,8 @@ pub(crate) unsafe fn init(config: ClockConfig) {
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PeriClkSrc::PllUsb => pll_usb_freq,
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PeriClkSrc::Rosc => rosc_freq,
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PeriClkSrc::Xosc => xosc_freq,
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PeriClkSrc::Gpin0 => gpin0_freq,
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PeriClkSrc::Gpin1 => gpin1_freq,
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// PeriClkSrc::Gpin0 => gpin0_freq,
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// PeriClkSrc::Gpin1 => gpin1_freq,
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};
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assert!(peri_freq != 0);
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CLOCKS.peri.store(peri_freq, Ordering::Relaxed);
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@ -470,8 +475,8 @@ pub(crate) unsafe fn init(config: ClockConfig) {
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UsbClkSrc::PllSys => pll_sys_freq,
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UsbClkSrc::Rosc => rosc_freq,
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UsbClkSrc::Xosc => xosc_freq,
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UsbClkSrc::Gpin0 => gpin0_freq,
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UsbClkSrc::Gpin1 => gpin1_freq,
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// UsbClkSrc::Gpin0 => gpin0_freq,
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// UsbClkSrc::Gpin1 => gpin1_freq,
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};
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assert!(usb_freq != 0);
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assert!(conf.div >= 1 && conf.div <= 4);
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@ -493,8 +498,8 @@ pub(crate) unsafe fn init(config: ClockConfig) {
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AdcClkSrc::PllSys => pll_sys_freq,
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AdcClkSrc::Rosc => rosc_freq,
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AdcClkSrc::Xosc => xosc_freq,
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AdcClkSrc::Gpin0 => gpin0_freq,
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AdcClkSrc::Gpin1 => gpin1_freq,
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// AdcClkSrc::Gpin0 => gpin0_freq,
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// AdcClkSrc::Gpin1 => gpin1_freq,
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};
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assert!(adc_in_freq != 0);
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assert!(conf.div >= 1 && conf.div <= 4);
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@ -519,8 +524,8 @@ pub(crate) unsafe fn init(config: ClockConfig) {
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RtcClkSrc::PllSys => pll_sys_freq,
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RtcClkSrc::Rosc => rosc_freq,
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RtcClkSrc::Xosc => xosc_freq,
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RtcClkSrc::Gpin0 => gpin0_freq,
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RtcClkSrc::Gpin1 => gpin1_freq,
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// RtcClkSrc::Gpin0 => gpin0_freq,
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// RtcClkSrc::Gpin1 => gpin1_freq,
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};
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assert!(rtc_in_freq != 0);
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assert!(config.sys_clk.div_int <= 0x1000000);
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@ -576,12 +581,12 @@ pub fn xosc_freq() -> u32 {
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CLOCKS.xosc.load(Ordering::Relaxed)
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}
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pub fn gpin0_freq() -> u32 {
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CLOCKS.gpin0.load(Ordering::Relaxed)
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}
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pub fn gpin1_freq() -> u32 {
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CLOCKS.gpin1.load(Ordering::Relaxed)
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}
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// pub fn gpin0_freq() -> u32 {
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// CLOCKS.gpin0.load(Ordering::Relaxed)
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// }
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// pub fn gpin1_freq() -> u32 {
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// CLOCKS.gpin1.load(Ordering::Relaxed)
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// }
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pub fn pll_sys_freq() -> u32 {
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CLOCKS.pll_sys.load(Ordering::Relaxed)
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@ -705,9 +710,9 @@ impl<'d, T: Pin> Gpin<'d, T> {
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}
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}
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fn map_into(self) -> Gpin<'d, AnyPin> {
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unsafe { core::mem::transmute(self) }
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}
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// fn map_into(self) -> Gpin<'d, AnyPin> {
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// unsafe { core::mem::transmute(self) }
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// }
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}
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impl<'d, T: Pin> Drop for Gpin<'d, T> {
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@ -743,8 +748,8 @@ impl_gpoutpin!(PIN_25, 3);
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#[repr(u8)]
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pub enum GpoutSrc {
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PllSys = ClkGpoutCtrlAuxsrc::CLKSRC_PLL_SYS.0,
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Gpin0 = ClkGpoutCtrlAuxsrc::CLKSRC_GPIN0.0,
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Gpin1 = ClkGpoutCtrlAuxsrc::CLKSRC_GPIN1.0,
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// Gpin0 = ClkGpoutCtrlAuxsrc::CLKSRC_GPIN0.0,
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// Gpin1 = ClkGpoutCtrlAuxsrc::CLKSRC_GPIN1.0,
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PllUsb = ClkGpoutCtrlAuxsrc::CLKSRC_PLL_USB.0,
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Rosc = ClkGpoutCtrlAuxsrc::ROSC_CLKSRC.0,
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Xosc = ClkGpoutCtrlAuxsrc::XOSC_CLKSRC.0,
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@ -813,8 +818,8 @@ impl<'d, T: GpoutPin> Gpout<'d, T> {
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let base = match src {
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ClkGpoutCtrlAuxsrc::CLKSRC_PLL_SYS => pll_sys_freq(),
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ClkGpoutCtrlAuxsrc::CLKSRC_GPIN0 => gpin0_freq(),
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ClkGpoutCtrlAuxsrc::CLKSRC_GPIN1 => gpin1_freq(),
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// ClkGpoutCtrlAuxsrc::CLKSRC_GPIN0 => gpin0_freq(),
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// ClkGpoutCtrlAuxsrc::CLKSRC_GPIN1 => gpin1_freq(),
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ClkGpoutCtrlAuxsrc::CLKSRC_PLL_USB => pll_usb_freq(),
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ClkGpoutCtrlAuxsrc::ROSC_CLKSRC => rosc_freq(),
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ClkGpoutCtrlAuxsrc::XOSC_CLKSRC => xosc_freq(),
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Block a user