Add remaining stm32f4 timers
This commit is contained in:
Thales Fragoso
parent
9d895a6383
commit
fc7977bd9a
@ -26,7 +26,6 @@ use crate::interrupt::{CriticalSection, Mutex, OwnedInterrupt};
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// corresponds to the next period.
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// corresponds to the next period.
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//
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//
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// `period` is a 32bit integer, so It overflows on 2^32 * 2^15 / 32768 seconds of uptime, which is 136 years.
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// `period` is a 32bit integer, so It overflows on 2^32 * 2^15 / 32768 seconds of uptime, which is 136 years.
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fn calc_now(period: u32, counter: u16) -> u64 {
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fn calc_now(period: u32, counter: u16) -> u64 {
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((period as u64) << 15) + ((counter as u32 ^ ((period & 1) << 15)) as u64)
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((period as u64) << 15) + ((counter as u32 ^ ((period & 1) << 15)) as u64)
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}
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}
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@ -48,6 +47,13 @@ impl AlarmState {
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// TODO: This is sometimes wasteful, try to find a better way
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// TODO: This is sometimes wasteful, try to find a better way
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const ALARM_COUNT: usize = 3;
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const ALARM_COUNT: usize = 3;
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/// RTC timer that can be used by the executor and to set alarms.
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///
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/// It can work with Timers 2, 3, 4, 5, 9 and 12. Timers 9 and 12 only have one alarm available,
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/// while the others have three each.
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/// This timer works internally with a unit of 2^15 ticks, which means that if a call to
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/// [`embassy::time::Clock::now`] is blocked for that amount of ticks the returned value will be
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/// wrong (an old value). The current default tick rate is 32768 ticks per second.
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pub struct RTC<T: Instance> {
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pub struct RTC<T: Instance> {
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rtc: T,
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rtc: T,
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irq: T::Interrupt,
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irq: T::Interrupt,
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@ -240,6 +246,7 @@ pub trait Instance: sealed::Sealed + Sized + 'static {
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fn compare_clear_flag(&self, n: usize);
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fn compare_clear_flag(&self, n: usize);
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fn overflow_interrupt_status(&self) -> bool;
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fn overflow_interrupt_status(&self) -> bool;
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fn overflow_clear_flag(&self);
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fn overflow_clear_flag(&self);
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// This method should ensure that the values are really updated before returning
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fn set_psc_arr(&self, psc: u16, arr: u16);
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fn set_psc_arr(&self, psc: u16, arr: u16);
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fn stop_and_reset(&self);
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fn stop_and_reset(&self);
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fn start(&self);
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fn start(&self);
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@ -248,117 +255,251 @@ pub trait Instance: sealed::Sealed + Sized + 'static {
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fn pclk(clocks: &Clocks) -> u32;
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fn pclk(clocks: &Clocks) -> u32;
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}
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}
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mod tim2 {
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#[allow(unused_macros)]
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use super::*;
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macro_rules! impl_timer {
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use stm32f4xx_hal::pac::{RCC, TIM2};
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($module:ident: ($TYPE:ident, $INT:ident, $apbenr:ident, $enrbit:expr, $apbrstr:ident, $rstrbit:expr, $ppre:ident, $pclk: ident), 3) => {
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mod $module {
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use super::*;
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use stm32f4xx_hal::pac::{$TYPE, RCC};
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impl sealed::Sealed for TIM2 {}
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impl sealed::Sealed for $TYPE {}
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impl Instance for TIM2 {
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impl Instance for $TYPE {
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type Interrupt = interrupt::TIM2Interrupt;
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type Interrupt = interrupt::$INT;
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const REAL_ALARM_COUNT: usize = 3;
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const REAL_ALARM_COUNT: usize = 3;
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fn enable_clock(&self) {
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fn enable_clock(&self) {
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// NOTE(unsafe) It will only be used for atomic operations
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// NOTE(unsafe) It will only be used for atomic operations
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unsafe {
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unsafe {
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let rcc = &*RCC::ptr();
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let rcc = &*RCC::ptr();
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bb::set(&rcc.apb1enr, 0);
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bb::set(&rcc.$apbenr, $enrbit);
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bb::set(&rcc.apb1rstr, 0);
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bb::set(&rcc.$apbrstr, $rstrbit);
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bb::clear(&rcc.apb1rstr, 0);
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bb::clear(&rcc.$apbrstr, $rstrbit);
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}
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}
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}
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}
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fn set_compare(&self, n: usize, value: u16) {
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fn set_compare(&self, n: usize, value: u16) {
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// NOTE(unsafe) these registers accept all the range of u16 values
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// NOTE(unsafe) these registers accept all the range of u16 values
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match n {
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match n {
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0 => self.ccr1.write(|w| unsafe { w.bits(value.into()) }),
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0 => self.ccr1.write(|w| unsafe { w.bits(value.into()) }),
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1 => self.ccr2.write(|w| unsafe { w.bits(value.into()) }),
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1 => self.ccr2.write(|w| unsafe { w.bits(value.into()) }),
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2 => self.ccr3.write(|w| unsafe { w.bits(value.into()) }),
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2 => self.ccr3.write(|w| unsafe { w.bits(value.into()) }),
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3 => self.ccr4.write(|w| unsafe { w.bits(value.into()) }),
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3 => self.ccr4.write(|w| unsafe { w.bits(value.into()) }),
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_ => {}
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_ => {}
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}
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}
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}
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}
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fn set_compare_interrupt(&self, n: usize, enable: bool) {
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fn set_compare_interrupt(&self, n: usize, enable: bool) {
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if n > 3 {
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if n > 3 {
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return;
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return;
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}
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}
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let bit = n as u8 + 1;
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let bit = n as u8 + 1;
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unsafe {
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unsafe {
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if enable {
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if enable {
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bb::set(&self.dier, bit);
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bb::set(&self.dier, bit);
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} else {
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} else {
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bb::clear(&self.dier, bit);
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bb::clear(&self.dier, bit);
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}
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}
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}
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fn compare_interrupt_status(&self, n: usize) -> bool {
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let status = self.sr.read();
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match n {
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0 => status.cc1if().bit_is_set(),
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1 => status.cc2if().bit_is_set(),
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2 => status.cc3if().bit_is_set(),
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3 => status.cc4if().bit_is_set(),
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_ => false,
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}
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}
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fn compare_clear_flag(&self, n: usize) {
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if n > 3 {
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return;
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}
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let bit = n as u8 + 1;
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unsafe {
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bb::clear(&self.sr, bit);
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}
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}
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fn overflow_interrupt_status(&self) -> bool {
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self.sr.read().uif().bit_is_set()
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}
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fn overflow_clear_flag(&self) {
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unsafe {
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bb::clear(&self.sr, 0);
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}
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}
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fn set_psc_arr(&self, psc: u16, arr: u16) {
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// NOTE(unsafe) All u16 values are valid
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self.psc.write(|w| unsafe { w.bits(psc.into()) });
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self.arr.write(|w| unsafe { w.bits(arr.into()) });
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unsafe {
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// Set URS, generate update, clear URS
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bb::set(&self.cr1, 2);
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self.egr.write(|w| w.ug().set_bit());
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bb::clear(&self.cr1, 2);
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}
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}
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fn stop_and_reset(&self) {
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unsafe {
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bb::clear(&self.cr1, 0);
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}
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self.cnt.reset();
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}
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fn start(&self) {
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unsafe { bb::set(&self.cr1, 0) }
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}
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fn counter(&self) -> u16 {
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self.cnt.read().bits() as u16
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}
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fn ppre(clocks: &Clocks) -> u8 {
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clocks.$ppre()
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}
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fn pclk(clocks: &Clocks) -> u32 {
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clocks.$pclk().0
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}
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}
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}
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}
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}
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}
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};
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fn compare_interrupt_status(&self, n: usize) -> bool {
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($module:ident: ($TYPE:ident, $INT:ident, $apbenr:ident, $enrbit:expr, $apbrstr:ident, $rstrbit:expr, $ppre:ident, $pclk: ident), 1) => {
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let status = self.sr.read();
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mod $module {
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match n {
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use super::*;
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0 => status.cc1if().bit_is_set(),
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use stm32f4xx_hal::pac::{$TYPE, RCC};
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1 => status.cc2if().bit_is_set(),
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2 => status.cc3if().bit_is_set(),
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impl sealed::Sealed for $TYPE {}
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3 => status.cc4if().bit_is_set(),
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_ => false,
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impl Instance for $TYPE {
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type Interrupt = interrupt::$INT;
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const REAL_ALARM_COUNT: usize = 1;
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fn enable_clock(&self) {
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// NOTE(unsafe) It will only be used for atomic operations
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unsafe {
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let rcc = &*RCC::ptr();
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bb::set(&rcc.$apbenr, $enrbit);
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bb::set(&rcc.$apbrstr, $rstrbit);
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bb::clear(&rcc.$apbrstr, $rstrbit);
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}
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}
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fn set_compare(&self, n: usize, value: u16) {
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// NOTE(unsafe) these registers accept all the range of u16 values
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match n {
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0 => self.ccr1.write(|w| unsafe { w.bits(value.into()) }),
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1 => self.ccr2.write(|w| unsafe { w.bits(value.into()) }),
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_ => {}
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}
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}
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fn set_compare_interrupt(&self, n: usize, enable: bool) {
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if n > 1 {
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return;
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}
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let bit = n as u8 + 1;
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unsafe {
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if enable {
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bb::set(&self.dier, bit);
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} else {
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bb::clear(&self.dier, bit);
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}
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}
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}
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fn compare_interrupt_status(&self, n: usize) -> bool {
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let status = self.sr.read();
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match n {
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0 => status.cc1if().bit_is_set(),
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1 => status.cc2if().bit_is_set(),
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_ => false,
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}
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}
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fn compare_clear_flag(&self, n: usize) {
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if n > 1 {
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return;
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}
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let bit = n as u8 + 1;
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unsafe {
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bb::clear(&self.sr, bit);
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}
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}
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fn overflow_interrupt_status(&self) -> bool {
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self.sr.read().uif().bit_is_set()
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}
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fn overflow_clear_flag(&self) {
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unsafe {
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bb::clear(&self.sr, 0);
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}
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}
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fn set_psc_arr(&self, psc: u16, arr: u16) {
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// NOTE(unsafe) All u16 values are valid
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self.psc.write(|w| unsafe { w.bits(psc.into()) });
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self.arr.write(|w| unsafe { w.bits(arr.into()) });
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unsafe {
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// Set URS, generate update, clear URS
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bb::set(&self.cr1, 2);
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self.egr.write(|w| w.ug().set_bit());
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bb::clear(&self.cr1, 2);
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}
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}
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fn stop_and_reset(&self) {
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unsafe {
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bb::clear(&self.cr1, 0);
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}
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self.cnt.reset();
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}
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fn start(&self) {
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unsafe { bb::set(&self.cr1, 0) }
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}
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fn counter(&self) -> u16 {
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self.cnt.read().bits() as u16
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}
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fn ppre(clocks: &Clocks) -> u8 {
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clocks.$ppre()
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}
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fn pclk(clocks: &Clocks) -> u32 {
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clocks.$pclk().0
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}
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}
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}
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}
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}
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};
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fn compare_clear_flag(&self, n: usize) {
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if n > 3 {
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return;
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}
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let bit = n as u8 + 1;
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unsafe {
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bb::clear(&self.sr, bit);
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}
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}
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fn overflow_interrupt_status(&self) -> bool {
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self.sr.read().uif().bit_is_set()
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}
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fn overflow_clear_flag(&self) {
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unsafe {
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bb::clear(&self.sr, 0);
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}
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}
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fn set_psc_arr(&self, psc: u16, arr: u16) {
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// NOTE(unsafe) All u16 values are valid
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self.psc.write(|w| unsafe { w.bits(psc.into()) });
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self.arr.write(|w| unsafe { w.bits(arr.into()) });
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unsafe {
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// Set URS, generate update, clear URS
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bb::set(&self.cr1, 2);
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self.egr.write(|w| w.ug().set_bit());
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bb::clear(&self.cr1, 2);
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}
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}
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fn stop_and_reset(&self) {
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unsafe {
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bb::clear(&self.cr1, 0);
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}
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self.cnt.reset();
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}
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fn start(&self) {
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unsafe { bb::set(&self.cr1, 0) }
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}
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fn counter(&self) -> u16 {
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self.cnt.read().bits() as u16
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}
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fn ppre(clocks: &Clocks) -> u8 {
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clocks.ppre1()
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}
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fn pclk(clocks: &Clocks) -> u32 {
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clocks.pclk1().0
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}
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}
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}
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}
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#[cfg(not(feature = "stm32f410"))]
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impl_timer!(tim2: (TIM2, TIM2Interrupt, apb1enr, 0, apb1rstr, 0, ppre1, pclk1), 3);
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#[cfg(not(feature = "stm32f410"))]
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impl_timer!(tim3: (TIM3, TIM3Interrupt, apb1enr, 1, apb1rstr, 1, ppre1, pclk1), 3);
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#[cfg(not(feature = "stm32f410"))]
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impl_timer!(tim4: (TIM4, TIM4Interrupt, apb1enr, 2, apb1rstr, 2, ppre1, pclk1), 3);
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impl_timer!(tim5: (TIM5, TIM5Interrupt, apb1enr, 3, apb1rstr, 3, ppre1, pclk1), 3);
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impl_timer!(tim9: (TIM9, TIM1_BRK_TIM9Interrupt, apb2enr, 16, apb2rstr, 16, ppre2, pclk2), 1);
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#[cfg(not(any(feature = "stm32f401", feature = "stm32f410", feature = "stm32f411")))]
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impl_timer!(tim12: (TIM12, TIM8_BRK_TIM12Interrupt, apb1enr, 6, apb1rstr, 6, ppre1, pclk1), 1);
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