Matous Hybl
015cad84dd
Initial support for STM32F767ZI.
2021-10-26 17:33:28 +02:00
bors[bot]
01e5376b25
Merge #456
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456: Fix L4 clock setup for MSI and PLL to allow RNG operation r=Dirbaio a=lulf
Example is tested on STM32L475VG.
Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2021-10-26 11:59:14 +00:00
Ulf Lilleengen
e55726964d
Fix clock setup for MSI and PLL to allow RNG opereation
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Add RNG example using PLL as clock source.
2021-10-26 13:45:53 +02:00
Ulf Lilleengen
f8ebc967a9
Add implementation of async trait for STM32 I2C v2
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* Add DMA read implementation for I2C v2
* Add example using DMA for I2C
2021-10-21 12:30:02 +02:00
Ulf Lilleengen
d2a79a46c5
Configure the correct pin instances
2021-10-21 11:57:00 +02:00
Tobias Pisani
43a7226d8b
inline FRE register check for SPI on F1
2021-10-11 23:33:32 +02:00
Tobias Pisani
2cbb8a7ece
Add AFType::Input for input configurations.
2021-10-11 22:57:21 +02:00
Tobias Pisani
259e84e68e
Make miso/mosi optional when for unidirectional spi
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Only suported on v1 currently
2021-10-11 22:57:21 +02:00
Tobias Pisani
c44bed300b
Correctly set alternate function for stm32f1 gpios
2021-10-11 22:57:21 +02:00
Tobias Pisani
091e7e1f98
Generate USART pin definitions for stm32f1
2021-10-11 22:57:21 +02:00
Tobias Pisani
39880de958
partial alternate function configuration on STM32f1
2021-10-11 22:57:10 +02:00
Tobias Pisani
f9a576d13d
feat: Add spi support for STM32F1 variants
2021-10-11 22:39:48 +02:00
Ben Gamari
006bbea51a
stm32/adc: Add IN0 channel
2021-09-29 00:32:40 -04:00
Ben Gamari
5a38cc2140
stm32/dac: Ensure that clock is enabled
2021-09-29 00:32:40 -04:00
Ben Gamari
0b9961584b
stm32/adc: Ensure that clock is enabled
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Sadly due to the inconsistency in clocking configuration across devices
we cannot use RccPeripheral.
2021-09-29 00:32:40 -04:00
Ben Gamari
573e6ec373
stm32g0: Add support for low-power run
2021-09-28 21:19:10 -04:00
Ben Gamari
794798e225
stm32g0: Add support for HSI divider
2021-09-28 21:19:10 -04:00
Ben Gamari
aa4069fe10
stm32/adc: Fix ADC support for STM32G0
2021-09-28 21:19:10 -04:00
Ben Gamari
e2e0464d04
stm32/adc: Factor out conversion logic
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Also guard errata workaround correctly.
2021-09-28 18:00:05 -04:00
Mariusz Ryndzionek
ce361abb1b
Changing the casts (code review request)
2021-09-28 18:31:04 +02:00
Mariusz Ryndzionek
bce909ec1e
Initial STM32F1 family support with two examples for STM32F103C8 (Blue Pill)
2021-09-28 18:31:04 +02:00
Joshua Salzedo
ab60cfd64b
Patch additional regressions
2021-09-27 15:48:56 -07:00
Joshua Salzedo
67e2f9159c
set moder::ALTERNATE last when configuring pins to AF modes.
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- as per STM32F4xx_hal's impl
2021-09-27 15:27:43 -07:00
Joshua Salzedo
07e20a7443
Pub use version-specific CRC symbols, not just the CRC struct.
2021-09-27 11:17:31 -07:00
Joshua Salzedo
a26ffeb84b
Cargo fmt
2021-09-27 10:49:32 -07:00
Joshua Salzedo
e36d4f460a
Fix variable names in crc_v2/v3.
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removed `reclaim` in crc_v1.
used write instead of modify.
renamed `init` to `reset` in crc_v1.
2021-09-27 10:46:09 -07:00
Joshua Salzedo
43ad28b9f9
Use unborrow for CRC constructor
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sort feature gates
fix repetition in CRC config names
2021-09-27 10:38:55 -07:00
Joshua Salzedo
7392e33ad5
cargo fmt
2021-09-26 19:20:21 -07:00
Joshua Salzedo
e67af514e9
Fix v2/3 module paths
2021-09-26 19:15:54 -07:00
Joshua Salzedo
642b0825a6
V3 is just an extension of V2, merge modules.
2021-09-26 19:14:08 -07:00
Joshua Salzedo
f9ff5336d4
Merge all of the crc_v2 configurations into a single modify call
2021-09-26 18:46:19 -07:00
Joshua Salzedo
8fac444c4e
Flesh out v2 config writes
2021-09-26 18:39:55 -07:00
Joshua Salzedo
afef19d813
Start work towards CRC_V2
2021-09-26 18:26:20 -07:00
Joshua Salzedo
7899d73359
Expose read so the value can be obtained without a write.
2021-09-26 17:28:58 -07:00
Joshua Salzedo
c892289b2c
Actually export CRC
2021-09-26 17:26:33 -07:00
Joshua Salzedo
24dea91f5a
Fix interface changes
2021-09-26 17:24:48 -07:00
Joshua Salzedo
e18a27eea2
First pass at CRC_V1
2021-09-26 16:46:17 -07:00
Joshua Salzedo
e527892d89
Start work on CRC_v1
2021-09-26 16:29:22 -07:00
Dario Nieuwenhuis
f8d833e0c5
Merge pull request #403 from mryndzionek/af_type
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Small adjustment to 'set_as_af' interface
2021-09-24 20:20:45 +02:00
Mariusz Ryndzionek
e4b37c40c9
Code review request - moving OutputType to mod sealed
2021-09-24 19:56:48 +02:00
Mariusz Ryndzionek
d371298a27
Small adjustment to 'set_as_af' interface
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Small adjustment to 'set_as_af' interface - v2
2021-09-24 18:39:07 +02:00
Vincent Stakenburg
7d6d274d55
Add MSI and PLL clock source for L4
2021-09-24 18:27:39 +02:00
Ulf Lilleengen
b6fc19182b
Add pwr for L1 and update RCC to new reg block
2021-09-23 14:51:16 +02:00
Ulf Lilleengen
9d45018077
Refactor V1 SPI
2021-09-21 14:50:23 +02:00
Ulf Lilleengen
c79485c286
Support for STM32L1
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* Add RCC
* Fix more issues with dash in chip names
* Update stm32-data version
* Add blinky and spi example
2021-09-21 14:50:23 +02:00
Ulf Lilleengen
fb697a2657
Updates
2021-09-15 12:46:20 +02:00
Dario Nieuwenhuis
ead987245d
embassy: Refactor module structure to remove kitchen-sink util.
2021-09-11 02:35:35 +02:00
Adam Greig
14fa6c2760
STM32H7: Ethernet: Disable RA in MAC filtering, fix order of MACA0 register writes.
2021-09-06 23:16:43 +01:00
Bob McWhirter
d4bf78a0c1
Don't set SAF=true, do set RA=true for Ethernet.
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Source-Address-Filtering is not helping the board to receive packets.
For unknown reasons, the Receive-All is required, when in theory
it should not be required. Until we figure it out, follow the
stm32h7xx-hal example of setting RA=true.
2021-09-06 14:21:26 -04:00
Dario Nieuwenhuis
eff8ae9c4d
Merge pull request #381 from lulf/stm32wl55-subghz
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Add HAL for SubGhz peripheral for STM32 WL series
2021-09-06 00:58:42 +02:00
