Commit Graph

735 Commits

Author SHA1 Message Date
Matous Hybl
371f3ef419 Add ADC support for H7 2022-04-12 22:25:00 +02:00
Michal Srb
c1914a477d stm32/dac: Check proper channel 2022-04-12 12:49:06 +02:00
Philip A Reimer
d90ecbbe40 add more clock options for l4 and l5 2022-04-11 19:11:02 -06:00
Philip A Reimer
d8860c0b80 add stm32l4 hsi48 and usb example 2022-04-09 14:55:03 -06:00
Dario Nieuwenhuis
8b757e1aec Add stm32wlexx support 2022-04-08 03:43:58 +02:00
Dario Nieuwenhuis
0c07d03754 Add missing stm32wl/stm32wb chips except stm32wle 2022-04-08 03:15:27 +02:00
Dario Nieuwenhuis
50ff63ab88 Add STM32L5 support. 2022-04-08 03:11:38 +02:00
Matous Hybl
eb6910fa86 Reexport unborrow macro in HALs 2022-04-07 12:57:02 +02:00
Dario Nieuwenhuis
aee19185b7 Add more docserver metadata. 2022-04-05 21:05:09 +02:00
Philip A Reimer
1f59f8e7d0 add pllsai1 and allow for 120Mhz clock on stm32l4+ 2022-04-01 22:42:43 -06:00
chemicstry
d052631118 Fix STM32 timer interrupt bug 2022-03-30 00:27:33 +03:00
Joonas Javanainen
83211c2b61
Add workaround for F2 errata 2022-03-27 19:00:36 +03:00
Joonas Javanainen
a608d0deaf
Add minimal STM32F2 RCC
No support for PLL or other clocks than SYSCLK/AHB/APB1/APB2
2022-03-27 18:40:49 +03:00
Joonas Javanainen
08e6a996bc
Regenerate embassy-stm32 features 2022-03-21 00:19:36 +02:00
bors[bot]
37ada65a33
Merge #669
669: Add SDMMC v1 and SDIO support r=Dirbaio a=chemicstry

SDMMC v2 peripheral is an extension of SDMMC v1 (or SDIO) so I managed to reuse most of the code, with some cfg's.

Apart from small differeces in registers, the biggest change is that v2 uses internal DMA, while v1 has to use shared DMA peripheral. This makes code a bit uglier, because DMA channel for v1 has to be passed around. Not sure if it's possible to make it any cleaner.

This also adds `TransferOptions` structure to DMA, because SDMMC v1 requires setting peripheral flow control and burst transfers. Let me know if some alternative way would be prefered.

I tested this on STM32F429ZIT6 (with sd card) and STM32H745ZIT6 (with oscilloscope).

Depends on: https://github.com/embassy-rs/stm32-data/pull/130

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-03-20 20:19:58 +00:00
bors[bot]
f0a071790d
Merge #673
673: Inline GPIO functions r=Dirbaio a=nviennot

All GPIO functions are monomorphized (per pin). Inlining these make the ROM smaller when using opt-level="z"

Co-authored-by: Nicolas Viennot <nicolas@viennot.biz>
2022-03-19 20:34:07 +00:00
Nicolas Viennot
4aba87f983 Inline GPIO functions
All GPIO functions are monomorphized (per pin). Inlining these make the
ROM smaller when using opt-level="z"
2022-03-19 14:06:11 -04:00
chemicstry
bdeb537ffa Fix compile for stm32wb 2022-03-18 01:33:39 +02:00
chemicstry
b30a42aff8 Fix RCC safety and add reset to DAC 2022-03-18 01:16:07 +02:00
chemicstry
ca88ace98d Reset peripherals on enable 2022-03-18 00:46:46 +02:00
chemicstry
d26b751edc Add comments 2022-03-17 19:41:44 +02:00
chemicstry
051c6350ea Make UART futures Send 2022-03-17 18:23:47 +02:00
chemicstry
c24d482d51 Fix DMA channels 2022-03-17 01:54:56 +02:00
chemicstry
24a9e19062 More cleanup 2022-03-17 01:12:29 +02:00
chemicstry
9d71acc49e Cleanup 2022-03-16 23:55:07 +02:00
chemicstry
224071f08e Add F7 example 2022-03-16 23:44:02 +02:00
chemicstry
ea467e0acb Rename DMA trait 2022-03-16 20:30:57 +02:00
chemicstry
8a8e5c4b73 Fix SDMMC v2 and add H7 example 2022-03-16 20:20:39 +02:00
chemicstry
48fc48ea7d Fix BDMA 2022-03-16 19:41:34 +02:00
chemicstry
bf4a38ac06 Use RCC frequency instead of config 2022-03-16 19:09:37 +02:00
chemicstry
6d547b1143 SDIO working on stm32f4 2022-03-16 18:52:27 +02:00
chemicstry
34b5175d2c Add more options to DMA 2022-03-16 18:52:06 +02:00
chemicstry
2d224cf6a0 Update 2022-03-15 19:58:19 +02:00
Ulf Lilleengen
e09bde9345 Add support for splitting stm32 usart into TX and RX
* Keeps existing API for usart, but wraps it in Tx and Rx sub-types
* Adds split() method similar to nRF for getting indepdendent TX and RX
  parts
* Implements e-h traits for TX and RX types
* Add stm32h7 example
2022-03-15 10:35:37 +01:00
Dario Nieuwenhuis
1dc618f0e4 stm32/spi: fix blocking transfer hanging after async. 2022-03-15 04:13:33 +01:00
Grant Miller
49ef19c0b2 stm32/spi: Clear rx fifo in blocking methods 2022-03-14 21:55:37 -05:00
Dario Nieuwenhuis
059b164234 stm32/spi: do not clear rxfifo in SPIv3, the hw already does it. 2022-03-15 02:37:08 +01:00
Dario Nieuwenhuis
4579192832 stm32/spi: fix hang in SPIv3 by not waiting for rxfifo empty in finish_dma. 2022-03-15 02:36:34 +01:00
Dario Nieuwenhuis
306110f56e stm32/spi: implement async trasnfer_in_place 2022-03-15 00:40:48 +01:00
Grant Miller
f1d6c95205 rustfmt 2022-03-14 18:22:41 -05:00
Grant Miller
71632648c7 Fix zero-length-slice bugs 2022-03-14 18:14:55 -05:00
Grant Miller
15c533fe2a Fix async write bug 2022-03-14 18:04:31 -05:00
Grant Miller
6e00c58854 Make all functions generic over word size 2022-03-14 16:53:50 -05:00
Grant Miller
f0b62bc8e0 Use const REGS 2022-03-14 15:56:08 -05:00
Grant Miller
482ffea4dd Finish unification 2022-03-14 15:56:08 -05:00
Grant Miller
406b1b3dd2 Finish matching versions 2022-03-14 15:56:08 -05:00
Grant Miller
7cd6f00a90 Add set_txdmaen and set_rxdmaen functions 2022-03-14 15:56:08 -05:00
Grant Miller
444b37fcdf Add flush_rx_fifo function 2022-03-14 15:56:08 -05:00
Grant Miller
683c11f399 Call set_word_size before disabling SPE 2022-03-14 15:56:08 -05:00
Dario Nieuwenhuis
9bad9365dc Update rust nightly, embedded-hal 1.0, embedded-hal-async. 2022-03-11 00:38:07 +01:00
Dario Nieuwenhuis
77841a4676 stm32/dma: panic on DMA error. 2022-03-09 03:19:05 +01:00
Grant Miller
8f7bb570ae Ignore BDMA1 in H7 2022-03-08 16:46:42 -06:00
Grant Miller
8c45c98e41 stm32: Refactor DMA interrupts
Previously, every dma interrupt handler called the same `on_irq`
function which had to check the state of every dma channel.

Now, each dma interrupt handler only calls an `on_irq` method for its
corresponding channel or channels.
2022-03-08 14:18:31 -06:00
Timo Kröger
372b71890d [can] Typo fix: l7 -> f7 2022-03-05 09:46:06 +01:00
Timo Kröger
d6d25e6470 [can] cfgs for naming inconsistencies
Approach is similar to USB OTG.
STM32L49x and STML4Ax have CAN1 and CAN2.
All others STM32L4xx do only have CAN1.
STM32F72x and STM32F73x are the only F7 devices with only CAN1.
2022-03-05 09:46:06 +01:00
Timo Kröger
6929350552 [can] Update macrotable comment
The chip description are corrected in:
https://github.com/embassy-rs/stm32-data/pull/123
2022-03-05 09:46:06 +01:00
Timo Kröger
4c30543938 [can] Do not use wildcard reexport for bxcan 2022-03-05 09:46:06 +01:00
bors[bot]
9ebf7eee6d
Merge #652 #653
652: Use new stm32-data registers and fix AHB clock calculation r=Dirbaio a=msamsonoff

This is the follow-on to my PR against stm32-data that added new register enums for the G0. I have updated the G0 RCC module to use those new enums.

I have also fixed an issue with the calculation of the AHB clock rate. 32 is not available as an AHB prescaler. The sequence jumps from 16 to 64. The original bit shifting math did not account for this gap. I have replaced it with a `match` instead.

653: Fixes for rustdoc building. r=Dirbaio a=Dirbaio



Co-authored-by: Matthew W. Samsonoff <matt.samsonoff@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-03-04 17:07:04 +00:00
Dario Nieuwenhuis
609975f821 rustfmt 2022-03-04 18:04:12 +01:00
Matthew W. Samsonoff
047ff9a2f2 Use new stm32-data registers and fix AHB clock calculation
The original code for calculating the AHB clock did not account for the gap in
prescaler values (32 is not an available value.) The bit shifting and math has
been replaced by a `match`.
2022-03-04 18:03:55 +01:00
Dario Nieuwenhuis
265cd1115b stm32: allow unused macrotables. 2022-03-04 18:03:41 +01:00
Dario Nieuwenhuis
44096358a2 docs: add metadata.embassy_docs to cargo tomls. 2022-03-04 18:03:41 +01:00
Dario Nieuwenhuis
53d9a0b516 stm32: exclude spammy files from docs by prefixing with _.
These files end up containing chip-specific info, so they deduplicate
really badly when building docs for all 1200 chips.

The doc generator removes files starting with `_`.
2022-03-04 18:03:41 +01:00
Dario Nieuwenhuis
94b232cf88 docs: prevent inline doc spam for reexports. 2022-03-04 18:03:41 +01:00
Matous Hybl
0172ca5b81 stm32: Add support for using TIM12 and TIM15 as time driver 2022-02-28 19:20:22 +01:00
Matous Hybl
a88c5e716e stm32: Register access for timers now doesn't require self 2022-02-28 16:20:42 +01:00
Dario Nieuwenhuis
dd828a7a92 stm32: move macrotables to embassy-stm32 build.rs 2022-02-26 03:23:09 +01:00
Dario Nieuwenhuis
e6299549a0 stm32/i2c: use one static per instance instead of an array. 2022-02-26 01:23:17 +01:00
Dario Nieuwenhuis
8d46d31824 stm32/dbgmcu: do not use macrotable. 2022-02-26 01:20:42 +01:00
Timo Kröger
48f700b35c stm32 usart: Fix RX interrupt flag handling
* On v1 interrupts cannot be cleared individually.
  Instead they are cleared implicitly by reading or writing DR (which we do now).
* Multiple error flags can be set at the same time:
  Handle them all in one go intstead of re-entering the ISR for each one so that
  we do not lose any error flags on v1 hardware.
* Wake when the RX buffer becomes full: This allows fast running chips to pull data
  from the buffer before receiving the next byte.
2022-02-25 14:32:39 +01:00
Dario Nieuwenhuis
0ad7a3aa6f stm32: fix chips without dbgmcu (wl55 cm0 core) 2022-02-25 01:16:23 +01:00
Dario Nieuwenhuis
ea5cd19c30 stm32: fix build for h7ab 2022-02-24 06:28:29 +01:00
Dario Nieuwenhuis
1ff80f8438 stm32/mco: fix on h7ab 2022-02-24 06:28:29 +01:00
Dario Nieuwenhuis
2a246be06e stm32/time_driver: use trait impls from the main timer mod. 2022-02-24 06:28:29 +01:00
Dario Nieuwenhuis
e8ca5f9b04 stm32/rcc: fix build on l0 chips without CRS 2022-02-24 06:28:29 +01:00
Dario Nieuwenhuis
bf80504ac7 stm32: centralize gpio reg access in the gpio module. 2022-02-24 02:49:20 +01:00
Dario Nieuwenhuis
1b3c34b923 stm32/gpio: fix wrong conf for AF input. 2022-02-24 00:37:15 +01:00
Dario Nieuwenhuis
17e77ede3f stm32f1: fix wrong AF type in uart, can. 2022-02-24 00:37:15 +01:00
Dario Nieuwenhuis
052f370de9 stm32: move ADC, DAC pin impls to build.rs 2022-02-23 20:21:28 +01:00
Dario Nieuwenhuis
30ce71127a stm32: move MCO pin impls to build.rs 2022-02-23 19:54:46 +01:00
Dario Nieuwenhuis
1e69a8c484 stm32: move pin trait impls from macrotables to build.rs 2022-02-23 19:54:46 +01:00
Dario Nieuwenhuis
b4abb1f5c2 stm32: move dma trait impls from macrotables to build.rs 2022-02-23 19:16:37 +01:00
Dario Nieuwenhuis
2abb04d4d1 stm32/rcc: fix f3 build failure. 2022-02-23 03:42:46 +01:00
Dario Nieuwenhuis
39d06b59cd Update stm32-data 2022-02-14 02:12:06 +01:00
bors[bot]
eb922c4655
Merge #608
608: stm32f4: add adc + example r=Dirbaio a=ain101

Example tested on stm32f407vg Discovery Board.
minimal adc: no vref, dma, complex sequence

Co-authored-by: Frederik <frederik@frederik.at>
2022-02-13 11:44:59 +00:00
Frederik
7a3d34c1ed fix build for stm32f410tb 2022-02-12 23:56:50 +01:00
Frederik
6f0488cbe7 remove unnecessary mod 2022-02-12 23:55:58 +01:00
Dario Nieuwenhuis
340eb4eead stm32: add rust stable support 2022-02-12 02:45:52 +01:00
bors[bot]
f2eb438905
Merge #615
615: rp: remove OptionalPin r=Dirbaio a=Dirbaio

Mirror of https://github.com/embassy-rs/embassy/pull/605 for rp2040

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-02-12 00:46:40 +00:00
Dario Nieuwenhuis
4a75475cfc stm32: remove unused sealed::OptionalPin 2022-02-12 01:34:09 +01:00
Dario Nieuwenhuis
20e14b8edb embassy, embassy-nrf: add nightly Cargo feature to gate nightly-only features. 2022-02-12 01:16:31 +01:00
Dario Nieuwenhuis
6c925b2342 blocking_mutex: refactor to work on stable. No GATs, and can be constructed in const. 2022-02-12 01:16:31 +01:00
Frederik
e4f240823d adc cleanup retval 2022-02-11 17:48:32 +01:00
Frederik
7a3d28ad00 stm32f4: add adc + example
Example tested on stm32f407vg Discovery Board.
minimal adc: no vref, dma, complex sequence
2022-02-10 23:28:41 +01:00
Dario Nieuwenhuis
b99ab3d5d9 stm32: Add standard crate-wide macros for pin/dma traits, switch all drivers to use them. 2022-02-10 21:38:03 +01:00
Dario Nieuwenhuis
a8bd3ab952 Add missing + 'd on unborrows. 2022-02-10 16:06:42 +01:00
Dario Nieuwenhuis
550da471be stm32: Remove OptionalPin
The idea behind OptionalPin has a few problems:

- you need to impl the signal traits for NoPin which is a bit weird https://github.com/embassy-rs/embassy/blob/master/embassy-stm32/src/dcmi.rs#L413-L416
- you can pass any combination of set/unset pins, which needs checking at runtime  https://github.com/embassy-rs/embassy/blob/master/embassy-stm32/src/dcmi.rs#L130

The replacement is to do multiple `new` constructors for each combination of pins you want to take.
2022-02-10 02:38:10 +01:00
bors[bot]
1d265b73b2
Merge #601
601: [part 1/n] Change macrotables to build.rs codegen r=lulf a=Dirbaio

This PR replaces the "macrotables" (the macros like `stm32_data::peripherals!`) with a `const METADATA`.

Macrotables had some problems:

- Hard to debug
- Somewhat footgunny (typo the "pattern" and then nothing matches and the macro now expands to nothing, silently!)
- Limited power
  - Can't count, so we had to add a [special macrotable for that](f50f3f0a73/embassy-stm32/src/dma/bdma.rs (L26)).
  - Can't remove duplicates, so we had to fallback to [Rust code in build.rs](f50f3f0a73/embassy-stm32/build.rs (L105-L145))
  - Can't include the results as a listto another macro, so again [build.rs](https://github.com/embassy-rs/embassy/blob/master/embassy-stm32/build.rs#L100-L101).

They work fine for the 95% of cases, but for the remaining 5% we need Rust code in build.rs. So we might as well do everything with Rust code, so everything is consistent.

The new approach generates a `const METADATA: Metadata = Metadata { ... }` with [these structs](https://github.com/embassy-rs/embassy/blob/unmacrotablize/stm32-metapac-gen/src/assets/metadata.rs) in `stm32-metapac`. `build.rs` can then read that and generate whatever code.


Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-02-09 15:27:35 +00:00
bors[bot]
d91bd0b9a6
Merge #602
602: Add stm32 USB OTG peripherals r=Dirbaio a=chemicstry

Fixes #557. This is similar to #580, but for synopsys IP.

I could add examples to other chips, but I have no way of testing them. The F4 example is tested and working.

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-02-09 00:29:00 +00:00
chemicstry
10981ee809 Cleanup 2022-02-09 02:10:54 +02:00