Commit Graph

5411 Commits

Author SHA1 Message Date
Ulf Lilleengen
eb23733767 Ignore compiling rust code 2022-06-15 10:44:15 +02:00
Ulf Lilleengen
72eb16b46d Add missing documentation for all public modules and types 2022-06-15 10:24:36 +02:00
Ulf Lilleengen
aaebea00eb Ensure links get formatted correctly in cargo doc 2022-06-15 10:24:18 +02:00
Ulf Lilleengen
f8f56c926d Include README.md in crate documentation 2022-06-15 09:06:18 +02:00
Ulf Lilleengen
746bc75a8e FIx broken link warnings 2022-06-15 09:05:48 +02:00
Ulf Lilleengen
faa59efbf6 Cargo fmt 2022-06-15 09:01:22 +02:00
Ulf Lilleengen
3696226fe8 Sync subghz peripheral support with stm32wlxx-hal 2022-06-14 16:27:42 +02:00
bors[bot]
624e46ccfb
Merge #809
809: Allow compiling usb-serial without defmt r=lulf a=lulf



Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-06-13 12:46:39 +00:00
Ulf Lilleengen
0c423cc901 Allow compiling usb-serial without defmt 2022-06-13 14:45:53 +02:00
bors[bot]
db685c0404
Merge #808
808: Add rustfmt.toml with some nice settings. r=lulf a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-06-13 07:22:04 +00:00
Dario Nieuwenhuis
a8703b7598 Run rustfmt. 2022-06-12 22:22:31 +02:00
Dario Nieuwenhuis
6199bdea71 Add rustfmt.toml with some nice settings. 2022-06-12 22:15:28 +02:00
bors[bot]
fff0a03fe0
Merge #806
806: Add embassy-cortex-m crate. r=Dirbaio a=Dirbaio

- Move Interrupt and InterruptExecutor from `embassy` to `embassy-cortex-m`.
- Move Unborrow from `embassy` to `embassy-hal-common` (nothing in `embassy` requires it anymore)
- Move PeripheralMutex from `embassy-hal-common` to `embassy-cortex-m`.

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-06-12 19:49:15 +00:00
Dario Nieuwenhuis
5085100df2 Add embassy-cortex-m crate.
- Move Interrupt and InterruptExecutor from `embassy` to `embassy-cortex-m`.
- Move Unborrow from `embassy` to `embassy-hal-common` (nothing in `embassy` requires it anymore)
- Move PeripheralMutex from `embassy-hal-common` to `embassy-cortex-m`.
2022-06-12 21:45:38 +02:00
bors[bot]
6b3499a5c8
Merge #807
807: Rename channel to mpmc r=huntc a=huntc

I've renamed the channel module for the MPMC as `mpmc`. There was a previous debate about this, but I feel that the strategy here avoids importing `channel::channel`. The change leaves `signal::Signal`, but I think that's ok. It is all a bit subjective of course. The bottom line for me is that I really like the term `mpmc` - it means something to me and aligns with broader naming e.g. in Tokio.

Co-authored-by: huntc <huntchr@gmail.com>
2022-06-12 06:27:11 +00:00
huntc
99d19c7dcf Rename channel to mpmc
I've renamed the channel module for the MPMC as mpmc. There was a previous debate about this, but I feel that the strategy here avoids importing `channel::channel`. The change leaves `signal::Signal`, but I think that's ok. It is all a bit subjective of course. The bottom line for me is that I really like the term mpmc - it means something to me and aligns with broader naming e.g. in Tokio.
2022-06-12 15:16:56 +10:00
Dario Nieuwenhuis
db344c2bda
common/PeripheralMutex: remove unsafe API. (#802)
Following the project's decision that "leak unsafe" APIs are not marked as "unsafe",
update PeripheralMutex to accept non-'static state without unsafe.

Fixes #801
2022-06-09 21:28:13 +02:00
bors[bot]
77c7d8f31b
Merge #797
797: Use correct index and bank for stm32 flash r=Dirbaio a=lulf

The page index was wrong because it doesn't take FLASH_BASE into account. 

For l4, the page index register also depends on a bank selection register.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-06-07 14:09:54 +00:00
Ulf Lilleengen
7d64f5cda7 Use correct index and bank 2022-06-07 15:59:22 +02:00
bors[bot]
bf09017032
Merge #796
796: nrf/twim: allow zero length transfers. r=Dirbaio a=Dirbaio

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-06-07 12:54:09 +00:00
Dario Nieuwenhuis
2be36122c7 nrf/twim: allow zero length transfers. 2022-06-07 14:52:45 +02:00
bors[bot]
c212f30be0
Merge #709
709: embassy-usb stm32 r=Dirbaio a=Dirbaio

TODO

- [x] Add cfgs for EP_COUNT, EP_MEMORY_ADDR. -- ended up doing it in stm32-data
- [x] Auto-enable PWR USV in stm32l5,
- [x] Auto-enable PWR on other families that need it -- didn't find any
- [ ] ~~Assert at runtime that RCC has valid 48Mhz clock?~~ -- won't do it yet, too messy without rcc cleanup
- [x] Tested on STM32L5
- [x] Tested on STM32F303ZE
- [x] Tested on STM32F103c8
- [x] Fix duplicated irqs on STM32F303 in stm32data, remove workaround in embassy-stm32
- [x] Test HID example
- [x] Test NCM example


Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-06-07 02:01:43 +00:00
Dario Nieuwenhuis
3e4bead321 stm32: add USB driver. 2022-06-07 03:29:00 +02:00
bors[bot]
ad6943adb3
Merge #795
795: Update stm32-metapac. r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-06-06 22:35:47 +00:00
Dario Nieuwenhuis
0aa73f58e2 Update stm32-metapac. 2022-06-07 00:28:26 +02:00
bors[bot]
62add4b2ab
Merge #792 #794
792: Add example for using a Signal. r=Dirbaio a=hydra

I didn't find an example, so I created one for the STM32H7.  Code based on the nrf mutex.rs example.

794: Fix F1 compilation by implementig AF pullup r=Dirbaio a=chemicstry

Embassy fails to compile on `STM32F103RET6`, because `set_as_af_pull` function is missing for GPIOv1:

```
error[E0599]: no method named `set_as_af_pull` found for mutable reference `&mut CLK` in the current scope
    --> C:\Users\chemi\.cargo\git\checkouts\embassy-0cff10c9b9902273\46473ae\embassy-stm32\src\sdmmc\mod.rs:1390:21
     |
1390 |             clk_pin.set_as_af_pull(clk_pin.af_num(), AFType::OutputPushPull, Pull::None);
     |                     ^^^^^^^^^^^^^^ method not found in `&mut CLK`
```

GPIOv1 actually supports pullups in AF mode, but only for inputs. The `sdmmc` driver, which was causing compile errors uses pullups for push-pull outputs and this will silently fail. But IMO not adding pullups to sdmmc interface is a hardware design problem, not HAL.

Co-authored-by: Dominic Clifton <me@dominicclifton.name>
Co-authored-by: chemicstry <chemicstry@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-06-06 15:45:03 +00:00
Dario Nieuwenhuis
fdc6cfed3e stm32: add stm32f103re to CI 2022-06-06 17:43:55 +02:00
chemicstry
b0ffd9a1cc Fix AF pullup configuration for GPIOv1 2022-06-06 17:12:52 +03:00
Dominic Clifton
1bad6a4989 Add example for using a Signal. 2022-06-06 11:54:01 +02:00
bors[bot]
34673f52c9
Merge #791
791: Channel clarification r=lulf a=diondokter

This was unclear from the docs.

Co-authored-by: Dion Dokter <diondokter@gmail.com>
2022-06-03 12:31:40 +00:00
Dion Dokter
9efaae495b
Channel clarification
This was unclear from the docs.
2022-06-03 14:27:33 +02:00
Ulf Lilleengen
9d5af531e3
Update copyright holder names and add notice file (#790)
* Update copyright holder names

Fixes #472

* Add notice file to clarify copyright ownership

The NOTICE file declares that copyright is owned by the individuals
contributing to Embassy, and that all contributed work is licensed under
Apache-2.0 or MIT.
2022-06-02 13:09:37 +02:00
bors[bot]
dbff4779eb
Merge #789
789: Embassy net improvements r=lulf a=lulf

I found these useful while implementing the TcpClient traits for embedded-nal-async:

https://github.com/drogue-iot/drogue-device/blob/shared-tcp-stack/device/src/drivers/tcp/smoltcp.rs

Once e-n-a PR is merged, I might add the above client to embassy-net if you think it makes sense.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-06-01 18:09:51 +00:00
Ulf Lilleengen
8b676e65ad Add embedded-io implementation of ConnectError 2022-06-01 13:48:28 +02:00
Ulf Lilleengen
39cffdd123 Add reexport for ipv6 types with proto-ipv6 2022-06-01 13:48:09 +02:00
bors[bot]
0adb4c926b
Merge #784
784: stm32: make tick rate configurable r=Dirbaio a=willglynn

The stm32 time drivers support arbitrary tick rates but the associated Cargo features do not. Enabling any time driver presently enables `embassy/time-tick-32768hz`; instead, enable only `embassy/time`.

Additionally, `embassy/time` now functions in the absence of any `embassy/time-tick-*` feature, defaulting to 32768 Hz if left unspecified.

Co-authored-by: Will Glynn <will@willglynn.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-05-31 21:55:40 +00:00
Dario Nieuwenhuis
1089674175 fix build adding missing time-tick feature. 2022-05-31 23:53:42 +02:00
Dario Nieuwenhuis
d13d893ff2 boot/stm32: autodetect thumbv6, remove cargo feature. 2022-05-31 23:52:27 +02:00
Will Glynn
962fabe5c9 examples/stm32*, tests/stm32: specify time-tick-32768hz 2022-05-31 16:14:23 -05:00
Will Glynn
34a8a64bf5 stm32: make tick rate configurable
The stm32 time drivers support arbitrary tick rates but the associated
Cargo features do not. Enabling any time driver presently enables
`embassy/time-tick-32768hz`; instead, enable only `embassy/time`.

This is a breaking change: users must now choose a tick rate. The
previous behavior is available by enabling the
`embassy/time-tick-32768hz` feature, but now users may also choose
`embassy/time-tick-1000hz` or `embassy/time-tick-1mhz` instead.
2022-05-30 20:13:25 -05:00
bors[bot]
a0d43c863d
Merge #788
788: Misc USB improvements, for stm32 r=Dirbaio a=Dirbaio

See individual commit messages. 

These changes help implementing the driver for STM32 USBD (#709)

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-05-31 00:46:22 +00:00
bors[bot]
70e4418df9
Merge #781 #785
781:  embassy-net v2 r=Dirbaio a=Dirbaio

- No more `dyn`
- It's no longer a global singleton, you can create muliple net stacks at once.
  - You can't tear them down though, the Device it still has to be `'static` due to restrictions with smoltcp's "fake GAT" in the Device trait. :(
- Removed `_embassy_rand` hack, random seed is passed on creation.



785: stm32: g0: add PLL clock source r=Dirbaio a=willglynn

STM32G0 SYSCLK can be sourced from PLLRCLK. Given that the HSI runs at 16 MHz and the HSE range is 4-48 MHz, the PLL is the only way to reach 64 MHz. This commit adds `ClockSrc::PLL`.

The PLL sources from either HSI16 or HSE, divides it by `m`, and locks its VCO to multiple `n`. It then divides the VCO by `r`, `p`, and `q` to produce up to three associated clock signals:

  * PLLRCLK is one of the inputs on the SYSCLK mux. This is the main reason the user will configure the PLL, so `r` is mandatory and the output is enabled unconditionally.
  * PLLPCLK is available as a clock source for the ADC and I2S peripherals, so `p` is optional and the output is conditional.
  * PLLQCLK exists only on STM32G0B0xx, and exists only to feed the MCO and MCO2 peripherals, so `q` is optional and the output is conditional.

When the user specifies `ClockSrc::PLL(PllConfig)`, `rcc::init()` calls `PllConfig::init()` which initializes the PLL per [RM0454]. It disables the PLL, waits for it to stop, enables the source oscillator, configures the PLL, waits for it to lock, and then enables the appropriate outputs. `rcc::init()` then switches the clock source to PLLRCLK.

`rcc::init()` is now also resonsible for calculating and setting flash wait states. SYSCLCK < 24 MHz is fine in the reset state, but 24-48 MHz requires waiting 1 cycle and 48-64 MHz requires waiting 2 cycles. (This was likely a blocker for anyone using HSE >= 24 MHz, with or without the PLL.) Flash accesses are now automatically slowed down as needed before changing the clock source, and sped up as permitted after changing the clock source. The number of flash wait states also determines if flash prefetching will be profitable, so that is now handled automatically too.

[RM0454]: https://www.st.com/resource/en/reference_manual/rm0454-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Co-authored-by: Will Glynn <will@willglynn.com>
2022-05-31 00:25:21 +00:00
Dario Nieuwenhuis
39ab599eed usb: set default max_packet_size_0 to 64.
Supported chips can always do 64 bytes, 8 bytes seems to be more rare.
We can add a way for the driver to specify the default in the future.
2022-05-31 02:01:22 +02:00
Dario Nieuwenhuis
a7383840e7 usb: make ControlPipe accept, reject async. 2022-05-30 00:35:27 +02:00
Dario Nieuwenhuis
883e28a0fb usb: add first, last params to ControlPipe data_in, data_out. 2022-05-30 00:08:28 +02:00
Dario Nieuwenhuis
1ec2e5672f usb: remove is_stalled, set_stalled from Endpoint.
They're unused, and I believe it's not allowed for classes to
stall EPs on their own?
2022-05-30 00:07:15 +02:00
Dario Nieuwenhuis
98d8c9373d usb: delay bus.set_address() to after ending the control transfer. 2022-05-30 00:03:36 +02:00
bors[bot]
842c7d08ab
Merge #787
787: Update embedded-hal-async to 0.1.0-alpha.1 r=Dirbaio a=Dirbaio

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-05-29 20:34:41 +00:00
Dario Nieuwenhuis
6320e30adf Update embedded-hal-async to 0.1.0-alpha.1 2022-05-29 22:34:08 +02:00
Will Glynn
1c2b27dcad embassy-stm32: g0: add PLL clock source
STM32G0 SYSCLK can be sourced from PLLRCLK. Given that the HSI runs at
16 MHz and the HSE range is 4-48 MHz, the PLL is the only way to reach
64 MHz. This commit adds `ClockSrc::PLL`.

The PLL sources from either HSI16 or HSE, divides it by `m`, and locks
its VCO to multiple `n`. It then divides the VCO by `r`, `p`, and `q`
to produce up to three associated clock signals:

  * PLLRCLK is one of the inputs on the SYSCLK mux. This is the main
    reason the user will configure the PLL, so `r` is mandatory and
	the output is enabled unconditionally.
  * PLLPCLK is available as a clock source for the ADC and I2S
    peripherals, so `p` is optional and the output is conditional.
  * PLLQCLK exists only on STM32G0B0xx, and exists only to feed the
    MCO and MCO2 peripherals, so `q` is optional and the output is
	conditional.

When the user specifies `ClockSrc::PLL(PllConfig)`, `rcc::init()`
calls `PllConfig::init()` which initializes the PLL per [RM0454]. It
disables the PLL, waits for it to stop, enables the source
oscillator, configures the PLL, waits for it to lock, and then
enables the appropriate outputs. `rcc::init()` then switches the
clock source to PLLRCLK.

`rcc::init()` is now also resonsible for calculating and setting flash
wait states. SYSCLCK < 24 MHz is fine in the reset state, but 24-48 MHz
requires waiting 1 cycle and 48-64 MHz requires waiting 2 cycles. (This
was likely a blocker for anyone using HSE >= 24 MHz, with or without
the PLL.) Flash accesses are now automatically slowed down as needed
before changing the clock source, and sped up as permitted after
changing the clock source. The number of flash wait states also
determines if flash prefetching will be profitable, so that is now
handled automatically too.

[RM0454]: https://www.st.com/resource/en/reference_manual/rm0454-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
2022-05-27 23:56:42 -05:00