Commit Graph

698 Commits

Author SHA1 Message Date
323b0d1a5c Have removed ANOTHER redondant ErrorType trait impl 2022-07-10 22:01:48 +02:00
1eca026ebd Have removed redondant ErrorType trait impl 2022-07-10 21:36:04 +02:00
e4a36e1d98 rustfmt on previously edited files 2022-07-10 21:08:12 +02:00
53388d4576 have adapted access to pin() and port() methods of Sealed::Pin in exti.rs according to previous changes on Input struct 2022-07-10 20:55:04 +02:00
fa3e1ab68a correction of the access to flex pin attribute in gpio_v2 2022-07-09 14:06:47 +02:00
39702d7624 set_as_input_output() and set_as_output() : Have added comments and made functions public 2022-07-08 21:46:16 +02:00
4e54d09ab1 Have added OutputOpenDrain with Flex 2022-07-04 22:38:05 +02:00
13b259d7cd Have added Flex to eh01 and eh2 2022-07-04 22:19:02 +02:00
359fc4d124 Flex GPIO implementation : Output 2022-06-30 23:03:15 +02:00
f05082b9a3 have reverted changed in mod eh1 from previous commit 2022-06-30 22:55:57 +02:00
9b3c5af92a Flex GPIO implementation : Input 2022-06-30 22:50:53 +02:00
3cdd8c1aeb Fix PWM for advanced timers 2022-06-23 02:27:39 +03:00
88e36a70bd Update to 2021 edition. (#820) 2022-06-18 02:15:48 +02:00
9031b8f80a Fix doc comments for BpskPacketParams 2022-06-16 07:34:59 +02:00
d0edd171f8 Fix typo in LoRaPacketParams::new doc 2022-06-16 06:22:03 +02:00
faa59efbf6 Cargo fmt 2022-06-15 09:01:22 +02:00
3696226fe8 Sync subghz peripheral support with stm32wlxx-hal 2022-06-14 16:27:42 +02:00
a8703b7598 Run rustfmt. 2022-06-12 22:22:31 +02:00
5085100df2 Add embassy-cortex-m crate.
- Move Interrupt and InterruptExecutor from `embassy` to `embassy-cortex-m`.
- Move Unborrow from `embassy` to `embassy-hal-common` (nothing in `embassy` requires it anymore)
- Move PeripheralMutex from `embassy-hal-common` to `embassy-cortex-m`.
2022-06-12 21:45:38 +02:00
db344c2bda common/PeripheralMutex: remove unsafe API. (#802)
Following the project's decision that "leak unsafe" APIs are not marked as "unsafe",
update PeripheralMutex to accept non-'static state without unsafe.

Fixes #801
2022-06-09 21:28:13 +02:00
7d64f5cda7 Use correct index and bank 2022-06-07 15:59:22 +02:00
3e4bead321 stm32: add USB driver. 2022-06-07 03:29:00 +02:00
0aa73f58e2 Update stm32-metapac. 2022-06-07 00:28:26 +02:00
b0ffd9a1cc Fix AF pullup configuration for GPIOv1 2022-06-06 17:12:52 +03:00
70e4418df9 Merge #781 #785
781:  embassy-net v2 r=Dirbaio a=Dirbaio

- No more `dyn`
- It's no longer a global singleton, you can create muliple net stacks at once.
  - You can't tear them down though, the Device it still has to be `'static` due to restrictions with smoltcp's "fake GAT" in the Device trait. :(
- Removed `_embassy_rand` hack, random seed is passed on creation.



785: stm32: g0: add PLL clock source r=Dirbaio a=willglynn

STM32G0 SYSCLK can be sourced from PLLRCLK. Given that the HSI runs at 16 MHz and the HSE range is 4-48 MHz, the PLL is the only way to reach 64 MHz. This commit adds `ClockSrc::PLL`.

The PLL sources from either HSI16 or HSE, divides it by `m`, and locks its VCO to multiple `n`. It then divides the VCO by `r`, `p`, and `q` to produce up to three associated clock signals:

  * PLLRCLK is one of the inputs on the SYSCLK mux. This is the main reason the user will configure the PLL, so `r` is mandatory and the output is enabled unconditionally.
  * PLLPCLK is available as a clock source for the ADC and I2S peripherals, so `p` is optional and the output is conditional.
  * PLLQCLK exists only on STM32G0B0xx, and exists only to feed the MCO and MCO2 peripherals, so `q` is optional and the output is conditional.

When the user specifies `ClockSrc::PLL(PllConfig)`, `rcc::init()` calls `PllConfig::init()` which initializes the PLL per [RM0454]. It disables the PLL, waits for it to stop, enables the source oscillator, configures the PLL, waits for it to lock, and then enables the appropriate outputs. `rcc::init()` then switches the clock source to PLLRCLK.

`rcc::init()` is now also resonsible for calculating and setting flash wait states. SYSCLCK < 24 MHz is fine in the reset state, but 24-48 MHz requires waiting 1 cycle and 48-64 MHz requires waiting 2 cycles. (This was likely a blocker for anyone using HSE >= 24 MHz, with or without the PLL.) Flash accesses are now automatically slowed down as needed before changing the clock source, and sped up as permitted after changing the clock source. The number of flash wait states also determines if flash prefetching will be profitable, so that is now handled automatically too.

[RM0454]: https://www.st.com/resource/en/reference_manual/rm0454-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Co-authored-by: Will Glynn <will@willglynn.com>
2022-05-31 00:25:21 +00:00
1c2b27dcad embassy-stm32: g0: add PLL clock source
STM32G0 SYSCLK can be sourced from PLLRCLK. Given that the HSI runs at
16 MHz and the HSE range is 4-48 MHz, the PLL is the only way to reach
64 MHz. This commit adds `ClockSrc::PLL`.

The PLL sources from either HSI16 or HSE, divides it by `m`, and locks
its VCO to multiple `n`. It then divides the VCO by `r`, `p`, and `q`
to produce up to three associated clock signals:

  * PLLRCLK is one of the inputs on the SYSCLK mux. This is the main
    reason the user will configure the PLL, so `r` is mandatory and
	the output is enabled unconditionally.
  * PLLPCLK is available as a clock source for the ADC and I2S
    peripherals, so `p` is optional and the output is conditional.
  * PLLQCLK exists only on STM32G0B0xx, and exists only to feed the
    MCO and MCO2 peripherals, so `q` is optional and the output is
	conditional.

When the user specifies `ClockSrc::PLL(PllConfig)`, `rcc::init()`
calls `PllConfig::init()` which initializes the PLL per [RM0454]. It
disables the PLL, waits for it to stop, enables the source
oscillator, configures the PLL, waits for it to lock, and then
enables the appropriate outputs. `rcc::init()` then switches the
clock source to PLLRCLK.

`rcc::init()` is now also resonsible for calculating and setting flash
wait states. SYSCLCK < 24 MHz is fine in the reset state, but 24-48 MHz
requires waiting 1 cycle and 48-64 MHz requires waiting 2 cycles. (This
was likely a blocker for anyone using HSE >= 24 MHz, with or without
the PLL.) Flash accesses are now automatically slowed down as needed
before changing the clock source, and sped up as permitted after
changing the clock source. The number of flash wait states also
determines if flash prefetching will be profitable, so that is now
handled automatically too.

[RM0454]: https://www.st.com/resource/en/reference_manual/rm0454-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
2022-05-27 23:56:42 -05:00
1d951a54be Reimplement BufRead for BufferedUart 2022-05-26 14:02:55 +03:00
a5aea995a8 WIP embassy-net v2 2022-05-25 19:56:22 +02:00
7743b8e1ae Merge #776
776: Automatically set ADC clock prescaler on v2 ADC to respect max frequency r=Dirbaio a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-05-19 04:00:23 +00:00
53f65d8b09 Automatically set ADC clock prescaler on v2 ADC to respect max frequency 2022-05-18 18:34:36 +02:00
c90968bb70 stm32/rcc: Modify only relevant CFGR bits and keep the settings previously done.
PLL settings remained intact because these bits are not writable when PLL is enabled,
but prescaler settings were overwritten by selecting PLL as sysclk (CFGR.SW[1:0]).
2022-05-12 09:09:39 +02:00
1a216958ac stm32/rcc: Set flash prefetch buffer and half cycle access according to AHB clock prescaler 2022-05-12 09:09:39 +02:00
f4677469f9 stm32/usart: Data length is including parity. To get e.g. 8E1 you need to choose 9 data bits 2022-05-12 09:09:30 +02:00
01fb447e9d Allow maximal clock for F7 HCLK 2022-05-08 23:07:28 +02:00
e9ab960ebf Merge #760
760: stm32/gpio: Add support for `set_speed` for gpio v1 r=Dirbaio a=GrantM11235



Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2022-05-08 19:53:31 +00:00
acc1761637 Remove unnecessary cfg 2022-05-08 14:50:15 -05:00
b230ac9c1a stm32/gpio: Add support for set_speed for gpio v1 2022-05-08 14:43:37 -05:00
96d0eb9476 stm32: Fix stm32f107 build. 2022-05-08 21:37:37 +02:00
a4bf190f2f Merge #752
752: Replace embassy::io with embedded_io. r=Dirbaio a=Dirbaio

TODO:

- [x] Release embedded-io on crates.io
- [x] Remove git dep

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-05-06 23:54:07 +00:00
931a137f8c Replace embassy::io with embedded_io. 2022-05-07 01:45:54 +02:00
118532278c Add H7 flash and bootloader support 2022-05-06 21:57:15 +02:00
6d56f772e1 Add F7 flash and bootloader support 2022-05-06 21:57:15 +02:00
f3700b4e42 Refactor flash handling to different modules for different families 2022-05-06 21:57:15 +02:00
4f5088d79d Add support for F3 flash 2022-05-06 21:57:15 +02:00
fc32b3750c Remove embassy_hal_common::usb.
The replacement is `embassy-usb`. There's a WIP driver for stm32 USBD in #709,
there's no WIP driver for stm32 USB_OTG. This means we're left without
USB_OTG support for now.

Reason for removing is I'm going to soon remove `embassy::io`, and
USB uses it. I don't want to spend time maintaining "dead" code
that is going to be removed. Volunteers welcome, either to update
old USB to the new IO, or write a USB_OTG driver fo the new USB.
2022-05-04 01:41:37 +02:00
49ae26f384 Merge pull request #748 from embassy-rs/nrf-i2c-timeout
Misc HAL improvements.
2022-05-03 01:25:05 +02:00
71e46d7efd stm32/gpio: add EH1.0 trait impls. 2022-05-03 00:52:48 +02:00
6e129cf34f Merge #747
747: stm32/adc/v4: Fix log statement r=Dirbaio a=GrantM11235



Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2022-05-02 20:18:01 +00:00
4bccd77849 stm32/adc/v4: Fix log statement 2022-05-02 15:14:49 -05:00
a5f5c3a844 net: add functions to get current Eth and IP config 2022-05-02 16:19:34 +02:00