Commit Graph

5701 Commits

Author SHA1 Message Date
fa36fa2808 stm32/tests: add spi 2021-12-07 05:01:01 +01:00
a14c4f49c4 stm32/tests: higher clocks for H7 2021-12-07 05:00:35 +01:00
5dc5192d79 Merge #520
520: stm32/tests: add stm32h755zi, stm32wb55rg r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-12-07 00:47:59 +00:00
17c5dc496e stm32/tests: add stm32h755zi, stm32wb55rg 2021-12-07 01:24:26 +01:00
c1b4759935 Merge #519
519: stm32: Add timer test, add g0, g4 tests. r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-12-06 23:39:34 +00:00
dde6607aec Add timer test, add g0, g4 tests. 2021-12-07 00:29:41 +01:00
693690cb5a Uncomment accidentally commented ci stuff. 2021-12-07 00:27:37 +01:00
d76bc45e30 Move Spi drop impl to mod 2021-12-06 17:19:55 -06:00
bd9e730024 Move set_word_size to mod 2021-12-06 16:47:08 -06:00
a35b7d90bc Add tx_ptr and rx_ptr methods 2021-12-06 16:33:06 -06:00
7058f29cf0 Merge #451
451: stm32f4 GPIO HIL test r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-12-06 21:42:47 +00:00
a35f337bd6 Move Spi::new and Spi::compute_baud_rate to mod 2021-12-06 15:19:24 -06:00
dd32358d6b stm32: add gpio HIL test 2021-12-06 22:05:41 +01:00
00a87b9a41 Fix build examples with defmt. 2021-12-06 21:58:57 +01:00
75374ce7e8 Fix ssoe in v1 2021-12-06 14:57:53 -06:00
e1cccc8391 Move Spi to mod (without NoDma defaults) 2021-12-06 14:47:50 -06:00
aeb69a7665 Track current word size in v2 and v3 also 2021-12-06 14:24:02 -06:00
d51885c0eb Move WordSize methods to mod 2021-12-06 14:13:25 -06:00
d426caefbf Move NoPin impls from v1 to mod 2021-12-06 14:02:21 -06:00
8b4a247af2 Merge #517
517: Fix embassy-net documentation of running examples. r=lulf a=matoushybl

and fix weird indentation.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2021-12-06 14:39:53 +00:00
a802fd83aa Fix embassy-net documentation of running examples. 2021-12-06 14:59:15 +01:00
7c155c3aba Merge #514
514: Refactor sx127x driver to use async SPI r=lulf a=lulf

It also contains a fix to SPI DMA transfer/read_write operations to ensure MISO doesn't contain any old data.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2021-12-06 08:35:11 +00:00
81ec4c82fd Flush MISO before transfer operation 2021-12-03 09:53:28 +01:00
9a730ef692 Refactor sx127x radio to use async SPI with DMA 2021-12-03 09:53:28 +01:00
b9693c0b91 Update rust-lorawan to version supporting defmt 0.3 2021-12-02 19:10:29 +01:00
6d6e6f55b8 Merge #513
513: Update stm32data ref r=lulf a=lulf

Not including the changes to stm32-data main which seems to break the build.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2021-12-02 17:55:07 +00:00
5d057eb12c Update stm32data ref 2021-12-02 18:46:53 +01:00
df9a41c3eb Merge #515
515: Downcast timer to GP16 for time drivers. r=lulf a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2021-12-02 17:13:55 +00:00
6e0eb33ea8 Downcast timer to GP16 for time drivers. 2021-12-02 18:07:05 +01:00
51c26a7d05 Merge #512
512: nrf9160: fix gpiote r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-12-02 03:03:52 +00:00
edbe242ccc ci: add gpiote+time-driver to embassy-nrf to catch more failures. 2021-12-02 04:01:39 +01:00
6dd55265cd nrf/gpiote: fix build for nrf9160 2021-12-02 04:01:03 +01:00
2d620df9d6 Merge #511
511: Fix wrong pin configuration in STM32's SPI v3. r=matoushybl a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2021-12-01 21:29:04 +00:00
f0cb77443c Fix wrong pin configuration in STM32's SPI v3. 2021-12-01 22:18:14 +01:00
9500c8c17b Merge #509
509: Remove unsafe from nRF uarte and improve doco with rationale r=Dirbaio a=huntc

The constructors themselves are not strictly unsafe. Interactions with DMA can be generally unsafe if a future is dropped, but that's a separate issue. It is important that we use the `unsafe` keyword diligently as it can lead to confusion otherwise.

I've also provided some rationale re. the usage of [Uarte] vs [BufferedUarte].

Co-authored-by: huntc <huntchr@gmail.com>
2021-11-30 22:39:18 +00:00
496ad4ed43 Rationale for uarte usage 2021-12-01 09:37:09 +11:00
469852c667 Removed unsafe from uarte
The constructors themselves are not strictly unsafe. Interactions with DMA can be generally unsafe if a future is dropped, but that's a separate issue. It is important that we use the `unsafe` keyword diligently as it can lead to confusion otherwise.
2021-12-01 09:14:24 +11:00
e36e36dab6 Merge #507
507: Stm32 data upate 4 r=Dirbaio a=Dirbaio

Main imrpvement is RCC regs info comes from yamls now.

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-29 01:28:24 +00:00
b0fabfab5d Update stm32-data: rcc regs info comes from yamls now. 2021-11-29 02:28:02 +01:00
3332c40705 examples: remove unused deps. 2021-11-29 02:07:48 +01:00
2a2911221d Merge #506
506: Clock cleaning r=Dirbaio a=lulf

Different STM32 RCC peripherals have different capabilities and register values. Define types for each RCC types inside each module to ensure full range of capabilities for each family can be used

Co-authored-by: Ulf Lilleengen <ulf.lilleengen@gmail.com>
2021-11-28 19:41:16 +00:00
25b49a8a2a Remove common clock types
Different STM32 RCC peripherals have different capabilities and register
values. Define types for each RCC types inside each module to ensure
full range of capabilities for each family can be used
2021-11-28 16:46:08 +01:00
1b24b3bd68 Make ci script run on Mac OS X 2021-11-28 14:07:21 +01:00
543cc65e56 Merge #449
449: STM32: Add PWM support r=Dirbaio a=bgamari

Here is a first-cut at implementing PWM support for STM32 targets via the TIM peripherals. Currently this only contains pin configuration for the STM32G0 but it would be straightforward to extend to other platforms.

Co-authored-by: Ben Gamari <ben@smart-cactus.org>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-27 02:07:43 +00:00
006e567716 stm32/pwm: allow using the advanced timer instances too. 2021-11-27 03:06:53 +01:00
e40555e245 examples/stm32g4: add pwm example 2021-11-27 03:06:46 +01:00
d7d1258411 stm32/pwm: small cleanups 2021-11-27 03:05:10 +01:00
22fad1e7bc stm32/pwm: impl instance/pin for all chips 2021-11-27 03:04:50 +01:00
8211d58ee2 stm32/pwm: initial commit 2021-11-27 02:50:30 +01:00
793f4b1f7d Merge #505
505: stm32: add stm32g4 support. r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-27 01:44:23 +00:00