Commit Graph

29 Commits

Author SHA1 Message Date
Mathias
88483b5abe Fix return type for EH-nb traits 2023-03-23 14:26:37 +01:00
Mathias
04f90e3a9d Add embedded-io blocking Read + Write for BufferedUart 2023-03-23 14:18:19 +01:00
Mathias
89a371d10c Add HIL test for into_buffered uart on embassy-rp 2023-03-14 12:46:58 +01:00
Mathias
bce1ce7dcb Allow upgrading a blocking uart to a BufferedUart, and implement blocking serial traits for BufferedUart 2023-03-14 10:36:30 +01:00
Andres Hurtado Lopez
2331d58aa6 RP-PICO UART adding set_baudrate: missing to run rust-fmt 2023-02-26 21:23:51 -05:00
Andres Hurtado Lopez
482ba835c4 RP-PICO UART adding set_baudrate: Changing static call from specific type to a Self (requires adding lifetime specifier) 2023-02-26 19:20:08 -05:00
Andres Hurtado Lopez
7172dfd083 RP-PICO UART adding set_baudrate: refactoring of methods 2023-02-26 19:14:25 -05:00
Andres Hurtado Lopez
8fb380b180 RP-PICO UART adding set_baudrate 2023-02-26 18:40:23 -05:00
bors[bot]
b6c8505697
Merge #1142
1142: More rp2040 BufferedUart fixes r=Dirbaio a=timokroeger

* Refactor init code
* Make it possible to drop RX without breaking TX (or vice versa)
* Correctly handle RX buffer full scenario

Co-authored-by: Timo Kröger <timokroeger93@gmail.com>
2023-01-14 00:07:02 +00:00
Timo Kröger
539f97da53 rp: Fix formatting string to please CI 2023-01-05 22:00:44 +01:00
Timo Kröger
1096a9746c rp: Improve BufferedUart interrupt handling
* Only clear interrupt flags that have fired (so that we do not lose any error flags)
* Enable RX interrupt when a read is requested, disable it when the RX buffer is full
* Rework TX interrupt handling: its "edge" triggered by a FIFO threshold
2023-01-05 18:45:58 +01:00
Pedro Ferreira
6d4c6e0481 rp2040: add {tx,rx}-only constructors to UART 2023-01-04 21:11:19 +01:00
Timo Kröger
840a75674b rp: Disable RX interrupts when ring buffer is full
When data is in the RX fifo the RX timeout interrupt goes high again even after clearing it.
The result is a deadlock because execution is stuck in the interrupt handler. No other code
can run to clear the receive buffer.
Enable and disable RX interrupts based on the buffer fill level.
Use the same approach for the TX code path.
2023-01-04 16:53:43 +01:00
Timo Kröger
a24037edf9 rp: Fix BufferedUart drop code
Only unregister the interrupt handler when both parts are inactive
2023-01-04 15:59:03 +01:00
Timo Kröger
68c186309f rp: Common init function for BufferedUart
BufferedUart, BufferedUartRx and BufferedUartTX can all use the same init code.
2023-01-04 15:58:26 +01:00
Timo Kröger
e4f457646f rp: Fill and empty FIFOs in buffered uart interrupt
Fixes an issue where only the first byte was transmitted.
Should improve throughput aswell.
2022-12-27 11:28:52 +01:00
kalkyl
aa92ce6dc7 embassy-rp: Add split() to BufferedUart 2022-12-22 23:03:05 +01:00
Dario Nieuwenhuis
7b838d0336 rp/uart: use lockfree ringbuffer.
This gets rid of another PeripheralMutex usage.
2022-11-25 22:30:47 +01:00
Dario Nieuwenhuis
1e2fb0459d Switch to async-fn-in-trait 2022-11-25 21:02:06 +01:00
Dario Nieuwenhuis
eeb072d9cb Update Rust nightly. 2022-10-26 16:47:29 +02:00
Ulf Lilleengen
72c2e985bb Update embedded-hal versions and explicitly pin 2022-09-29 11:27:46 +02:00
Mathias
820e6462b6 Add preliminary I2C implementation for RP2040 2022-09-27 22:08:49 +02:00
Mathias
e129a97d48 Fix bufferedUart read and write tests 2022-09-27 07:45:10 +02:00
Mathias
65907204d6 Rename from {Rx,Tx}BufferedUart to BufferedUart{Rx,Tx} to be compliant with stm32 and nrf implementations 2022-09-27 05:51:31 +02:00
Mathias
b743d9f48c Add HIL test for bufferedUart 2022-09-26 05:32:45 +02:00
Mathias
1d3e41f970 Remove code-duplication in async bufferedUart implementations 2022-09-21 06:00:35 +02:00
Mathias
b2d0f8d590 Formatting 2022-09-09 10:49:47 +02:00
Mathias
31d85da78a Add bufferedUart, including a split version for only Rx or Tx 2022-09-09 10:48:52 +02:00
Mathias
9611e7c9f2 Add BufferedUart implementation, and feature-guard time-driver initialization, to free up TIMER peripheral if not used with embassy executor 2022-09-09 10:48:30 +02:00