xoviat
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b24520579a
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rcc: ahb/apb -> hclk/pclk
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2023-10-15 19:51:35 -05:00 |
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Dario Nieuwenhuis
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4a43cd3982
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stm32/rcc: LSE xtal is 32768hz, not 32000hz.
Fixes #2043
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2023-10-11 13:39:04 +02:00 |
|
Dario Nieuwenhuis
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b91d1eaca0
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stm32/rcc: add LSE/LSI to all chips, add RTC to more chips.
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2023-10-11 04:12:38 +02:00 |
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Dario Nieuwenhuis
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21915a9a3f
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stm32/rcc: unify L0 and L1.
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2023-10-11 01:22:27 +02:00 |
|
Matt Ickstadt
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f01609036f
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h7: implement RTC and LSE clock configuration
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2023-10-06 13:28:30 -05:00 |
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xoviat
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bb8a1b7f1f
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wpan: re-enable HIL tests
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2023-10-03 15:53:22 -05:00 |
|
Dario Nieuwenhuis
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b856d760f4
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stm32/rcc: reset backup domain before enabling LSE.
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2023-10-02 22:12:50 +02:00 |
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xoviat
|
04b09a2acb
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stm32/rtc: use rccperi enable
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2023-09-25 16:26:29 -05:00 |
|
xoviat
|
9f2fc04caa
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stm32: fix bd lsi
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2023-09-24 18:37:09 -05:00 |
|
Christian Enderle
|
ad64d7b20b
|
fix low-power: APB1 needed for LSE
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2023-09-21 17:17:58 +02:00 |
|
xoviat
|
a6ef314be1
|
stm32: update configure_ls as agreed
|
2023-09-17 18:41:45 -05:00 |
|
Dario Nieuwenhuis
|
8315cf064e
|
stm32: add stm32wba support.
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2023-09-16 04:04:45 +02:00 |
|
xoviat
|
9fb14379c3
|
stm32: add lp to l0
|
2023-09-14 18:53:27 -05:00 |
|
xoviat
|
11a78fb1e4
|
rcc: more cleanup
|
2023-09-08 18:20:58 -05:00 |
|
xoviat
|
c21ad04c2e
|
stm32: extract lse/lsi into bd mod
|
2023-09-06 17:48:12 -05:00 |
|
xoviat
|
d097c99719
|
stm32/rcc: add lsi and lse bd abstraction
|
2023-09-06 17:33:56 -05:00 |
|
xoviat
|
70a5221b2e
|
stm32/bd: consolidate enable_rtc
|
2023-08-28 15:34:08 -05:00 |
|
xoviat
|
cbc92dce05
|
stm32/bd: fix errors
|
2023-08-27 15:18:34 -05:00 |
|
xoviat
|
531f51d0eb
|
rcc/bd: consolidate mod
|
2023-08-27 15:01:09 -05:00 |
|
xoviat
|
10ea068027
|
stm32/bd: allow dead code
|
2023-08-27 09:12:04 -05:00 |
|
xoviat
|
4caa8497fc
|
stm32: extract backupdomain into mod
|
2023-08-27 09:07:34 -05:00 |
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