Commit Graph

6126 Commits

Author SHA1 Message Date
Dario Nieuwenhuis
288309b9d5 net-driver: document crate. 2023-05-15 00:56:59 +02:00
Dario Nieuwenhuis
d07821d851 net: document crate. 2023-05-15 00:56:09 +02:00
Dario Nieuwenhuis
62857bdb2d net: reexport UDP PacketMetadata under the udp module. 2023-05-15 00:55:34 +02:00
Dario Nieuwenhuis
26d7610554 net: do not use smoltcp Instant/Duration in public API. 2023-05-15 00:53:30 +02:00
bors[bot]
6e93d193cf
Merge #1451
1451: Work around xtensa deadlock, take 2 r=Dirbaio a=bugadani

This PR is another go at trying to do something with #1449. The commit was part of the previous attempt but mistakenly discarded as I still experienced lockups. However, after further testing, it looks like that lockup is caused by something else.

This is a manual, "cpu-local" critical section impl that should be good enough on dual-core CPUs, although the implementation still contains `SIGNAL_WORK_THREAD_MODE` which is absolutely not correct on dual-core. This approach was chosen because:
 - not taking the global lock technically allows the second core to run
 - wrapping the signal read and the sleep in a critical section prevents a race condition that would cause the CPU to sleep longer than ideal if an interrupt hits after reading, but before sleeping.

Co-authored-by: Dániel Buga <bugadani@gmail.com>
2023-05-14 22:20:15 +00:00
bors[bot]
4567eff78e
Merge #1455
1455: Remove unused `feature(type_alias_impl_trait)`. r=Dirbaio a=Dirbaio

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-05-14 21:57:51 +00:00
Dario Nieuwenhuis
2d65373f63 Remove unused feature(type_alias_impl_trait). 2023-05-14 23:44:53 +02:00
bors[bot]
ae4827587c
Merge #1454
1454: stm32f0 flash implementation r=Dirbaio a=jp99

i've copied and modified the f3 implementation and it seems to be working.


Co-authored-by: Jaap Prickartz <jaap@tetra.nl>
2023-05-14 21:39:55 +00:00
Dario Nieuwenhuis
a3d6aa5d7d
Merge pull request #79 from embassy-rs/update-embassy
Update Embassy, to new PIO API.
2023-05-14 21:08:37 +00:00
Dario Nieuwenhuis
db907a914c cyw43-pio: add overclock feature flag. 2023-05-14 23:02:49 +02:00
bors[bot]
cdd326284a
Merge #1453
1453: stm32 uart: Fix error flag handling for blocking operations r=Dirbaio a=timokroeger

Clear and report the error flags one by one and pop the data byte only after all error flags were handled.

For v1/v2 we emulate the v3/v4 behaviour by buffering the status register because a read to the data register clears all flags at once which means we might loose all but the first error.

Only tested on stm32f3 discovery board with loopback. Let‘s see what CI says for the other families.
Fixes #1452 

Co-authored-by: Timo Kröger <timokroeger93@gmail.com>
2023-05-14 20:20:45 +00:00
Timo Kröger
3e9d5978c0 stm32 uart: Add a test for blocking RX overflow 2023-05-14 22:03:06 +02:00
Jaap Prickartz
ec7a4fd9cc stm32f0 flash implementation 2023-05-14 21:57:31 +02:00
Timo Kröger
977a7906e4 stm32 uart: Fix error flag handling for blocking operations
Clear and report the error flags one by one and pop the data byte only
after all error flags were handled.

For v1/v2 we emulate the v3/v4 behaviour by buffering the status
register because a read to the data register clears all flags at once
which means we might loose all but the first error.
2023-05-14 21:10:37 +02:00
Dario Nieuwenhuis
7cfce05bd2
Merge pull request #81 from mkj/powersave-none
Fix PowerManagementMode::None
2023-05-14 15:26:48 +00:00
Matt Johnston
f46e0eb5f2 Fix PowerManagementMode::None
Mode was being set to 2 (PM2_POWERSAVE_MODE), should be
0 (NO_POWERSAVE_MODE). Setting None mode failed with a panic:

85.707099 DEBUG set pm2_sleep_ret = [00, 00, 00, 00]
└─ cyw43::control::{impl#0}::set_iovar_v::{async_fn#0} @ cyw43/src/fmt.rs:127
85.710469 ERROR panicked at 'IOCTL error -29'
2023-05-14 22:48:04 +08:00
Dániel Buga
5fe36b6bb0 Work around xtensa deadlock, take 2 2023-05-13 15:04:02 +02:00
kalkyl
6c1137177f Wait until there's enough space in tx buffer, remove busy wait for completed send 2023-05-13 06:34:03 +02:00
Dario Nieuwenhuis
8800caa216 Update Embassy, to new PIO API. 2023-05-13 02:58:42 +02:00
bors[bot]
82f7e104d9
Merge #1448
1448: rp: don't use SetConfig trait in PWM and PIO. r=Dirbaio a=Dirbaio

It was intended to allow changing baudrate on shared spi/i2c. There's no advantage in using it for PWM or PIO, and makes it less usable because you have to have `embassy-embedded-hal` as a dep to use it.

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-05-13 00:14:50 +00:00
Dario Nieuwenhuis
2fcdfc4876 rp: don't use SetConfig trait in PWM and PIO.
It was intended to allow changing baudrate on shared spi/i2c. There's no
advantage in using it for PWM or PIO, and makes it less usable because you have to
have `embassy-embedded-hal` as a dep to use it.
2023-05-13 02:13:26 +02:00
bors[bot]
dec75474d5
Merge #1447
1447: rp/watchdog: fix overflow if period is longer than 4294 seconds. r=Dirbaio a=Dirbaio

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-05-12 22:33:59 +00:00
Dario Nieuwenhuis
3edd81a94e rp/watchdog: fix overflow if period is longer than 4294 seconds. 2023-05-13 00:33:00 +02:00
goueslati
3810fe6a20 tl_mbox: added zigee, lld tests and ble lld tables to ref table 2023-05-12 10:26:46 +01:00
bors[bot]
7f96359804
Merge #1424
1424: add TL maibox for stm32wb r=xoviat a=OueslatiGhaith

Hello,

This pull request is related to #1397 and #1401, inspired by #24, build upon the work done in #1405, and was tested on an stm32wb55rg.

This pull request aims to add the transport layer mailbox for stm32wb microcontrollers. For now it's only capable of initializing it and getting the firmware information

Co-authored-by: goueslati <ghaith.oueslati@habemus.com>
Co-authored-by: Ghaith Oueslati <73850124+OueslatiGhaith@users.noreply.github.com>
Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-05-11 22:48:55 +00:00
xoviat
bf45b1d83d fix memory.x 2023-05-11 17:23:18 -05:00
xoviat
d7262f9849 rustfmt 2023-05-11 16:53:55 -05:00
xoviat
8a620fd59c stm32/ble: fix tests and add instructions to run example 2023-05-11 16:45:42 -05:00
kalkyl
bbd687fcb0 Update embassy 2023-05-10 02:40:41 +02:00
kalkyl
7b83d53bbf vscode settings 2023-05-10 02:25:18 +02:00
kalkyl
adefa4f86b vscode settings 2023-05-10 02:23:54 +02:00
bors[bot]
e179e7cf85
Merge #1436
1436: rp: Clock configuration r=CBJamo a=CBJamo

Draft of a more complete clock config for the 2040.

I also extended and made public the clk_<name>_freq functions. I know at least the ws2812 pio example would like to get the sys clock at runtime rather than just using a constant. I suspect most pio-based peripherals will want access to the clocks.

Open questions:

1. Best way to handle the 3 external clock frequencies. I think the XIN (aka crystal) freq should just be set by the init function then never changed, though if it's an external clock that could change? I'm not sure anyone would ever want to do that but maybe it should be handled just in case? The other two should probably be set by the application.
2. Better estimation of ROSC frequency. Right now it's really just a lookup table of the speed from the single sample I did this testing on, and only uses the frequency range and div, drive strength is ignored.
3. Probably some kind of warning should be generated if the random bit from the rosc won't be useful, not sure how to do that.
4. Should clocks only be allowed to be configured at init, or should they be modifiable at runtime? For example, switching the RTC to a clock in pin when a pps source is available.

Bonus feature to support clock output. I only implemented the bare minimum, and only for gpout0. I'm sure there's a clean way with macros to impl all 4 without just copy/paste, but I haven't learned macros yet.

Co-authored-by: Caleb Jamison <caleb@cbjamo.com>
2023-05-09 21:56:43 +00:00
Caleb Jamison
9d971e5b15
Merge branch 'master' into master 2023-05-09 17:55:27 -04:00
Caleb Jamison
5cfe1a1fb4 Dirbaio comments round 2 2023-05-09 17:45:24 -04:00
bors[bot]
856b944eaf
Merge #1439
1439: rp: use rp2040-boot2 to provide the boot2 blob r=Dirbaio a=pennae

we're currently shipping an old boot2 that runs the flash at half speed. use the more recent version instead, and allow user to choose between the different supported boot2 versions for different flash chips if they need that.

Co-authored-by: pennae <github@quasiparticle.net>
2023-05-09 16:39:13 +00:00
pennae
0e3cd87a32 rp: use rp2040-boot2 to provide the boot2 blob
we're currently shipping an old boot2 that runs the flash at half speed.
use the more recent version instead, and allow user to choose between
the different supported boot2 versions for different flash chips if they
need that.
2023-05-09 18:36:17 +02:00
Caleb Jamison
6bea078487 Remove patches, bump rp-pac version 2023-05-09 12:20:23 -04:00
Caleb Jamison
5015c845c5 Improve gpout example, clk_gpout_freq 2023-05-09 12:10:24 -04:00
Caleb Jamison
c1eaad41f3 Gpout cleanup, basic Gpin support
Requires rp-pac #3
2023-05-09 11:46:25 -04:00
kalkyl
d40589f082 Fix CI 2023-05-09 02:27:28 +02:00
kalkyl
9d018a0075 Add CI 2023-05-09 02:24:25 +02:00
kalkyl
fdc87a8e7f Add CI 2023-05-09 02:21:17 +02:00
kalkyl
72b0379125 🌈 2023-05-09 01:51:08 +02:00
Caleb Jamison
14eecf2fc4 Address Dirbaio comments
Gpout still incomplete.
2023-05-08 19:13:50 -04:00
bors[bot]
0b4b87e344
Merge #1437 #1438
1437: Fix some typos r=Dirbaio a=striezel

This pull request fixes some typos, no functional changes intended.

1438: Update GitHub Actions CI r=Dirbaio a=striezel

The following updates are performed:
* update [`actions/cache`](https://github.com/actions/cache) to v3
* update [`actions/checkout`](https://github.com/actions/checkout) to v3

Still using the outdated actions will generate several warnings in CI runs, for example in https://github.com/embassy-rs/embassy/actions/runs/4917900672:

> Node.js 12 actions are deprecated. Please update the following actions to use Node.js 16: actions/checkout@v2, actions/cache@v2. For more information see: https://github.blog/changelog/2022-09-22-github-actions-all-actions-will-begin-running-on-node16-instead-of-node12/.

The PR will get rid of those warnings.

Co-authored-by: Dirk Stolle <striezel-dev@web.de>
2023-05-08 21:38:30 +00:00
Dirk Stolle
5df263db38 Update GitHub Actions CI
The following updates are performed:
* update actions/cache to v3
* update actions/checkout to v3
2023-05-08 23:28:01 +02:00
Dirk Stolle
0584312ef0 Fix some typos 2023-05-08 23:25:01 +02:00
Dario Nieuwenhuis
6b5d9642d5 Rename BCD -> BDC. That's what Broadcom calls it. Still no idea what it means. 2023-05-08 22:01:44 +02:00
Dario Nieuwenhuis
881e9d07d2 Fix missing padding in tx. Makes max-sized packets not get dropped 2023-05-08 21:53:03 +02:00
Dario Nieuwenhuis
a7dee5b65c Change all logging level to debug. 2023-05-08 21:53:03 +02:00