c5022b1196
stm32: Make sure Output gpio driver is pushpull
2021-06-27 13:25:35 -03:00
0eaadfc125
stm32: Update gpio examples
2021-06-25 18:16:43 -03:00
a3f0aa02a4
Separate OpenDrain pin to a new type
2021-06-25 17:22:51 -03:00
efb3b3a0a8
stm32: Allow for open drain configuration for output pin
2021-06-24 20:42:43 -03:00
013792b944
Separate exti into v1 and v2
2021-06-24 20:28:06 -03:00
1c33a3b94c
#[cfg] exti
2021-06-24 19:41:04 -03:00
210104e6dc
Remove unused gpio_af from codegen
2021-06-24 19:23:51 -03:00
409884be2a
Add F0 RCC
2021-06-24 19:21:56 -03:00
797534d1a6
Update features to include F0
2021-06-22 14:41:42 -03:00
5a4e3ceb88
Update stm32-data (adds DBGMCU to all chips)
2021-06-21 01:38:59 +02:00
098ce6e740
stm32h7: Add ethernet example
2021-06-16 16:48:35 +02:00
77546825a1
stm32: Make vcell dependency optional
2021-06-16 16:48:35 +02:00
598201bff3
eth-v2: Make embassy-net optional
2021-06-16 16:48:35 +02:00
6cecc6d4b5
eth-v2: Get hclk frequency from clock singleton
2021-06-16 16:48:35 +02:00
f7e1f262af
eth-v2: Enable source address filtering
2021-06-16 16:48:35 +02:00
ffc19a54d6
eth-v2: Fix bug in Rx descriptors and add docs art
2021-06-16 16:48:35 +02:00
6daa55a897
eth-v2: Fix setting the registers for the descriptors
...
Also, the interrupts are set to 1 to clear, the manual could have helped
with that one...
2021-06-16 16:48:35 +02:00
0b42e12604
eth-v2: Fix off by one bug
2021-06-16 16:48:35 +02:00
54ad2a41f1
eth-v2: Work around missing AF for REF_CLK
2021-06-16 16:48:35 +02:00
0c837f07c0
eth-v2: Enable clocks in new
2021-06-16 16:48:35 +02:00
e039c7c42c
eth-v2: Remove Instance trait
2021-06-16 16:48:35 +02:00
05a239faf6
eth-v2: Implement embassy-net's Device Trait and fix Drop
2021-06-16 16:48:35 +02:00
4cffa200bd
eth: Add lan8742a PHY
2021-06-16 16:48:35 +02:00
46e1bae9e3
eth-v2: Start Ethernet peripheral implementation
2021-06-16 16:48:35 +02:00
56c5218292
Prescaler 1 means divide by 3 on WL55
2021-06-16 16:21:16 +02:00
383beb37b3
Rename from wl55 to wl5x and enable debug wfe
2021-06-16 16:07:21 +02:00
b6a8703698
Add support for generating PAC for dual cores
...
* Chips that have multiple cores will be exposed as chipname_corename,
i.e. stm32wl55jc_cm4
* Chips that have single cores will use the chip family as feature name
and pick the first and only core from the list
* Add support for stm32wl55 chip family
2021-06-16 15:12:07 +02:00
8ae4f47d3d
Fix compile
2021-06-15 16:44:00 +02:00
49fad2de8a
Use correct frequencies for timers
2021-06-15 16:07:23 +02:00
4b406dd107
Remove default rcc impl
2021-06-14 20:24:51 +02:00
d58fb11b2e
ADCv3 and example.
2021-06-14 13:20:42 -04:00
531093f281
Derive SPI v1 and v3 clocks automatically
2021-06-14 11:58:16 +02:00
5e1b0a5398
Add wb55 clocks
2021-06-14 11:41:02 +02:00
ee9f67fa01
Add common types
2021-06-14 11:33:11 +02:00
a2da2a6db2
Remove unused l0 code
2021-06-14 11:33:11 +02:00
95532726b2
Add minimal RCC impls for L4 and F4
2021-06-14 11:33:11 +02:00
a13e07625f
Add ... c1?
2021-06-14 11:33:11 +02:00
0b52731897
Add clocks for h7
2021-06-14 11:33:11 +02:00
2c63393c9e
Add Clock type per RCC family
2021-06-14 11:33:11 +02:00
952f525af5
Provide a way for a peripheral to query its clock frequency
...
Currently this looks up the frequency in the global singleton that must
be initialized by the per-chip RCC implementation. At present, this is
only done for the L0 family of chips.
2021-06-14 11:33:11 +02:00
9edb6e41ce
Make gen.py work without CSafeLoader
2021-06-12 18:28:21 +02:00
0eab96f573
Initial support and example for STM32WB55
2021-06-12 07:06:36 +02:00
0a9022d59f
Enable timer clock in RCC on timer start
...
* Moves the tim2-specific code into macro which always uses TIM2
* For peripherals without clock specified, attempt to locate enable and
reset registers in the RCC block matching the peripheral name. This
could be useful for peripherals where deducing the clock name might
not be feasible, but it remains to be tested with more chip families
to see if it is sufficiently accurate.
2021-06-10 09:37:30 +02:00
1bb7123156
Add examples for STM32L0
2021-06-09 23:09:48 +02:00
f3d1ac6623
Enable clock for RNG
2021-06-09 13:54:53 +02:00
939ea3bbd0
Reduce generics noise
2021-06-08 17:20:29 +02:00
ed29d82071
Use critical_section
2021-06-08 17:20:29 +02:00
212bda0940
Enable clock for SPI v1 and v3
2021-06-08 17:20:29 +02:00
a57482fddd
Cargo fmt
2021-06-08 17:20:29 +02:00
ee3b82b743
Auto generate SPI v2 clock enable
...
Adds RccPeripheral trait for peripherals implementing clock enable and reset for a given peripheral.
Add macro table generting implementations of RccPeripheral for peripherals with clock set, currently restricted to SPI.
2021-06-08 17:20:29 +02:00
