Commit Graph

15 Commits

Author SHA1 Message Date
16a47a0ad9 Add embassy-lora crate
This crate contains async radio drivers for various lora drivers that
work with embassy timers. The code is imported from Drogue Device (
https://github.com/drogue-iot/drogue-device)

The radio drivers integrate with the async LoRaWAN MAC layer in the
lorawan-device crate.

Also added is an example for the STM32WL55 and for STM32L0 (requires
the LoRa Discovery board) for LoRaWAN. Future work is to make the
underlying radio drivers using fully async SPI when communicating
with the peripheral.
2021-09-30 10:32:24 +02:00
de016e8456 Remove trait_alias, allow(incomplete_features).
trait_alias seems unused. no idea why it's there.
2021-09-03 17:00:58 +02:00
2c992f7010 stm32: move dbgmcu stuff to toplevel config setting, defaulting to true. 2021-08-19 23:50:19 +02:00
cbff0398bb Add IRQ-driven buffered USART implementation for STM32 v2 usart (#356)
* Add IRQ-driven buffered USART implementation for STM32 v2 usart

* Implementation based on nRF UARTE, but simplified to not use DMA to
  avoid complex interaction between DMA and USART.
* Implementation of AsyncBufRead and AsyncWrite traits
* Some unit tests to ring buffer
* Update polyfill version
* Update sub module to get usart IRQ fix
2021-08-16 17:16:49 +02:00
f4950c4449 examples: Consistently use unwrap! in favor of .unwrap()
Unfortunately errors from `embedded_graphics` and `core` doesn't provide
the necessary instances currently.
2021-08-05 22:39:59 +02:00
0ea6a2d890 time: replace dyn clock/alarm with a global Driver trait 2021-08-05 19:14:09 +02:00
07d4b196f7 Update nightly, remove removed features. 2021-08-04 19:48:14 +02:00
a1a5acb825 rustfmt everything 2021-08-04 15:25:21 +02:00
6ff0614cb6 Add uart::Read DMA-based implementation
* Rename existing read() to bread() (blocking)
2021-08-03 15:31:24 +02:00
cad43587e6 stm32l0: Use embassy::main for examples 2021-07-29 17:37:32 +02:00
638235e72d Fix up the L0 example for SPI. 2021-07-23 13:22:39 -04:00
0eaadfc125 stm32: Update gpio examples 2021-06-25 18:16:43 -03:00
b6a8703698 Add support for generating PAC for dual cores
* Chips that have multiple cores will be exposed as chipname_corename,
  i.e. stm32wl55jc_cm4
* Chips that have single cores will use the chip family as feature name
  and pick the first and only core from the list
* Add support for stm32wl55 chip family
2021-06-16 15:12:07 +02:00
95532726b2 Add minimal RCC impls for L4 and F4 2021-06-14 11:33:11 +02:00
1bb7123156 Add examples for STM32L0 2021-06-09 23:09:48 +02:00