Commit Graph

630 Commits

Author SHA1 Message Date
bors[bot]
77c2b151c2
Merge #715
715: stm32/dac: Check proper channel r=Dirbaio a=michalsrb

Small fix. Otherwise it panics when trying to use channel 1 if channel 2 does not exist.

Co-authored-by: Michal Srb <michalsrb@gmail.com>
2022-04-12 20:57:36 +00:00
Matous Hybl
371f3ef419 Add ADC support for H7 2022-04-12 22:25:00 +02:00
Michal Srb
c1914a477d stm32/dac: Check proper channel 2022-04-12 12:49:06 +02:00
Philip A Reimer
d8860c0b80 add stm32l4 hsi48 and usb example 2022-04-09 14:55:03 -06:00
Dario Nieuwenhuis
8b757e1aec Add stm32wlexx support 2022-04-08 03:43:58 +02:00
Dario Nieuwenhuis
50ff63ab88 Add STM32L5 support. 2022-04-08 03:11:38 +02:00
Matous Hybl
eb6910fa86 Reexport unborrow macro in HALs 2022-04-07 12:57:02 +02:00
Philip A Reimer
1f59f8e7d0 add pllsai1 and allow for 120Mhz clock on stm32l4+ 2022-04-01 22:42:43 -06:00
chemicstry
d052631118 Fix STM32 timer interrupt bug 2022-03-30 00:27:33 +03:00
Joonas Javanainen
a608d0deaf
Add minimal STM32F2 RCC
No support for PLL or other clocks than SYSCLK/AHB/APB1/APB2
2022-03-27 18:40:49 +03:00
bors[bot]
37ada65a33
Merge #669
669: Add SDMMC v1 and SDIO support r=Dirbaio a=chemicstry

SDMMC v2 peripheral is an extension of SDMMC v1 (or SDIO) so I managed to reuse most of the code, with some cfg's.

Apart from small differeces in registers, the biggest change is that v2 uses internal DMA, while v1 has to use shared DMA peripheral. This makes code a bit uglier, because DMA channel for v1 has to be passed around. Not sure if it's possible to make it any cleaner.

This also adds `TransferOptions` structure to DMA, because SDMMC v1 requires setting peripheral flow control and burst transfers. Let me know if some alternative way would be prefered.

I tested this on STM32F429ZIT6 (with sd card) and STM32H745ZIT6 (with oscilloscope).

Depends on: https://github.com/embassy-rs/stm32-data/pull/130

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-03-20 20:19:58 +00:00
bors[bot]
f0a071790d
Merge #673
673: Inline GPIO functions r=Dirbaio a=nviennot

All GPIO functions are monomorphized (per pin). Inlining these make the ROM smaller when using opt-level="z"

Co-authored-by: Nicolas Viennot <nicolas@viennot.biz>
2022-03-19 20:34:07 +00:00
Nicolas Viennot
4aba87f983 Inline GPIO functions
All GPIO functions are monomorphized (per pin). Inlining these make the
ROM smaller when using opt-level="z"
2022-03-19 14:06:11 -04:00
chemicstry
bdeb537ffa Fix compile for stm32wb 2022-03-18 01:33:39 +02:00
chemicstry
b30a42aff8 Fix RCC safety and add reset to DAC 2022-03-18 01:16:07 +02:00
chemicstry
ca88ace98d Reset peripherals on enable 2022-03-18 00:46:46 +02:00
chemicstry
d26b751edc Add comments 2022-03-17 19:41:44 +02:00
chemicstry
051c6350ea Make UART futures Send 2022-03-17 18:23:47 +02:00
chemicstry
24a9e19062 More cleanup 2022-03-17 01:12:29 +02:00
chemicstry
9d71acc49e Cleanup 2022-03-16 23:55:07 +02:00
chemicstry
ea467e0acb Rename DMA trait 2022-03-16 20:30:57 +02:00
chemicstry
8a8e5c4b73 Fix SDMMC v2 and add H7 example 2022-03-16 20:20:39 +02:00
chemicstry
48fc48ea7d Fix BDMA 2022-03-16 19:41:34 +02:00
chemicstry
bf4a38ac06 Use RCC frequency instead of config 2022-03-16 19:09:37 +02:00
chemicstry
6d547b1143 SDIO working on stm32f4 2022-03-16 18:52:27 +02:00
chemicstry
34b5175d2c Add more options to DMA 2022-03-16 18:52:06 +02:00
chemicstry
2d224cf6a0 Update 2022-03-15 19:58:19 +02:00
Ulf Lilleengen
e09bde9345 Add support for splitting stm32 usart into TX and RX
* Keeps existing API for usart, but wraps it in Tx and Rx sub-types
* Adds split() method similar to nRF for getting indepdendent TX and RX
  parts
* Implements e-h traits for TX and RX types
* Add stm32h7 example
2022-03-15 10:35:37 +01:00
Dario Nieuwenhuis
1dc618f0e4 stm32/spi: fix blocking transfer hanging after async. 2022-03-15 04:13:33 +01:00
Grant Miller
49ef19c0b2 stm32/spi: Clear rx fifo in blocking methods 2022-03-14 21:55:37 -05:00
Dario Nieuwenhuis
059b164234 stm32/spi: do not clear rxfifo in SPIv3, the hw already does it. 2022-03-15 02:37:08 +01:00
Dario Nieuwenhuis
4579192832 stm32/spi: fix hang in SPIv3 by not waiting for rxfifo empty in finish_dma. 2022-03-15 02:36:34 +01:00
Dario Nieuwenhuis
306110f56e stm32/spi: implement async trasnfer_in_place 2022-03-15 00:40:48 +01:00
Grant Miller
f1d6c95205 rustfmt 2022-03-14 18:22:41 -05:00
Grant Miller
71632648c7 Fix zero-length-slice bugs 2022-03-14 18:14:55 -05:00
Grant Miller
15c533fe2a Fix async write bug 2022-03-14 18:04:31 -05:00
Grant Miller
6e00c58854 Make all functions generic over word size 2022-03-14 16:53:50 -05:00
Grant Miller
f0b62bc8e0 Use const REGS 2022-03-14 15:56:08 -05:00
Grant Miller
482ffea4dd Finish unification 2022-03-14 15:56:08 -05:00
Grant Miller
406b1b3dd2 Finish matching versions 2022-03-14 15:56:08 -05:00
Grant Miller
7cd6f00a90 Add set_txdmaen and set_rxdmaen functions 2022-03-14 15:56:08 -05:00
Grant Miller
444b37fcdf Add flush_rx_fifo function 2022-03-14 15:56:08 -05:00
Grant Miller
683c11f399 Call set_word_size before disabling SPE 2022-03-14 15:56:08 -05:00
Dario Nieuwenhuis
9bad9365dc Update rust nightly, embedded-hal 1.0, embedded-hal-async. 2022-03-11 00:38:07 +01:00
Dario Nieuwenhuis
77841a4676 stm32/dma: panic on DMA error. 2022-03-09 03:19:05 +01:00
Grant Miller
8c45c98e41 stm32: Refactor DMA interrupts
Previously, every dma interrupt handler called the same `on_irq`
function which had to check the state of every dma channel.

Now, each dma interrupt handler only calls an `on_irq` method for its
corresponding channel or channels.
2022-03-08 14:18:31 -06:00
Timo Kröger
372b71890d [can] Typo fix: l7 -> f7 2022-03-05 09:46:06 +01:00
Timo Kröger
d6d25e6470 [can] cfgs for naming inconsistencies
Approach is similar to USB OTG.
STM32L49x and STML4Ax have CAN1 and CAN2.
All others STM32L4xx do only have CAN1.
STM32F72x and STM32F73x are the only F7 devices with only CAN1.
2022-03-05 09:46:06 +01:00
Timo Kröger
6929350552 [can] Update macrotable comment
The chip description are corrected in:
https://github.com/embassy-rs/stm32-data/pull/123
2022-03-05 09:46:06 +01:00
Timo Kröger
4c30543938 [can] Do not use wildcard reexport for bxcan 2022-03-05 09:46:06 +01:00