840a75674b
rp: Disable RX interrupts when ring buffer is full
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When data is in the RX fifo the RX timeout interrupt goes high again even after clearing it.
The result is a deadlock because execution is stuck in the interrupt handler. No other code
can run to clear the receive buffer.
Enable and disable RX interrupts based on the buffer fill level.
Use the same approach for the TX code path.
2023-01-04 16:53:43 +01:00
a24037edf9
rp: Fix BufferedUart drop code
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Only unregister the interrupt handler when both parts are inactive
2023-01-04 15:59:03 +01:00
68c186309f
rp: Common init function for BufferedUart
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BufferedUart, BufferedUartRx and BufferedUartTX can all use the same init code.
2023-01-04 15:58:26 +01:00
e4f457646f
rp: Fill and empty FIFOs in buffered uart interrupt
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Fixes an issue where only the first byte was transmitted.
Should improve throughput aswell.
2022-12-27 11:28:52 +01:00
aa92ce6dc7
embassy-rp: Add split() to BufferedUart
2022-12-22 23:03:05 +01:00
7b838d0336
rp/uart: use lockfree ringbuffer.
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This gets rid of another PeripheralMutex usage.
2022-11-25 22:30:47 +01:00
1e2fb0459d
Switch to async-fn-in-trait
2022-11-25 21:02:06 +01:00
eeb072d9cb
Update Rust nightly.
2022-10-26 16:47:29 +02:00
e129a97d48
Fix bufferedUart read and write tests
2022-09-27 07:45:10 +02:00
65907204d6
Rename from {Rx,Tx}BufferedUart to BufferedUart{Rx,Tx} to be compliant with stm32 and nrf implementations
2022-09-27 05:51:31 +02:00
b743d9f48c
Add HIL test for bufferedUart
2022-09-26 05:32:45 +02:00
1d3e41f970
Remove code-duplication in async bufferedUart implementations
2022-09-21 06:00:35 +02:00
31d85da78a
Add bufferedUart, including a split version for only Rx or Tx
2022-09-09 10:48:52 +02:00
9611e7c9f2
Add BufferedUart implementation, and feature-guard time-driver initialization, to free up TIMER peripheral if not used with embassy executor
2022-09-09 10:48:30 +02:00
