Commit Graph

5364 Commits

Author SHA1 Message Date
e36e36dab6 Merge #507
507: Stm32 data upate 4 r=Dirbaio a=Dirbaio

Main imrpvement is RCC regs info comes from yamls now.

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-29 01:28:24 +00:00
b0fabfab5d Update stm32-data: rcc regs info comes from yamls now. 2021-11-29 02:28:02 +01:00
3332c40705 examples: remove unused deps. 2021-11-29 02:07:48 +01:00
2a2911221d Merge #506
506: Clock cleaning r=Dirbaio a=lulf

Different STM32 RCC peripherals have different capabilities and register values. Define types for each RCC types inside each module to ensure full range of capabilities for each family can be used

Co-authored-by: Ulf Lilleengen <ulf.lilleengen@gmail.com>
2021-11-28 19:41:16 +00:00
25b49a8a2a Remove common clock types
Different STM32 RCC peripherals have different capabilities and register
values. Define types for each RCC types inside each module to ensure
full range of capabilities for each family can be used
2021-11-28 16:46:08 +01:00
1b24b3bd68 Make ci script run on Mac OS X 2021-11-28 14:07:21 +01:00
543cc65e56 Merge #449
449: STM32: Add PWM support r=Dirbaio a=bgamari

Here is a first-cut at implementing PWM support for STM32 targets via the TIM peripherals. Currently this only contains pin configuration for the STM32G0 but it would be straightforward to extend to other platforms.

Co-authored-by: Ben Gamari <ben@smart-cactus.org>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-27 02:07:43 +00:00
006e567716 stm32/pwm: allow using the advanced timer instances too. 2021-11-27 03:06:53 +01:00
e40555e245 examples/stm32g4: add pwm example 2021-11-27 03:06:46 +01:00
d7d1258411 stm32/pwm: small cleanups 2021-11-27 03:05:10 +01:00
22fad1e7bc stm32/pwm: impl instance/pin for all chips 2021-11-27 03:04:50 +01:00
8211d58ee2 stm32/pwm: initial commit 2021-11-27 02:50:30 +01:00
793f4b1f7d Merge #505
505: stm32: add stm32g4 support. r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-27 01:44:23 +00:00
88d4b0c00d stm32: add stm32g4 support. 2021-11-27 02:34:23 +01:00
c7d9729028 Merge #486
486: Pwm ppi events r=Dirbaio a=jacobrosenthal

More PWM yak shaving. I was going to do some safe pwm ppi events stuff but I just dont think it fits this api design.. ppi is just very low level, im not sure how safe it will be in general

* first we should probably have borrows of handlers for ppi with lifetime of the peripheral?  hal does eb4ba6ae42/nrf-hal-common/src/pwm.rs (L714-L716)
* in general having access to tasks can put the state in some configuration the api doesnt understand anymore. for `SequencePwm` ideally id hand you back either only seq_start0 or seq_start1 because youd only use one based on if your `Times` is even or odd.. but again we only know that with this api AFTER start has been called. I dont think were ready for typestates

SO I figured why not add the pwm ppi events but make them unsafe and commit this example since I started it.

Somewhat related drop IS removing the last duty cycle from the pin correctly, but stop DOES NOT..the only thing that sets the pin back is pin.conf() as far as I can tell, so I tried to document that better and got rid of stop for the `SimplePwm` again since that doesnt need it then. However its ackward we dont have a way to unset the pwm without setting a new sequence of 0s, or dropping the peripheral


Co-authored-by: Jacob Rosenthal <jacobrosenthal@gmail.com>
2021-11-26 23:08:24 +00:00
524eed5db5 Update smoltcp, fix build issues with no ethernet. 2021-11-26 21:09:44 +01:00
6aa27d1a8e Merge #504
504: net: update smoltcp r=Dirbaio a=Dirbaio

What it says on the tin

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-26 03:15:54 +00:00
c257893da9 net: update smoltcp 2021-11-26 04:12:14 +01:00
539c007b44 Merge #502
502: Ensure SPI DMA write is completed r=lulf a=lulf

Fix a bug where DMA writes were not fully completed and only a single
byte out of two were written.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2021-11-24 20:02:49 +00:00
32d52c89a9 Merge #503
503: net: don't depend directly on smoltcp outside embassy-net r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-24 19:22:04 +00:00
e4de15e4de net: don't depend directly on smoltcp outside embassy-net 2021-11-24 17:48:48 +01:00
cd9a1d547c Ensure SPI DMA write is completed
Fix a bug where DMA writes were not fully completed and only a single
byte out of two were written.
2021-11-24 14:59:18 +01:00
8fea6c94f6 Merge #501
501: stm32-metapac cleanups r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-24 01:00:22 +00:00
f9934fb56b ci: do main build with fully generated stm32-metapac. 2021-11-24 01:43:53 +01:00
e187f50f4b stm32: remove unused deps 2021-11-24 01:41:51 +01:00
78d109f5d5 stm32-metapac: add pac feature to allow building only the macrotables. 2021-11-24 01:04:23 +01:00
d06cb0a264 stm32-metapac-gen: use actually common common.rs instead of emitting it at every single chip file. 2021-11-24 00:42:14 +01:00
e725d22fd4 Merge #489
489: Faster CI with cargo-batch r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-23 23:24:27 +00:00
dfb6d407a1 stm32: rename core features from _cmX to -cmX, cleanup gen. 2021-11-23 23:49:06 +01:00
b0da114395 Merge #491
491: Fix interrupt_take macro by specifying path to panic macro. r=Dirbaio a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2021-11-23 14:34:15 +00:00
0ca6060bfd Fix interrupt_take macro by specifying path to panic macro. 2021-11-23 11:00:37 +01:00
d98d18d2ee Merge #499
499: Update to latest stm32-data r=Dirbaio a=lulf



Co-authored-by: Ulf Lilleengen <ulf.lilleengen@gmail.com>
2021-11-22 12:33:09 +00:00
a6a744d0d9 Update to latest stm32-data 2021-11-22 13:30:53 +01:00
039621c56d stm32-metapac-gen: fix broken build.rs 2021-11-22 02:38:01 +01:00
0db4da10f8 stm32-metapac-gen: separate data structs 2021-11-22 02:37:46 +01:00
5b45dd4eb5 Merge #497
497: Some documentation corrections and expansion r=Dirbaio a=huntc

Some documentation to help us along with `Signal` and `Saadc`.

Co-authored-by: huntc <huntchr@gmail.com>
2021-11-22 01:28:00 +00:00
d4179ee2e4 Some documentation corrections and expansion 2021-11-22 12:26:11 +11:00
c8e69a14eb Faster CI with cargo-batch 2021-11-22 01:25:07 +01:00
10a3a8bbed Merge #496
496: Fix warning for field never used. r=Dirbaio a=ithinuel



Co-authored-by: Wilfried Chauveau <wilfried.chauveau@ithinuel.me>
2021-11-21 20:02:14 +00:00
d7bbaf1a4c Merge #494
494: nrf: saadc do not reexport pac enums r=Dirbaio a=jacobrosenthal

Closes #415

Co-authored-by: Jacob Rosenthal <jacobrosenthal@gmail.com>
2021-11-21 19:47:31 +00:00
920bb3690e Merge #495
495: Fix missing lifetime bounds r=lulf a=ithinuel



Co-authored-by: Wilfried Chauveau <wilfried.chauveau@ithinuel.me>
2021-11-21 11:10:44 +00:00
d5a2462cba Update embassy-nrf with lifetime bounds on gpio implementations. 2021-11-21 10:25:43 +00:00
eac604accd Fix missing lifetime bounds 2021-11-21 10:10:28 +00:00
e6abd9f5df Fix warning for field never used. 2021-11-21 08:33:18 +00:00
18d94a7d01 nrf: saadc do not reexport pac enums
Closes #415
2021-11-20 18:07:20 -07:00
8d108d8753 Merge #493
493: Update stm32-data r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-17 20:43:52 +00:00
24e5013c00 Allow unused to fix build failure in u5 2021-11-17 21:43:05 +01:00
63688bf61f Update stm32-data 2021-11-17 21:31:37 +01:00
5754be5d1e Merge #492
492: Adjust the config.toml for U5. r=Dirbaio a=bobmcwhirter

- Correct ISA
- Remove commented-out cruft.

Co-authored-by: Bob McWhirter <bmcwhirt@redhat.com>
2021-11-17 15:37:00 +00:00
2649984b55 Adjust the config.toml for U5.
- Correct ISA
- Remove commented-out cruft.
2021-11-17 10:35:25 -05:00