Commit Graph

6352 Commits

Author SHA1 Message Date
Mehmet Ali Anil
935633c90b Merge upstream 2023-03-07 23:16:54 +01:00
bors[bot]
bd4c4209af
Merge #1265
1265: nrf/uicr: only check lowest bit. r=Dirbaio a=Dirbaio

This mirrors what nrfx does. Also it won't reboot/warn if NFCPINS is set to either 0xFFFF_FFFE or 0x0000_0000, which are all valid.


bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-03-07 14:30:22 +00:00
Dario Nieuwenhuis
27e989afa9 nrf/uicr: only check lowest bit.
This mirrors what nrfx does. Also it won't reboot/warn if NFCPINS is set to either
0xFFFF_FFFE or 0x0000_0000, which are all valid.
2023-03-07 15:28:27 +01:00
Mehmet Ali Anil
b0e26440ee Merge upstream 2023-03-07 10:47:56 +01:00
Mehmet Ali Anil
bc0cb43307 Bump embedded-storage-async to 0.4 2023-03-06 22:16:36 +01:00
Leon Camus
c22218c72e feat: Add multicast to udp socket 2023-03-06 18:43:37 +01:00
Dario Nieuwenhuis
18fe398673
Merge pull request #1224 from embassy-rs/interrupt-binding
nrf: new interrupt binding traits/macro
2023-03-06 00:41:47 +01:00
Dario Nieuwenhuis
f5e09a8f4a nrf/interrupt: do not reexport take! macro. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
5249996d28 nrf/usb: switch to new interrupt binding, fix vbus detect on nrf53. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
5913553cb1 nrf/twis: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
36319fc121 nrf/temp: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
9e58d9274c nrf/twim: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
9f5762d365 nrf/spis: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
a32e82029a nrf/spim: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
2dc5608203 nrf/saadc: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
d113fcfe32 nrf/rng: make available on all chips, use Instance trait, switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
96788ac93a nrf/qspi: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
c66b28e759 nrf/qdec: make available on all chips, use Instance trait, switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
f8f1d3bcf0 nrf/pdm: make available on all chips, use Instance trait, switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
34563b74aa nrf/i2s: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
63b75eaf64 nrf/timer: remove awaitable. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
9cf000ef4e nrf/uart: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
42c13c8c3d nrf: add new interrupt binding traits and macro. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
a054891263 cortex-m: rename Handler to DynHandler.
I want to use the name Handler for the new interrupt binding macro.
2023-03-06 00:17:51 +01:00
bors[bot]
403a83e08d
Merge #1260
1260: time/ticker: make sure the future for .next() is Unpin. r=Dirbaio a=Dirbaio

It was Unpin before #1248 

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-03-05 22:15:14 +00:00
Dario Nieuwenhuis
c88bbaa5ec time/ticker: make sure the future for .next() is Unpin. 2023-03-05 23:13:22 +01:00
Dario Nieuwenhuis
6dfda69cc4
readme: add embassy-rp 2023-03-05 20:19:18 +01:00
Dario Nieuwenhuis
bf013be9ba
Merge pull request #1232 from embassy-rs/nrf-qspi-fixes
nrf/qspi: nrf53 support, u32 addrs, remove const generic, add raw read/write.
2023-03-05 03:19:11 +01:00
Dario Nieuwenhuis
d91efe3e62
Merge pull request #1208 from embassy-rs/nrf-uarte-lockfree
nrf/buffered_uarte: make it work without rts/cts, and lock-free.
2023-03-05 02:56:15 +01:00
Dario Nieuwenhuis
f7dfc49c5c nrf/qspi: add _raw variants of methods that don't do bounds checks.
Useful for the nRF7002, which presents as a "fake" QSPI flash, and
the "capacity" concept doesn't really apply to it.
2023-03-05 02:55:00 +01:00
Dario Nieuwenhuis
8eb8ea6174 nrf/qspi: remove FLASH_SIZE const generic param. 2023-03-05 02:33:02 +01:00
Dario Nieuwenhuis
75f69803af nrf/qspi: always use u32 for addresses. 2023-03-05 02:30:53 +01:00
Dario Nieuwenhuis
1955a225e8 nrf/qspi: add nrf53 support. 2023-03-05 02:17:59 +01:00
Dario Nieuwenhuis
9eb65b11cb nrf/qspi: remove cfg_if hack 2023-03-05 02:08:29 +01:00
Dario Nieuwenhuis
7650fea5f2 nrf/buffered_uarte: add HIL tests. 2023-03-04 15:12:49 +01:00
Dario Nieuwenhuis
916f94b366 nrf/buffered_uarte: make available on stable. 2023-03-04 15:12:49 +01:00
Dario Nieuwenhuis
ccc224c81f nrf/buffered_uarte: remove PeripheralMutex, make it work without rts/cts.
> dirbaio: so I was checking how zephyr does UARTE RX on nRF
> dirbaio: because currently we have the ugly "restart DMA on line idle to flush it" hack
> dirbaio: because according to the docs "For each byte received over the RXD line, an RXDRDY event will be generated. This event is likely to occur before the corresponding data has been transferred to Data RAM."
> dirbaio: so as I understood it, the only way to guarantee the data is actually transferred to RAM is to stop+restart DMA
> dirbaio: well, guess what?
> dirbaio: they just count RXDRDY's, and process that amount of data without restarting DMA
> dirbaio: with a timer configured as counter https://github.com/zephyrproject-rtos/zephyr/blob/main/drivers/serial/uart_nrfx_uarte.c#L650-L692
> dirbaio: 🤔🤷⁉️
> dirbaio: someone saying you can do the "hook up rxdrdy to a counter" trick, someone else saying it's wrong 🤪 https://devzone.nordicsemi.com/f/nordic-q-a/28420/uarte-in-circular-mode

So we're going to do just that!

- BufferedUarte is lock-free now. No PeripheralMutex.
- The "restart DMA on line idle to flush it" hack is GONE. This means
  - It'll work correctly without RTS/CTS now.
  - It'll have better throughput when using RTS/CTS.
2023-03-04 15:12:49 +01:00
Dario Nieuwenhuis
bef559307c
Merge pull request #1259 from dalegaard/master
embassy_usb: Add split() for cdc_acm
2023-03-04 15:08:02 +01:00
Lasse Dalegaard
7b9075130e embassy_usb: Add split() for cdc_acm 2023-03-04 10:36:10 +01:00
Dario Nieuwenhuis
51478caad8 nrf/timer: add support for counter mode. 2023-03-04 05:37:33 +01:00
Dario Nieuwenhuis
4314b823aa nrf: add PPI channel group driver. 2023-03-04 05:37:33 +01:00
Dario Nieuwenhuis
78d733fc73
Merge pull request #1258 from CBJamo/rp-gpio-loglevel
Swap debug! for trace! in rp gpio
2023-03-02 22:18:01 +01:00
Caleb Jamison
7bdb3abad7 Swap debug! for trace! in rp gpio
When using gpio pin changes for things like peripheral interrupts these
debug! calls flood defmt, making it difficult to find what you're
actually looking for.
2023-03-02 13:59:52 -05:00
Dario Nieuwenhuis
14ed0b90b8
Merge pull request #1257 from MabezDev/docs/add-esp-hal
docs: add esp-hal
2023-03-02 17:57:39 +01:00
Scott Mabin
64003cdfd6 Add embassy-esp README 2023-03-02 16:56:58 +00:00
Dario Nieuwenhuis
8bd8fbd131
Merge pull request #1256 from pattop/hal_common_atomic_ring_buffer_push_slices
hal-common/atomic_ring_buffer: add push_bufs() push_slices()
2023-03-02 17:26:43 +01:00
Patrick Oppenlander
78974dfeb4 hal-common/atomic_ring_buffer: add push_bufs() push_slices()
This allows a writer to access all of the free space in the buffer, even
when it's wrapping around.
2023-03-02 14:11:49 +11:00
bors[bot]
4ac257adb9
Merge #1255
1255: common: allow atomic ringbuf to fill up to N instead of just N-1. r=Dirbaio a=Dirbaio

Extracted out of #1208. Since I don't think that'll end up using the ringbuf in the end, I've separated it.

This allows the ringbuf to be filled up to `N` instead of just `N-1`, using some fun tricks on the indices. 

The advantage is better performance: Before, the first write would fill N-1 bytes, The second would write just the 1 byte left before wrapping, then N-2. Then 2, then N-3, and so on. This would result in more smaller chunks, so worse perf. This problem is gone now.

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-03-02 00:01:49 +00:00
Dario Nieuwenhuis
f95aafc90e common: allow atomic ringbuf to fill up to N instead of just N-1.
This allows the ringbuf to be filled up to `N` instead of just `N-1`, using some fun tricks on the indices.

The advantage is better performance: Before, the first write would fill N-1 bytes, The second would write just the 1 byte left before wrapping, then N-2. Then 2, then N-3, and so on. This would result in more smaller chunks, so worse perf. This problem is gone now.
2023-03-02 01:01:19 +01:00
Dario Nieuwenhuis
c4f4aa10f9
Merge pull request #1244 from embassy-rs/interruptexecutor
cortex-m/executor: don't use the owned interrupts system.
2023-03-01 22:38:27 +01:00