Commit Graph

4883 Commits

Author SHA1 Message Date
Davide Della Giustina
3c601bf8d2
PacketQueue::init() does not need to be unsafe 2023-02-28 18:04:43 +00:00
Davide Della Giustina
485bb76e46
Implemented suggestions from @Dirbaio 2023-02-28 17:39:02 +00:00
bors[bot]
d719f8bc03
Merge #1248
1248: embassy-time: add async tick() method to Ticker r=Dirbaio a=kbleeke

Small QOL change so you don't have to add a direct dependency on futures-util to use the Ticker

Co-authored-by: kbleeke <pluth@0t.re>
2023-02-28 17:12:13 +00:00
kbleeke
4e212c7a0b embassy-time: add async tick() method to Ticker 2023-02-28 17:25:42 +01:00
Davide Della Giustina
c1e93c0904
PacketQueue::new() uses ::init() when in nightly 2023-02-28 14:34:26 +00:00
Davide Della Giustina
90f2939bf6
Added PacketQueue::init() 2023-02-28 14:22:54 +00:00
Lachezar Lechev
5cb0c8cc01
fix: rp - disable Pull-down/up resistors for ADC read
Signed-off-by: Lachezar Lechev <elpiel93@gmail.com>
2023-02-28 09:22:38 +02:00
bors[bot]
28b695e7c9
Merge #1243
1243: RP-PICO UART adding set_baudrate r=Dirbaio a=andres-hurtado-lopez

The following PR attepts to bring fuctionality to allow change od UART baudrate changes during runtime.

Changes where created under `@Dirbaio` supervision and discussed on issue:

[https://github.com/embassy-rs/embassy/issues/1241#issuecomment-1445500175]( https://github.com/embassy-rs/embassy/issues/1241#issuecomment-1445500175)

Co-authored-by: Andres Hurtado Lopez <andresh@cultivate-agri.com>
2023-02-27 02:26:20 +00:00
Andres Hurtado Lopez
2331d58aa6 RP-PICO UART adding set_baudrate: missing to run rust-fmt 2023-02-26 21:23:51 -05:00
Andres Hurtado Lopez
482ba835c4 RP-PICO UART adding set_baudrate: Changing static call from specific type to a Self (requires adding lifetime specifier) 2023-02-26 19:20:08 -05:00
Andres Hurtado Lopez
7172dfd083 RP-PICO UART adding set_baudrate: refactoring of methods 2023-02-26 19:14:25 -05:00
Andres Hurtado Lopez
8fb380b180 RP-PICO UART adding set_baudrate 2023-02-26 18:40:23 -05:00
Dario Nieuwenhuis
bc71230cd0 examples/std: fix net running out of sockets. 2023-02-26 21:50:12 +01:00
bors[bot]
5367baa845
Merge #1238
1238: embassy-net: DNS resolver detects when name is just an IP address r=lulf a=kbleeke

fixes #1237 

I am not sure, if this is the right place to put this code. Alternatively, It could be in dns::DnsSocket or reqwless (and all other libraries that need to maybe resolve hostnames).

Are there other DNS query-types where it would make sense to try to parse an IP address?

Co-authored-by: kbleeke <pluth@0t.re>
2023-02-26 08:22:38 +00:00
kbleeke
d5f88e578c embassy-net: DNS resolver detects when name is just an IP address and returns immediately 2023-02-25 21:52:15 +01:00
bors[bot]
64247ae456
Merge #1236
1236: Add `#[must_use]` to all futures r=Dirbaio a=GrantM11235

I think that's all of them, I just grep'd for `impl.* Future for`

Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2023-02-24 19:20:32 +00:00
Grant Miller
7be4337de9 Add #[must_use] to all futures 2023-02-24 13:01:41 -06:00
bors[bot]
2209bef4f2
Merge #1231
1231: embassy-time: Implement conversions to/from core::time::Duration for embassy-time::Duration r=Dirbaio a=kbleeke

I chose microseconds for the conversion as the lowest resolution that embassy provides. A new Error-type did not seem that useful but I can add one, if necessary.

Co-authored-by: kbleeke <pluth@0t.re>
2023-02-23 18:33:47 +00:00
kbleeke
43a4409405 embassy-time: Implement conversions to/from core::time::Duration for embassy-time::Duration 2023-02-23 19:25:22 +01:00
bors[bot]
3255e0a172
Merge #1228
1228: stm32/sdmmc: Implement proper clock configuration r=chemicstry a=chemicstry

This implements proper clock configuration for sdmmc based on chip family, because `RccPeripheral::frequency()` is almost always incorrect. This can't be fixed in PAC, because sdmmc uses two clock domains, one for memory bus and one for sd card. `RccPeripheral::frequency()` usually returns the memory bus clock, but SDIO clock calculations need sd card domain clock. Moreover, chips have multiple clock source selection bits, which makes this even more complicated. I'm not sure if it's worth implementing all this logic in `RccPeripheral::frequency()` instead of cfg's in sdmmc.

Some chips (Lx, U5, H7) require RCC updates to expose required clocks. I didn't want to mash everything in a single PR so left a TODO comment. I also left a `T::frequency()` fallback, which seemed to work in H7 case even though the clock is most certainly incorrect.

In addition, added support for clock divider bypass for sdmmc_v1, which allows reaching a maximum clock of 48 MHz. The peripheral theoretically supports up to 50 MHz, but for that ST recommends setting pll48 frequency to 50 MHz 🤔

Co-authored-by: chemicstry <chemicstry@gmail.com>
2023-02-23 16:22:31 +00:00
chemicstry
73ef85b765 stm32/sdmmc: Fix compile errors 2023-02-23 18:00:55 +02:00
bors[bot]
f0f92909c1
Merge #1227
1227: stm32/dma: fix spurious transfer complete interrupts r=Dirbaio a=pattop

DMA interrupts must be acknowledged by writing to the DMA_{L,H}IFCR
register.

Writing to the CR register is unnecessary as the channel (EN bit) is
disabled by hardware on completion of the transfer.


Co-authored-by: Patrick Oppenlander <patrick.oppenlander@gmail.com>
2023-02-23 15:44:43 +00:00
chemicstry
896764bb85 stm32/sdmmc: Refactor TypeId into a macro 2023-02-23 17:38:52 +02:00
chemicstry
42462681bd stm32/sdmmc: Implement proper clock configuration 2023-02-23 16:57:21 +02:00
Patrick Oppenlander
4e884ee2d2 stm32/dma: fix spurious transfer complete interrupts
DMA interrupts must be acknowledged by writing to the DMA_{L,H}IFCR
register.

Writing to the CR register is unnecessary as the channel (EN bit) is
disabled by hardware on completion of the transfer.
2023-02-23 10:12:48 +11:00
bors[bot]
dda5a4cc9d
Merge #1225
1225: nrf: rename UARTETWISPIn -> SERIALn r=Dirbaio a=Dirbaio

The UARTETWISPIn naming is quite horrible. With the nRF53, Nordic realized this and renamed the interrupts to SERIALn. Let's copy that for our peripheral names, in nrf53 and nrf91.

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-02-22 14:43:17 +00:00
bors[bot]
464faa2a04
Merge #1226
1226: embassy-net: Implement flush for TcpSocket r=Dirbaio a=kbleeke

Implements flush for TcpSocket by checking the send queue. 

Flushing is implemented by checking if smoltcp's send_queue/tx_buffer is empty. The flush is completed when all outstanding octets are acknowledged. Smoltcp wakes the send waker [here](https://docs.rs/smoltcp/latest/src/smoltcp/socket/tcp.rs.html#1712) when ACKs are processed and data is removed from the send buffer. So we can re-check in our flush implementation, if the buffer is now empty.

fixes #1223



Co-authored-by: kbleeke <pluth@0t.re>
2023-02-22 14:27:19 +00:00
kbleeke
035de6f3ff embassy-net: add flush to TcpSocket and TcpWriter as an inherent method 2023-02-22 14:45:17 +01:00
kbleeke
f1a4db44c4 Implement flush for TcpSocket 2023-02-22 13:57:40 +01:00
Dario Nieuwenhuis
ada3d5be7c nrf: rename UARTETWISPIn -> SERIALn
The UARTETWISPIn naming is quite horrible. With the nRF53, Nordic realized this
and renamed the interrupts to SERIALn. Let's copy that for our peripheral names, in nrf53 and nrf91.
2023-02-21 22:41:23 +01:00
Pol Fernandez
f6f041b05d Add from_utf8 2023-02-21 08:52:57 +01:00
Pol Fernandez
f34829f534 Add stringify function 2023-02-20 21:03:39 +01:00
bors[bot]
b05cd77a62
Merge #1170
1170: nrf: add support for UICR configuration. r=Dirbaio a=Dirbaio

- APPROTECT enable/disable. Notably this fixes issues with nrf52-rev3 and nrf53 from locking itself at reset.
- Use NFC pins as GPIO.
- Use RESET pin as GPIO.

NFC and RESET pins singletons are made available only when usable as GPIO, for compile-time checking.

TODO: test
- [x] nrf52 rev1
- [x] nrf52 rev3
- [x] nrf53
- [x] nrf91

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-02-20 00:47:15 +00:00
Dario Nieuwenhuis
7fa478358a nrf: warn if uicr configuration could not be written.
If the user requests some configuration, but UICR is already programmed
to something else, detect this and warn the user.

We don't do it for the debug port settings, because if they are wrong
then the user will simply not be able to read debug logs.
2023-02-20 01:31:02 +01:00
Dario Nieuwenhuis
3f88bf6f9b nrf: add support for UICR configuration.
- APPROTECT enable/disable. Notably this fixes issues with nrf52-rev3 and nrf53 from locking itself at reset.
- Use NFC pins as GPIO.
- Use RESET pin as GPIO.

NFC and RESET pins singletons are made available only when usable as GPIO,
for compile-time checking.
2023-02-20 01:28:45 +01:00
bors[bot]
a2bd37be40
Merge #1221
1221: examples/stm32wb: do not reserve words at start of RAM. r=Dirbaio a=Dirbaio

They're used to communicate from the app to ST's OTA bootloader. See AN5247. 

This bootloader is optional, must be flashed by the user, and requires changing the FLASH start address as well, so the current memory regions still require modifications to use it. Therefore there's no point in reserving these words.

Thanks `@adamgreig` for investigating the purpose.

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-02-20 00:01:22 +00:00
Dario Nieuwenhuis
13328c58d3
examples/stm32wb: do not reserve words at start of RAM.
They're used to communicate from the app to ST's OTA bootloader. See AN5247. 

This bootloader is optional, must be flashed by the user, and requires changing the FLASH start address as well, so the current memory regions still require modifications to use it. Therefore there's no point in reserving these words.

Thanks @adamgreig for investigating the purpose.
2023-02-20 01:01:01 +01:00
bors[bot]
1567e724f9
Merge #1218 #1219
1218: Lora: sx126x: Change timing window to match values found experimentally. r=Dirbaio a=CBJamo

As mentioned in #1188.

1219: stm32/sdmmc: Fix SDIOv1 writes r=Dirbaio a=chemicstry

This fixes writes on sdmmc v1 (SDIO). I'm pretty sure I tested writes in #669, but maybe I was just lucky or I just forgot.

There were two problems:
- Writes require DMA FIFO mode, otherwise SDIO FIFO is under/overrun depending on sdio/pclk2 clock ratio.
- Hardware flow control is broken for sdmmc v1 (I checked F1 and F4 erratas). This causes clock glitches above 12 MHz and results in write CRC errors.

Co-authored-by: Caleb Jamison <caleb@cbjamo.com>
Co-authored-by: chemicstry <chemicstry@gmail.com>
2023-02-19 23:01:44 +00:00
bors[bot]
4ad255b34b
Merge #1217
1217: Fix a typo in "PioPeripheral" r=Dirbaio a=SekoiaTree

Renames "PioPeripherial" to "PioPeripheral" (without the second i).

Co-authored-by: sekoia <sequoia.1009@gmail.com>
2023-02-19 22:46:57 +00:00
bors[bot]
4fd59f26fb
Merge #1220
1220: examples/stm32wb: fix linker script. r=Dirbaio a=Dirbaio

cortex-m-rt 0.7.2 now enforces the stack is 8-byte aligned. Stack is placed at `ORIGIN(RAM) + LENGTH(RAM)` by default, which wasn't 8-byte-aligned. See https://github.com/rust-embedded/cortex-m/discussions/469

ST trims 8 bytes from start of RAM, and uses the whole 192kb, so let's just copy that:

bceb1dae09/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb55xx_flash_cm4.ld (L48)

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-02-19 22:03:13 +00:00
Dario Nieuwenhuis
272982ee54 examples/stm32wb: fix linker script.
cortex-m-rt 0.7.2 now enforces the stack is 8-byte aligned. Stack is placed
at `ORIGIN(RAM) + LENGTH(RAM)` by default, which wasn't 8-byte-aligned. See https://github.com/rust-embedded/cortex-m/discussions/469

ST trims 8 bytes from start of RAM, and uses the whole 192kb, so let's just
copy that:

bceb1dae09/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb55xx_flash_cm4.ld (L48)
2023-02-19 23:02:31 +01:00
chemicstry
a53f525f51 stm32/sdmmc: Fix SDIOv1 writes 2023-02-18 01:37:06 +02:00
Caleb Jamison
7783e0ebb1 Change timing window to match values found experimentally. 2023-02-17 07:43:19 -05:00
sekoia
e641db1f75 Fix a typo in "PioPeripheral" 2023-02-15 14:10:07 +01:00
Dario Nieuwenhuis
e3492862e9
Merge pull request #38 from overheat/master
update embassy dependences
2023-02-15 12:34:45 +01:00
Aaron Tsui
0bcd1b1e10 update embassy dependences 2023-02-15 11:08:27 +08:00
bors[bot]
e3f8020c3b
Merge #1215
1215: Add clone to embassy_rp::gpio::Level r=Dirbaio a=Slushee-a

Allows you to wite a cleaner state change detector. Example:
```rs
let mut button_state: Level = Level::Low;
let mut prev_button_state: Level = button_state;

loop {
    button_state = button.get_level();

    if prev_button_state != button_state {
        led.set_level(button_state);  // Takes ownership of button_state. 
    }

    prev_button_state = button_state; // Can't be done since the ownership has been moved.
                                      // Adding Clone makes this code possible
}
```

Co-authored-by: Slushee <55996847+Slushee-a@users.noreply.github.com>
2023-02-13 17:31:47 +00:00
Slushee
dfc58ad3a2
Add copy to Level enum in embassy-rp gpio module 2023-02-13 17:29:35 +00:00
Slushee
1626a4a74b
Add clone to embassy_rp::gpio::Level 2023-02-13 17:12:50 +00:00
Mathias
5e74926907 feature-gate variants without vals defined 2023-02-13 15:46:49 +01:00